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Conrad Murphy
6 years ago
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1 dvanced igital Logic esign EES :32 decoder/demultiplexer Teacher: Robert ick Office: L477 Tech Phone: \EN 5:32 ecoder Subs ys tem \Y31 \Y0 S4 S3 S2 S1 S0... \EN S4 S3 1G G 2 2 1Y3 1Y2 1Y1 1Y0 2Y3 2Y2 2Y1 2Y0 S2 S1 S0 S2 S1 S0 S2 S1 S0 G1 Y7 Y6 G2 G2 Y5 Y4 138 Y3 Y2 Y1 Y0 G1 Y7 G2 Y6 G2 Y5 Y4 138 Y3 Y2 Y1 Y0 G1 Y7 G2 Y6 G2 Y5 138 Y4 Y3 Y2 Y1 Y0 \Y S2 S1 S0 G1 Y7 G2 Y6 G2 Y5 138 Y4 Y3 Y2 Y1 Y \Y0 4 Robert ick dvanced igital Logic esign 5:32 decoder/demultiplexer implementation details Tally circuit example Why is G1 connected to an inverted active-low enable signal? Why are 2, 2, and 2G not connected on the part? What would happen if this design were used and the parts were TTL (I don t expect you to know this one already)? How about MOS? Given n-input circuit ount number of 1s in input Robert ick dvanced igital Logic esign 7 Robert ick dvanced igital Logic esign Tally circuit example Tally circuit example an implement using logic gates an implement using TGs 8 Robert ick dvanced igital Logic esign 9 Robert ick dvanced igital Logic esign Tally circuit example TG tally circuit an implement using TGs 10 Robert ick dvanced igital Logic esign 11 Robert ick dvanced igital Logic esign

2 TG tally circuit 4-input tally I 2 Two Robert ick dvanced igital Logic esign 13 Robert ick dvanced igital Logic esign 4-input tally 4-input tally I 2 Two I 2 Two I 2 I 2 Two Two 14 Robert ick dvanced igital Logic esign 15 Robert ick dvanced igital Logic esign TG tally circuit TG tally circuit I 2 Two I 2 Two 16 Robert ick dvanced igital Logic esign 17 Robert ick dvanced igital Logic esign,, and multi-level minimization Programmable read-only memories (P) Programmable read-only memories (P) Field-programmable gate arrays () Programmable devices for prototyping 2- array of binary values Input: ddress Output: Word 19 Robert ick dvanced igital Logic esign 20 Robert ick dvanced igital Logic esign

3 PROM Implementing logic with P +5V +5V +5V +5V ec n n 1 ddress i j Word Line 0011 Word Line 1010 it Lines F 0 = + + F 1 = + + F 2 = + + F 3 = Robert ick dvanced igital Logic esign 22 Robert ick dvanced igital Logic esign Truth table PROM suitable for implementing example F 3 F 2 F 1 F ddress Word 8 words x 4 bits outputs addresses 23 Robert ick dvanced igital Logic esign 24 Robert ick dvanced igital Logic esign Memory composition Memory composition 2764 EPROM 8K x VPP PGM O7 9 O6 8 O5 7 O4 6 O3 5 O2 4 O1 3 O S OE hip select 13 /OE 12:0 15:8 7: VP P + P GM O7 9 8 O6 O5 7 O4 6 5 O3 4 O2 O1 3 O S U3 OE VP P P GM O7 9 O6 8 O5 7 O4 6 O3 5 O2 4 O1 3 O S U1 OE 16K x VP P P GM O7 9 O6 8 O5 7 O4 6 O3 5 O2 4 O1 3 O S U2 OE 2764 VP P P GM O7 8 O6 7 O5 6 O4 5 O3 4 O2 3 O1 2 O0 1 0 S OE U0 25 Robert ick dvanced igital Logic esign 26 Robert ick dvanced igital Logic esign PL/PL vs. PROM PL/PL vs. PROM PL Takes advantage of don t-cares Good at random logic PL Good when product terms shared More area-efficient for certain designs OR-plane can t be programmed, usually no sharing PROM esign trivial an t take advantage of don t-cares rea-inefficient Product/sum terms not shared 27 Robert ick dvanced igital Logic esign 28 Robert ick dvanced igital Logic esign

4 FIRST FUSE NUMERS INREMENT S YNHRONOUS RE S E T (TO LL RE GIS TE RS ) R Q Q S P LOGI MROE LL P 5810 R 5811 LOGI MROE LL P 5812 R 5813 LOGI MROE LL P 5814 R 5815 LOGI R MROE LL P 5816 R P INREMEN T LOGI MROE L L P 5818 R 5819 LOGI MROE L L P 5820 R 5821 LOGI MROE L L P 5822 R 5823 LOGI MROE L L P 5824 R 5825 LOGI MROE L L P 5826 R S YNHRONOUS P RE S E T 13 Field-programmable gate arrays () ltera EPLs PLs gate equivalent ltera ctel Xilinx 100 1,000,000 gate equivalent Each has from 8 48 macrocells Macrocell behavior controlled with EPROM bits an be used sequentially Has synchronous and asynchronous modes 30 Robert ick dvanced igital Logic esign 31 Robert ick dvanced igital Logic esign ltera erasable programmable logic devices (EPLs) Multiple array matrix (MX) omposed of many macrocells 8 product term N/OR array with programmable MUXs N RRY Invert ontrol lk MUX Output Q MUX F/ MUX pad I/O Pin Seq. Logic lock ltera macrocells quite limited an t share product terms between macrocells Workaround: onnect together macrocells with programmable interconnect Programmable po larity Programmable feedback 32 Robert ick dvanced igital Logic esign 33 Robert ick dvanced igital Logic esign Multiple array matrix (MX) MX expander terms Logic rray locks (s imilar to macrocells ) L L L L P I L H L G L F L E Global Routing: Programmable Interconnect rray EPM5128: 8 Fixed Inputs 52 I/O Pins 8 Ls 16 Macrocells /L 32 Expanders /L I N P U T S P I Macrocell RRY Expander Product Term RRY I/O lock I/O Pad I/O Pad 34 Robert ick dvanced igital Logic esign 35 Robert ick dvanced igital Logic esign MX expander terms ltera 22V10 PL Macrocell P Term s Expander P Term s Expander product terms shared among all macrocells Robert ick dvanced igital Logic esign 37 Robert ick dvanced igital Logic esign

5 ltera 22V10 PL ctel programmable gate arrays Many product terms per output Latches and MUXs associated with outputs 22 IO pins 10 may be used as outputs Rows of programmable logic blocks Rows of interconnect olumns of interconnect ttach to rows using antifuses 38 Robert ick dvanced igital Logic esign 39 Robert ick dvanced igital Logic esign ctel programmable gate arrays ctel logic block S O S 0 S 1 Each combinational logic block has 8 inputs, 1 output No built-in sequential elements uild flip-flops using logic blocks :1 MUX 2:1 MUX 2:1 MUX Y S O Modified 4:1 MUX 40 Robert ick dvanced igital Logic esign 41 Robert ick dvanced igital Logic esign ctel logic block ctel programmable gate arrays R IO buffers, programming & test logic 2:1 MUX 2:1 MUX 2:1 MUX Q IO buf., prog. & test logic IO buf., prog. & test logic Logic modules Wiring tracks S ross-couple for sequential use IO buffers, programming & test logic 42 Robert ick dvanced igital Logic esign 43 Robert ick dvanced igital Logic esign ctel interconnect ntifuse routing Logic Module Horizontal Track nti fuse uild long routing lines from short segments Vertical Track 44 Robert ick dvanced igital Logic esign 45 Robert ick dvanced igital Logic esign

6 ctel routing example Xilinx logic cell arrays (Ls) Logic Module Logic Module Output Input Logic Module MOS static RM Run-time programmable Serial shift-register based programming Program on power-up (external PROM) Input Minimize number of antifuse hops for critical path 2-3 hops for most interconnections 46 Robert ick dvanced igital Logic esign 47 Robert ick dvanced igital Logic esign Xilinx L components Xilinx Ls IO IO IO IO IO onfigurable logic blocks (s) IO blocks (IOs) Wiring channels IO Wiring hanne ls IO IO 48 Robert ick dvanced igital Logic esign 49 Robert ick dvanced igital Logic esign Xilinx L features Xilinx L features Inputs Input variables Tri-state (high-z) enable bit for output Output clocks Output the input bit ontains internal flip-flops for inputs and outputs Fast and slow outputs available, e.g., 5 ns vs. 30 ns Slower option limits slew rate Lower noise Lower power consumption 50 Robert ick dvanced igital Logic esign 51 Robert ick dvanced igital Logic esign Xilinx L Xilinx Program ontrolled Options Enable Output Out irect In Registered In OUT INV TS OUTPUT S LEW PS S IVE INV S OURE RTE PULLUP MUX Q Output uffer R Q TTL or MOS Input uffer R Vcc P 2 flip-flops General function of 4 variables 2 non-general functions of 5 variables ertain special-case functions of 6 variables Global reset lock lock enable Independent input, IN locks Global Reset 52 Robert ick dvanced igital Logic esign 53 Robert ick dvanced igital Logic esign

7 Xilinx generator Res et IN E lock lock Enable om binational Generator F G R Q E R Q E X Y E of 5 Variables F G Two constrained functions of five variables 54 Robert ick dvanced igital Logic esign 55 Robert ick dvanced igital Logic esign generator generator E E of 4 Variables of 4 Variables Two arbitrary functions of four variables F G of 4 Variables of 4 Variables E ertain limited functions of 6 variables F G 56 Robert ick dvanced igital Logic esign 57 Robert ick dvanced igital Logic esign PRITY5 cost example 2-bit comparator cost example etermine whether the number of 1s is even or odd F = E Implement using 1 = or > GT = + + EQ = Only 1 required 58 Robert ick dvanced igital Logic esign 59 Robert ick dvanced igital Logic esign Majority cost example Large parity cost example High whenever n /2 outputs are high 5 input Majority ircuit 2 levels allow up to 25 inputs 9 Input Parity Logic 7 input Majority ircuit 60 Robert ick dvanced igital Logic esign 61 Robert ick dvanced igital Logic esign

8 4-bit adder cost example 4-bit adder cost example Full adder, 4 delays to final carry out (O), 4 s in omposition from 2 2-bit adders give 2 delay, 6 cost in out S 3 2 S 2 1 S 1 0 S 0 S 3 S 2 S 1 S 0 out 2 62 Robert ick dvanced igital Logic esign 63 Robert ick dvanced igital Logic esign Xilinx interconnect Xilinx interconnect Short direct connections Global long lines Horizontal/vertical long lines Switching matrix connections Hierarchical routing organization Some designs are constrained by routing resources an use logic s to control routing Substantial communication power consumption 64 Robert ick dvanced igital Logic esign 65 Robert ick dvanced igital Logic esign Xilinx interconnect Example Xilinx parts Interconnect irect onnections Global Long Line Ho rizontal/vertical Long Lines Switching Matrix onnections irect onnections Horizontal Long Line Horizontal Long Line I E X 0 K Y E R I E X 2 K Y E R Switching Matrix I E X 1 K Y E R I E X 3 K Y E R Parameter X4024 X3195 X2018 Number of FFs 2,560 1, Number of IOs Number of logic inputs per generators per Fast carry logic yes no no Number of logic outputs per RM bits 32, Vertical Long Lines Global Long Line 66 Robert ick dvanced igital Logic esign 67 Robert ick dvanced igital Logic esign ynamic reconfiguration FPG application examples Serial configuration slow Parallelize Full reconfiguration slow Partial reconfiguration Reconfiguration slow Use configuration cache Prototyping onstant coefficient multiplication irect HW implementation of problem instance, e.g., 3ST esign rule checking (R) 68 Robert ick dvanced igital Logic esign 69 Robert ick dvanced igital Logic esign

9 Prototype designs Programmable devices in prototyping iscrete packages Slow Error-prone ustom layout requires circuit fabrication Slow Expensive for small runs an t be changed Multiplexers (MUXs) and demultiplexers (MUXs) Wiring them up is tedious and error-prone Programmable array logic (PL) and programmable logic array (PL) Fuses blown, write-once Generic array logic (GL) Electrically reprogrammable 70 Robert ick dvanced igital Logic esign 71 Robert ick dvanced igital Logic esign Programmable devices in prototyping Programmable devices in prototyping Programmable read-only memories (P) Inefficient for implementing random logic Write-once Erasable programmable read-only memories (EP) an be erased Erasure slow (UV) Expensive package window Electrically erasable programmable read-only memories (EEP) Erasure fast Packaging less expensive Potential for in-circuit erasure Field-programmable gate arrays () are ideal If market size small, ship In-circuit programming practical 72 Robert ick dvanced igital Logic esign 73 Robert ick dvanced igital Logic esign emorgan s Law for MOS emorgan s Law for MOS ( + ) = () = + + = = + OR is the same as NN with complemented inputs N is the same as NOR with complemented inputs NN is the same as OR with complemented inputs NOR is the same as N with complemented inputs 75 Robert ick dvanced igital Logic esign 76 Robert ick dvanced igital Logic esign emorgan s Law for OR/NN emorgan s Law for N/NOR + ( ) + () ( + ) ( + ) Robert ick dvanced igital Logic esign 78 Robert ick dvanced igital Logic esign

10 N/OR NN/NOR N/OR NN/NOR N N OR 79 Robert ick dvanced igital Logic esign 80 Robert ick dvanced igital Logic esign N/OR NN/NOR N/OR NN/NOR NN N N NN NN OR NN NN NN NN NN NN 81 Robert ick dvanced igital Logic esign 82 Robert ick dvanced igital Logic esign N/OR/NOT network to NN/NOR = = = Review for midterm exam on Thursday Will post solutions to homework tonight Responsible for all reading, assignments, labs = 83 Robert ick dvanced igital Logic esign 85 Robert ick dvanced igital Logic esign Review Two-level transformations and minimization Multi-level minimization esign with various implementation technologies 86 Robert ick dvanced igital Logic esign

Ch 9. Sequential Logic Technologies. IX - Sequential Logic Technology Contemporary Logic Design 1

Ch 9. Sequential Logic Technologies Technology Contemporary Logic Design Overview Basic Sequential Logic Components FSM Design with Counters FSM Design with Programmable Logic FSM Design with More Sophisticated