MATC DIGITAL ELECTRONICS LAB ASYNCHRONOUS RIPPLE COUNTERS

Transcription

1 MT IGITL ELETONIS L SYNHONOUS IPPLE OUNTES Submitted to: Mr. Pham Submitted by: Jody ecker Submitted on: //00 Performed on: //00 Lab Group #

2 OJETIVES Jody ecker Elctec 0-00 Lab synchronous ounters Page of esign and build an asynchronous mod, mod 0, and mod counters with segment display. MTEILS () uad -Input NN gate 00 () ual J-K Flip-Flop - () to segment decoder/driver () segment display () 00 Ohm resistors () 0 Ohm resistor () s PT - MO OUNTE POEUES. onstruct cross coupled NN gate latch for use as debounce switch. (Fig..). onstruct -bit MO counter using J-K Flip-Flops, and using NN gate latch from step as a clock input. (Fig..). Test to verify that circuit counts from 0000 to (0 to 0 ), then resets to 0000 again. (Table., and Fig., and Fig.) 0 Ohm 00 Ohm 00 Ohm 00 Ohm 00 Ohm p.k to 0k Ohm LOK HI J-K F.F. - J-K F.F. - J-K F.F. - J-K F.F SW NO 0 N L V L L V L PE PE PE PE LS MS 0 p.k to 0k Ohm 00 ESET Fig.. MO counter circuit

3 Jody ecker Elctec 0-00 Lab synchronous ounters Page of Table. MO counter output table. ount Fig. MO state transition diagram. Fig.. MO Timing iagram.

4 Jody ecker Elctec 0-00 Lab synchronous ounters Page of PT - MO 0 OUNTE WITH SEGMENT ISPLY POEUES. esign circuit for MO 0 counter. efer to state transition diagram Fig.., and MO 0 counter output table (Table.) to determine output conditions that will be used for resetting counter. Use the combination of outputs following last number in the sequence to reset the counter by connecting them to a NN gate which will output a temporary low to the reset pins when both of the NN gate inputs are high.. onstruct cross coupled NN gate latch for use as debounce switch. (Fig..). onstruct -bit MO 0 counter using J-K Flip-Flops, and using NN gate from step as a reset, and NN gate latch from step as a clock input. (Fig..). onnect outputs from counter to decoder/driver chip. onnect decoder chip to segment display. (Fig..). Test to verify that circuit counts from 0000 to 00 (0 to 0 ), then resets to 0000 again. (ef Table., and Fig., and Fig.) E./V. 0 E LT F I G V 00 Ohm (X) -SEGMENT- a V 0 b a c f b d g e e c f g d 0 Ohm ESET- NN GTE Ohm 00 Ohm 00 Ohm 00 Ohm 00 Ohm p.k to 0k Ohm SW NO 00 LOK HI J-K F.F. - J K J-K F.F. - 0 J-K F.F. - J-K F.F. - 0 N L V PE LS L PE L V PE L PE MS p.k to 0k Ohm 00 Fig.. MO 0 counter circuit

5 Jody ecker Elctec 0-00 Lab synchronous ounters Page of Table. MO 0 counter output table. ount Fig. Mod 0 state transition diagram. eset state. Outputs and. Fig.. MO 0 Timing iagram

6 Jody ecker Elctec 0-00 Lab synchronous ounters Page of PT - MO OUNTE WITH SEGMENT ISPLY POEUES. esign circuit for MO counter. efer to state transition diagram Fig.., and MO counter output table (Table.) to determine output conditions that will be used for resetting counter. Use the combination of outputs following last number in the sequence to reset the counter by connecting them to a NN gate which will output a temporary low to the reset pins when both of the NN gate inputs are high.. onstruct cross coupled NN gate latch for use as debounce switch. (Fig..). onstruct -bit MO counter ( th bit not used) using J-K Flip-Flops, and using NN gate from step as a reset, and NN gate latch from step as a clock input. (Fig..). onnect outputs from counter to decoder/driver chip. onnect decoder chip to segment display. (Fig..). Test to verify that circuit counts from 0000 to 00 (0 to 0 ), then resets to 0000 again. (ef Table., and Fig., and Fig.) E./V. 0 E LT F I G V 00 Ohm (X) -SEGMENT- a V 0 b a c f b d g e e c f g d 0 Ohm ESET- NN GTE Ohm 00 Ohm 00 Ohm 00 Ohm 00 Ohm p.k to 0k Ohm SW NO 00 LOK HI J K J-K F.F. - J-K F.F. - 0 J-K F.F. - J-K F.F. - 0 N L V PE LS L PE L V PE L PE MS p.k to 0k Ohm 00 Fig.. MO counter circuit

7 Jody ecker Elctec 0-00 Lab synchronous ounters Page of Table. MO counter output table. ount Fig. Mod state transition diagram. eset state. Outputs and. Fig.. MO Timing iagram