Chapter #6: Sequential Logic Design

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1 Chapter #6: equential Logic esign Contemporary Logic esign No. 6- Cross-Coupled NO Gates ust like cascaded inverters, with capability to force output to (reset) or (set) \ eset Hold et eset et ace \ Forbidden tate Forbidden tate No. 6-2

2 Observed - Latch Behavior =, =, = = = = = = = = = Very difficult to observe - Latch in the - state Ambiguously retur to state - or - A so-called "race condition" No. 6-3 efinition of Terms Clock: Periodic Event, causes state of memory element to change Input rising edge, falling edge, high level, low level Clock There is is a timing "window" around the the clocking event during which the the input must remain stable and and unchanged in in order to to be be recognized etup Time (Tsu) Minimum time before the clocking event by which the input must be stable Hold Time (Th) Minimum time after the clocking event during which the input must remain stable No. 6-4

3 7474 Positive edge-triggered flip-flop Edge triggered device sample inputs on the event edge Traparent latches sample inputs as long as the clock is asserted 7476 Timing iagram: C Level-seitive latch Bubble here for negative edge triggered device Behavior the same unless input changes while the clock is high No. 6-5 Typical Timing pecificatio: Flipflops vs. Latches 74L74 Positive Edge Triggered Flipflop etup time Hold time Minimum clock width Propagation delays (low to high, high to low, max and typical) T w 25 T plh 25 3 T phl 4 25 All measurements are made from the clocking event that is, the rising edge of the clock No. 6-6

4 Typical Timing pecificatio: Flipflops vs. Latches 74L76 Traparent Latch etup time Hold time Minimum Clock Width Propagation elays: high to low, low to high, maximum, typical data to output clock to output T w 2 T plh C» 27 5 T plh» 27 5 T phl» 6 7 T phl C» 25 4 Measurements from falling clock edge or rising or falling data edge No Flipflop How to eliminate the forbidden state? Idea: use output feedback to guarantee that and are never both one, both one yields toggle - latch \ \ Characteristic Equation: + = + No. 6-8

5 - Latch: ace Condition et eset Toggle \ ace Condition Toggle Correctness: ingle tate change per clocking event olution: Master/lave Flipflop No. 6-9 Master/lave - Flipflop Master tage lave tage - Latch \ \P P - Latch \ \ ample inputs while clock high ample inputs while clock low Uses Uses time time to to break break feedback path path from from outputs to to inputs! 's et eset Catch T oggle P \ P \ Master outputs lave outputs Correct Toggle Operation No. 6-

6 Edge-Triggered Flipflops 's Catching: a -- glitch on the or inputs leads to a state change! forces designer to use hazard-free logic olution: edge-triggered logic = Holds when clock goes low Negative Edge-Triggered flipflop 4-5 gate delays setup, hold times necessary to successfully latch the input Holds when clock goes low Negative edge-triggered FF when clock is high Characteristic Equation: + = No. 6- The Problem of Clock kew Correct behavior assumes next state of all storage elements determined by all storage elements at the same time Not possible in real systems! logical clock driven from more than one physical circuit with timing behavior different wire delay to different points in the circuit Effect of kew on Cascaded Flipflops: FF samples IN FF samples In CL2 is a delayed version of CL 2 Original tate: =, =, In = Because of skew, next state becomes: =, =, not =, = No. 6-2

7 ealizing Circuits with ifferent inds of Flipflops -: : -: T: + = + + = + = + + = T + T Implementing One FF in Terms of Another C C implemented with - - implemented with No. 6-3 Excitation Tables: What are the necessary inputs to cause a particular kind of change in state? + Implementing FF with a - FF: ) tart with -map of + = ƒ(, ) 2) Create -maps for and with same inputs (, ) 3) Fill in -maps with appropriate values for and to cause the same state changes as in the original -map E.g., = =, + = then =, = T + = = = No. 6-4

8 Implementing - FF with a FF: ) -Map of + = F(,, ) 2,3) evised -map using 's excitation table its the same! that is why design procedure with FF is simple! esulting equation is the combinational logic input to to cause same behavior as - FF. Of course it is identical to the characteristic equation for a - FF. + = = + No. 6-5

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