Sequential Logic Design

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1 221: igital esign equential Logic esign (FF& egister) A. ahu ept of omp. c. & ngg. ndian nstitute of echnology Guwahati Outline FF: haracterization able and quation,, and Flip flop egister ParallelLoad,Parallelout:(PPO) out : erial Load, Wrap around load, erial out (O) PO, PO egister Multifunction egister : How to design? Master lave + = + o synthesize a flip flop, simply set equal to the complement of. he flip flop is a universal flip flop Because it can be configured to work as any FF flip flop or flip flop or flip flop. = = + t t = = + t t = = + t t ==1, + = oggle Flip Flop: FF + t U 4 ypes of Flip Flops + t t + + t 1 t 1

2 Given a FF: onstruct FF Given a FF: onstruct FF = + = + haracteristic quations A descriptions of the next state table of a flip flop onstructingfromthearnaughmap the for t+1 in terms of the present state and input haracteristic tables he tables that we ve made so far are called characteristic tables. hey show the next state (t+1) in terms of the current state (t) and the inputs. For simplicity, the control input is not usually listed. Again, these tables don t indicate the positive edgetriggered behavior of the flip-flops that we ll be using. + t t + + t 1 t haracteristic equations We can also write characteristic equations, where the next state (t+1) is defined in terms of the current state (t) and inputs. + += +t + t = = = (+ ) +(+ ) t + = + (t+1)= (t) + (t) haracteristic equations We can also write characteristic equations, where the next state (t+1) is defined in terms of the current state (t) and inputs. + + = + (t+1) = t 1 t += + = (t+1) = (t) + (t) = (t) 2

3 haracteristic equations + = + (=) ype + = haracteristic quation + = + (=) + = + + = + = FF with Asynchronous nputs, and inputs are synchronous inputs As data on these inputs are transferred to the flipflop s output Only on the triggered edge of the clock pulse. Asynchronous inputs affect the state of the flipflop independent of the clock xample: Preset(P) and clear(l) or direct set() and direct reset() FF with Asynchronous nputs When P=HGH, is immediately set to HGH. When L=HGH, is immediately cleared to LOW. Flip flop in normal operation mode when both PandLareLOW LOW. Asynchronous nputs A flip flop with active LOW preset and clear inputs. P ' P L L = = 1 Preset oggle lear egisters Group of Flip Flops ynchronized (ingle lock) tore ata 2 eset A A Note: New data has to go in with every clock egisters eset ee carefully: nput at the dotted will be reflected to output : ust before rising edges 2 3 A 3

4 egisters with Parallel Load ontrol Loadingthe egister with New ata L G L (t+1) (t) 1 egisters with Parallel Load hould we block the lock to keep the ata? L G elays the lock Load A egisters with Parallel Load irculate the old data A hift egisters egister (et of FFs) 4 Bit hift egister (xample) erial in erial Out (O) Load 21 hift egister ight hift xample (Left shift is similar) Move each bit one position right hift in to leftmost bit : o four right shifts on 11, showing value after each shift A: 11 (original) egister contents before shift right egister contents after shift right hift egister 1 1 egister contents before shift right egister contents after shift right mplementation: onnect flip-flop output to next flip-flop s input shr_in

5 hift egisters hift egisters (O) 4 Bit hift egister erial in erial Out (O) O erial nput O erial Output / 28 hift egister with ontrol o allow register to either shift or retain, use 2x1 muxes hift ontrol: shr: means retain, 1 shift shr_in: value to shift in : May be /1, or right most bit erial n Bit hift ontrol ilotbit erial Out hift egister with ontrol hift ontrol=1, o one right shift per cycle erial n Bit hift ontrol erial Out Bit 27 hift egister with ontrol hift ontrol=, No change to ata erial n Bit hift ontrol erial Out Bit hanks 5

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