A B D 1 Y D 2 D 3. Truth table for 4 to 1 MUX: A B Y 0 0 D D D D 3
|
|
- Rebecca Small
- 5 years ago
- Views:
Transcription
1 . What is a multiplexer? esign a 4 to multiplexer using logic gates. Write the truth table and explain its working principle. Answer: is a circuit with many inputs but only one output. esigning of 4 to multiplexer shown below: A B Y 2 3 Truth table for 4 to MUX: A B Y 2 3 Working principle of 4 to multiplexer: From the above diagram, the Logic Equation for 4 to multiplexer is Y A B A B AB AB 2 3 If A, B then, Y Similarly, if A= and B= then Y=, if A= and B= then Y= 2 and, if A= and B= then Y= 3 Page:
2 2. onstruct 4: multiplexer using only 2: multiplexer. Answer: Logic Equation for 2 : is Y A A Logic equation for 4 : Multplexer is Y A B A B AB AB Y A ( B B ) A( B B ) We require three 2: s and the connection is shown below. B 2: A B 2: Y 2 3 2: 3. onstruct 8: multiplexer using only 2: multiplexer. Answer: Logic Equation for 2 : is Y A A Logic Equation for 8 : is Y A B A B A B A B AB AB AB AB Y A ( B B B B ) A( B B B B ) Y A [ B ( ) B( 2 3 )] A[ B ( 4 5 ) B( 6 7 )] Page: 2
3 2: B 2: 2 3 2: A 2: Y 4 5 2: B 2: 6 7 2: 4. esign 6 to multiplexer using 8 to multiplexer and one 2 to multiplexer. Answer: Logic Equation for 2 : is Y A A Logic Equation for 8: is Y A B A B A B A B AB AB AB AB Logic Equation for 6 : is Y A B A B... A B A B AB AB... AB AB Y A ( B B... B B ) A( B B... B B ) Page: 3
4 B 8: A 7 B 2: Y 8 5 8: 5. esign 32 to multiplexer using 6 to multiplexer and one 2 to multiplexer. Answer: Logic Equation for 2 : is Y A A Logic Equation for 6 : is Y A B A B... AB AB 4 5 Logic Equation for 32 : is Y A B E... A BE A BE AB E... ABE ABE Y A ( B E... BE BE ) A( B E... BE BE ) B E : A 5 B E 2: Y 6 3 6: Page: 4
5 6. Mention the differences between decoder and demultiplexer. Answer: emultiplexer There is one data input and multiple output. There are selects used as control bits. The data input appears at one of the output as per the control inputs. Input appears at the output where subscription of the output is equal to the decimal equivalent to the inputs. ecoder There is no data input. The only inputs are the control bit. One of the output is high as per the control inputs. Output becomes high where subscription of the output is equal to the decimal equivalent to the inputs 7. (a) Realize Y A B B AB using an 8 to. (b) an it be realized with a 4 to multiplxer? Answer : ( a) Logic Equation for 8: is Y A B A B A B A B AB AB AB AB We should express Y as a function of three variables i.e function of minterms. Y A B B AB Y A B( ) B ( A A ) AB Y A B A B AB A B AB Y A B A B A B AB AB omparing with the Logic equation of 8:, we have and A B = = 2 = 3 = 4 = 5 = 6 = 7 = 8: Y ( b) Y A B B AB Y A B B ( A A ) AB Y A B AB A B AB Y A B. A B. AB. AB. Logic equation for 4 : Multplexer is Y A B A B AB AB 2 3 Page: 5
6 We have,,, and 2 3 A B =ʹ = 2 =ʹ 4: Y 3 = 8. Implement the following Boolean functions using 4: multiplexer (MUX): ( i) Y f ( A, B,, ) m(,,2, 4,6,9,2,4) ( ii) F( A, B, ) m(,3,5,6) Answer: Logic equation for 4 : Multplexer is Y A B A B AB 2 AB3 Y f ( A, B,, ) m(,,2,4,6,9,2,4) Y A B A B A B A B A B AB AB AB Y A B ( ) A B( ) AB AB( ) omparing with Logic Equation of 4 :, We have Page: 6
7 I = I = I 2 = I 3 = 4: I 4 = I 5 = I 6 = I 7 = 4: A B 4: Y I 8 = I 9 = I = I = 4: 2 I 2 = I 3 = I 4 = 4: 3 I 5 = Logic equation for 4 : Multplexer is Y A B A B AB AB (ii) 2 3 F( A, B, ) m(,3,5,6) F A B A B AB AB F A B. A B. AB. AB. omparing with Logic Equation of 4 :, we have,, and 2 3 Page: 7
8 A B = = 2 = 3 =ʹ 4: F 9. Implement the Boolean function expressed by SOP: f ( A, B,, ) m(, 2,5,6,9,2) using 8 to MUX. Answer: AB = = f d d' d' d' d' d 8: MUX data input = = ' 2 = 3 =' 4 = 5 = 6 = ' 7 = ircuit diagram: A B ' : MUX f Page: 8
9 . Implement the Boolean function: F( A, B,, ) m(,,2, 4,5,7,8,9) using 8 to multiplexers. raw the logic diagram and explain the operation. Additional gates can be used if required. Answer : ( a) Logic Equation for 8: is Y A B A B A B A B AB AB AB AB Logic Equation for 2 : is Y A A F( A, B,, ) m(,,2,4,5,7,8,9) F A B A B A B A B A B A B AB AB F A ( B B B B B B) A( B B ) omparing with 2 : Logic Equation, we have B B B B B B B. B. B. B. B. B. B. B. B B B. B. B. B. B. B. B. B. B I = I = I 2 = I 3 = I 4 = I 5 = I 6 = I 7 = 8: Multiplxer Aʹ B F I 8 = I 9 = I = I = I 2 = I 3 = I 4 = I 5 = 8: Multiplxer (Note: 9 and are similar. But method for 9 is preferable) A Page: 9
10 . Realize the following Boolean function: P f ( w, x, y, z) (,,5,6,7,,5) using (i) 6: MUX (ii) 8: MUX (iii) 4: MUX Answer : ( i) Logic Equation for 6 : is P w x y z. w x y z. w x yz. w x yz. w xy z. w xy z. w xyz. w xyz. wx y z wx y z. 9 wx yz. wx yz. wxy z. 2 wxy z. 3 wxyz. 4 wxyz. 5 P f ( w, x, y, z) m(,,5,6,7,,5) P w x y z w x y z w xy z w xyz w xyz wx yz wxyz P w x y z. w x y z. w x yz. w x yz. w xy z. w xy z. w xyz. w xyz. wx y z. + wx y z. wx yz. wx yz. wxy z. wxy z. wxyz. wxyz. omparing with Logic Equation for 6 :, we have and w x y z = = 2 = 3 = 4 = 5 = 6 = 7 = 8 = 9 = = = 2 = 3 = 4 = 5 = 6: P ( ii) Logic Equation for 8: is Y x y z. I x y z. I x yz. I x yz. I xy z. I xy z. I xyz. I xyz. I Logic Equation for 2 : is Y w w Page:
11 P f ( w, x, y, z) m(,,5,6,7,,5) P w x y z w x y z w xy z w xyz w xyz wx yz wxyz P w ( x y z x y z xy z xyz xyz) w( x yz xyz) P w ( x y z. x y z. x yz. x yz. xy z. xy z. xyz. xyz.) w( x y z. x y z. x yz. x yz. xy z. xy z. xyz. xyz.) omparing with Logic Equation of 2:, we have x y z. x y z. x yz. x yz. xy z. xy z. xyz. xyz. x y z. x y z. x yz. x yz. xy z. xy z. xyz. xyz. x y z I = I = I 2 = I 3 = I 4 = I 5 = I 6 = I 7 = 8: Multiplxer wʹ x y z P I 8 = I 9 = I = I = I 2 = I 3 = I 4 = I 5 = 8: Multiplxer w Page:
12 (iii) Logic equation for 4 : Multplexer is Y w x w x wx 2 wx3 P f ( w, x, y, z) m(,,5,6,7,,5) P w x y z w x y z w xy z w xyz w xyz wx yz wxyz P w x ( y z y z) w x( y z yz yz) wx yz wxyz omparing with Logic Equation for 4:, we have y z y z 2 3 y z. y z. yz. yz. y z yz yz y z. y z. yz. yz. yz y z. y z. yz. yz. yz y z. y z. yz. yz. y z I = I = I 2 = I 3 = 4: y z I 4 = I 5 = I 6 = I 7 = 4: y z w x 4: P I 8 = I 9 = I = I = 4: 2 y z I 2 = I 3 = I 4 = 4: 3 I 5 = Page: 2
13 2. esign and implement B to excess-3 code converter using four 8: multiplexers. Take MSB A as map entered variable(input variable) B lines as select lines, assuming f(a,b,,) as B input. Answer: Truth table for converting B to Excess-3 B Excess-3 A B W X Y Z esigning of the multiplexer whose output is W B A= A= X X X X X X W A A 8: MUX ata Input =A =A 2 = 3 = 4 = 5 = 6 = 7 = esigning of the multiplexer whose output is X B A= A= X X X X X X X 8: MUX ata Input = = 2 = 3 = 4 = 5 = 6 = 7 = esigning of the multiplexer whose output is Y B A= A= X X X X X X Y 8: MUX ata Input = = 2 = 3 = 4 = 5 = 6 = 7 = esigning of the multiplexer whose output is Z B A= A= X X X X X X Z ata Input = = 2 = 3 = 4 = 5 = 6 = 7 = Page: 3
14 Page: B B B B W X Y Z A A 8: 8: 8: 8:
15 3. Realize a logic circuit for octal to binary encoder. Answer: Truth table for octal to binary encoder Input Output B 2 B B B 2 B B 4. Implement a full adder using a 3 to 8 decoder. Answer: Truth table for full adder A B Sum arry Page: 5
16 A B 3:8 ecoder Sum 5 6 arry 7 5. Implement full adder using I 7438 Answer: Truth table for full adder A B Sum arry A B 3:8 ecoder Sum 5 6 arry 7 Page: 6
17 6. Implement 3 bit binary to gray code conversion by using I Answer: Truth table for converting 3 bit binary to gray code Binary code Gray code A B X Y Y K-Map for X: K-Map for Y: K-Map for Z: AB AB AB X=A Y=AB+AB Z=B+B A X B 7439 Y 7439 Z Page: 7
18 7. esign a priority encoder for a system with a 3 inputs, the middle bit with highest priority encoding to, the MSB with the next priority encoding to, while the LSB with least priority encoding to. Answer: Truth table of the priority encoder Input Output A B X Y AB K-Map for X: AB K-Map for Y: X=A+B Y=AB+B=B(A+) A B X Y Page: 8
19 8. esign a 4 to 6 line decoder using 2 to 4 line decoder which has the active low outputs as active low enable input. Explain its operation. Answer: 2 to 4 line decoder E A B 2 to 4 line decoder 2 to 4 line decoder E 2 to 4 line decoder E 2 to 4 line decoder E 9. Write the comparisons between PLA and PAL. Answer: PAL The output OR-gate array is fixed while the input AN gate array is fusible linked and thus programmable. PAL is easier to program. PAL is less expensive. PLA Both output OR-gate array and input AN gate array are fusible linked. PLA is more complicated since the number fusible links are more compared to PAL PLA is more expensive compared to PAL. Page: 9
20 2. esign 7-segments decoder using PLA. Answer: Seven segment indicator: a f b g e c d Following table shows the segments should light up to display a number. Number to display Segments to light up a,b,c,d,e,f b,c 2 a,b,d,e,g 3 a,b,c.d,g 4 b,c,f,g 5 a,c,d,f 6 a,c,d,e,f,g 7 a,b,c 8 a,b,c,d,e,f,g 9 a,b,c,f,g Page: 2
21 Page: a b c d e f g A B
22 2. Implement the following function using PLA: A(x,y,z)=Σm(,2,3,6); B(x,y,z)=Σm(,,6,7); (x,y,z)=σm(2,6) Answer: A B A(x,y,z) =Σm(,2,3,6) B(x,y,z) =Σm(,,6,7) A(x,y,z) =Σm(,2,6) Page: 22
23 22. raw the PLA circuit and realize the Boolean functions: X A B AB B, Y A B AB, Z B Answer : X A B AB B A B AB B ( A A ) A B AB AB Y A B AB Z B B ( A A ) AB A B A B Y Z Page: 23
24 23. escribe the working principle of 3:8 decoder. esign a circuit that realizes the following functions using a 3:8 decoder and multi input OR gates. ( i) F ( A, B, ) m(,3,7) (ii) F ( A, B, ) m(2,3,5) 2 Answer: Working principle of 3:8 decoder: There are 3 inputs and 8 outputs in a 3:8 decoder. One of the output is HIGH and remaining seven are LOW according to inputs. This is shown in truth table. A B 3:8 ecoder Y Y Y 2 Y 3 Y 4 Y 5 Y 6 Y 7 AB AB AB AB AB AB AB AB Truth table of 3:8 ecoder : A B Y Y Y 2 Y 3 Y 4 Y 5 Y 6 Y 7 Page: 24
25 A B 3:8 ecoder Y Y Y 2 Y 3 Y 4 Y 5 Y 6 Y 7 AB AB AB AB AB AB AB AB F (A,B,) =Σm(,3.7) F 2 (A,B,) =Σm(2,3.5) 24. What is magnitude comparator? esign one bit comparator and write the truth table, logic circuit using basic gates. Answer: A magnitude comparator compares two binary numbers and it produces an output showing the comparison of the two input numbers. For example, two n-bit binary numbers X=X X..X n and Y=Y Y Y n are compared. There are three ouputs. The outputs are for X>Y, X=Y and X<Y as shown in the figure below. Page: 25
26 X X n Y Y n n-bit comparator X>Y X=Y X<Y esigning of one bit comparator: Truth table Input Output X Y X>Y X=Y X<Y If G, L, E stand for greater than, less than and equal to respectively, then (X>Y): G=XYʹ; (X<Y):L=XʹY; (X=Y): E=XʹYʹ+XY=(XYʹ+XʹY)ʹ=(G+L)ʹ X X<Y X=Y Y X>Y Page: 26
27 25. What is parity generator? Explain with an example. Answer: A parity generator is a logic circuit which produces either even parity number or odd parity number as per requirement. For example: X 7 X 6 X 5 X 4 X 3 X 2 X X X 8 ata Input 9-bit number with odd parity Page: 27
28 26. What is parity checker? Explain with example. Answer: A parity checker check the parity of a number whether the number is of even parity or odd parity. For example: The exclusive OR gate produces an output when the input ( X X 7 ) is of odd parity and produces when the input is of even parity. X 7 X 6 X 5 X 4 X 3 X 2 X X Y Page: 28
29 27. Give state transition diagram of SR,, JK and T flip flops. Answer: S R State Transition iagram S R S R S R flip flop SR flip flop J K J K J K T J K T T flip flop JK flip flop T T Page: 29
30 28. Obtain the characteristic equation of SR, JK, and T flip flops. Answer: S R State Transition iagram S R S R S R flip flop SR flip flop J K J K J K T J K T T flip flop JK flip flop T T Excitation Table for SR, JK, and T flip flop is given below is prepared State Transition iagram above n n+ S R J K T X X X X X X Page: 3
31 From the Excitation Table, K-map is formed and then the characteristic equation is determined. SR n x haracteristic Equation for SR flip flop is x n+ =S+R n JK n haracteristic Equation for JK flip flop is n+ =J n +K n n haracteristic Equation for flip flop is n+ = n T haracteristic Equation for T flip flop is n+ =T n +T n Page: 3
32 29. Explain the operation of a gated SR latch with a logic diagram and truth table. Logic diagram and truth table of gated SR flip flop is shown below: S S EN S R n+ n (No hange) EN R R x x Illegal n (No hange) Logic iagram Truth table When the Enable (EN) input is high, information at the R and S inputs will be transmitted directly to the outputs. The latch is said to be enabled. When the Enable (EN) input is low, the outputs of the AN gates are low and information at the R and S inputs will not be transmitted to the outputs. The latch is said to be disabled. It is possible to strobe or clock the flip flop in order to store information at any time and then hold the stored information for any desired period of time. This flip flop is called a gated or clocked RS flip flop. Page: 32
33 3. Explain the operation of edge triggered SR flip flop with the help of a logic diagram and truth table. Also draw the relevant waveforms. Answer: Positive edge triggered SR flip flop S S S PT R R R Logic iagram IEEE Symbol S R n+ n (No hange) ( Reset ) ( Set ) Illegal PT S R t t t 2 t 3 t 4 Truth table Positive edges occur at t,t,t 2,t 3 and t 4. At t, S= and R=, hence no change in the output and =. At t, S= and R=, hence the output is set and =. At t 2, S= and R=, hence the output is reset and =. At t 3, S= and R=, hence the output is set and = At t 4, S= and R=, hence no change in the output and =. Waveform of positive edge triggered RS flip flop Page: 33
34 Negative edge triggered SR flip flop S S S NT R R R Logic iagram SR flip flop Symbol S R n+ n (No hange) ( Reset ) ( Set ) Illegal PT S R t t t 2 t 3 t 4 Truth table. Negative edges occur at t,t,t 2,t 3 and t 4. At t, S= and R=, hence no change in the output and =. At t, S= and R=, hence the output is set and =. At t 2, S= and R=, hence the output is reset and =. At t 3, S= and R=, hence the output is set and = At t 4, S= and R=, hence no change in the output and =. Waveform of negative edge triggered SR flip flop Page: 34
35 3. Explain the operation of edge triggered flip flop with the help of a logic diagram and truth table. Also draw the relevant waveforms. Answer: Positive edge triggered flip flop S PT R Logic iagram flip flop Symbol n+ x n (No hange) PT t t t 2 t 3 t 4 Truth table Positive edges occur at t,t,t 2,t 3 and t 4. At t, =, hence the output is low and =. At t, =, hence the output is high and =. At t 2, =, hence the output is low and =. At t 3, =, hence the output is high and = At t 4, =, hence no change in the output and =. Waveform of positive edge triggered flip flop Page: 35
36 Negative triggered flip flop S NT R Logic iagram flip flop Symbol n+ x n (No hange) PT t t t 2 t 3 t 4 Truth table Negative edges occur at t,t,t 2,t 3 and t 4. At t, =, hence the output is low and =. At t, =, hence the output is high and =. At t 2, =, hence the output is low and =. At t 3, =, hence the output is high and = At t 4, =, hence no change in the output and =. Waveform of positive edge triggered flip flop Page: 36
37 32. Explain the working of pulse triggered JK flip flop with typical JK flip flop waveform. Answer: Positive Edge Triggered JK flip flop J S J PT K R K Logic iagram JK flip flop Symbol J K n+ n (No hange) Toggle PT J K t t t 2 t 3 t 4 Truth table Positive edges occur at t,t,t 2,t 3 and t 4. At t, J= and K=, hence no change in the output and =. At t, J= and K=, hence the output is high and =. At t 2, J= and K=, hence the output is low and =. At t 3, J= and K=, hence the output is high and = At t 4, J= and K=, hence no change in the output and =. Waveform of positive edge triggered JK flip flop : Page: 37
38 Negative Edge Triggered JK flip flop J S J NT K R K Logic iagram JK flip flop Symbol J K n+ n (No hange) Toggle NT J K t t t 2 t 3 t 4 Truth table Waveform of positive edge triggered JK flip flop Negative edges occur at t,t,t 2,t 3 and t 4. At t, J= and K=, hence no change in the output and =. At t, J= and K=, hence the output is high and =. At t 2, J= and K=, hence the output is low and =. At t 3, J= and K=, hence the output is high and = At t 4, J= and K=, hence no change in the output and =. Page: 38
39 33. Explain the working of Master Slave J K flip flops with logic diagram. Answer: J J K K Master Slave flip flop Master is positive-level-triggered and the slave is negative-level-triggered. The master responds to its J and K inputs before the slave. If J= and K=, the master sets on the positive clock transition. The high output of the master drives the J input of the slave. So, on the negative clock transition, the slave sets, thus copying the action of the master. If J= and K=, the master resets on the positive clock transition. The high output of the master drives the K input of the slave. So, on the negative clock transition, the slave resets, thus copying the action of the master. If J= and K=, the master toggle on the positive clock transition. The slave also toggle at the negative clock transition thus copying the action of the master. If J= and K=, the master and the slave both are disabled, thus copying the action of the master. Page: 39
40 34. What is contact bounce? With neat diagram, explain the working principles of Switch e bounce circuit. Answer: 5V Voltage at A R 5V S A V Bounce Any mechanical switching device consists of a moving contact arm restrained by some spring system. As a result, when a mechanical switch is closed, the arm is moved from one stable position to other and the arm bounces much as a hard ball bounces when dropped on a hard surface. This phenomenon is known as contact bounce. When switch S is closed, due contact bounce the voltage at the A is shown in the above figure. RS Latch ebounce ircuit +V SW H R S L R 2 R When switch(sw) is moved to the position H, R= and S=. Bouncing occurs at S due to contact bounce of the switch. The flip flop treat as high and low inputs. The flip flop will be set with = at the firs high of the contact bounce. When the switch continue to bounce, losing contact, the input signals are R=S=, thus the flip flop remains at =. As a result, the flip flop responds only to the first high of the contact bounce. Page: 4
vidyarthiplus.com vidyarthiplus.com vidyarthiplus.com ANNA UNIVERSITY- COMBATORE B.E./ B.TECH. DEGREE EXAMINATION - JUNE 2009. ELECTRICAL & ELECTONICS ENGG. - FOURTH SEMESTER DIGITAL LOGIC CIRCUITS PART-A
More informationDHANALAKSHMI COLLEGE OF ENGINEERING, CHENNAI DEPARTMENT OF COMPUTER SCIENCE AND ENGINEERING CS6201 DIGITAL PRINCIPLES AND SYSTEM DESIGN
DHANALAKSHMI COLLEGE OF ENGINEERING, CHENNAI DEPARTMENT OF COMPUTER SCIENCE AND ENGINEERING CS6201 DIGITAL PRINCIPLES AND SYSTEM DESIGN UNIT I : BOOLEAN ALGEBRA AND LOGIC GATES PART - A (2 MARKS) Number
More informationReg. No. Question Paper Code : B.E./B.Tech. DEGREE EXAMINATION, NOVEMBER/DECEMBER Second Semester. Computer Science and Engineering
Sp 6 Reg. No. Question Paper Code : 27156 B.E./B.Tech. DEGREE EXAMINATION, NOVEMBER/DECEMBER 2015. Second Semester Computer Science and Engineering CS 6201 DIGITAL PRINCIPLES AND SYSTEM DESIGN (Common
More informationELECTRONICS & COMMUNICATION ENGINEERING PROFESSIONAL ETHICS AND HUMAN VALUES
EC 216(R-15) Total No. of Questions :09] [Total No. of Pages : 02 II/IV B.Tech. DEGREE EXAMINATIONS, DECEMBER- 2016 First Semester ELECTRONICS & COMMUNICATION ENGINEERING PROFESSIONAL ETHICS AND HUMAN
More informationDepartment of Electrical & Electronics EE-333 DIGITAL SYSTEMS
Department of Electrical & Electronics EE-333 DIGITAL SYSTEMS 1) Given the two binary numbers X = 1010100 and Y = 1000011, perform the subtraction (a) X -Y and (b) Y - X using 2's complements. a) X = 1010100
More informationKUMARAGURU COLLEGE OF TECHNOLOGY COIMBATORE
Estd-1984 KUMARAGURU COLLEGE OF TECHNOLOGY COIMBATORE 641 006 QUESTION BANK UNIT I PART A ISO 9001:2000 Certified 1. Convert (100001110.010) 2 to a decimal number. 2. Find the canonical SOP for the function
More informationComputer Science Final Examination Friday December 14 th 2001
Computer Science 03 60 265 Final Examination Friday December 14 th 2001 Dr. Robert D. Kent and Dr. Alioune Ngom Last Name: First Name: Student Number: INSTRUCTIONS EXAM DURATION IS 3 HOURs. CALCULATORS,
More informationS.Y. Diploma : Sem. III [DE/ED/EI/EJ/EN/ET/EV/EX/IC/IE/IS/IU/MU] Principles of Digital Techniques
S.Y. Diploma : Sem. III [DE/ED/EI/EJ/EN/ET/EV/EX/IC/IE/IS/IU/MU] Principles of Digital Techniques Time: 3 Hrs.] Prelim Question Paper Solution [Marks : 100 Q.1(a) Attempt any SIX of the following : [12]
More informationUnit 3 Session - 9 Data-Processing Circuits
Objectives Unit 3 Session - 9 Data-Processing Design of multiplexer circuits Discuss multiplexer applications Realization of higher order multiplexers using lower orders (multiplexer trees) Introduction
More informationS.Y. Diploma : Sem. III [CO/CM/IF/CD/CW] Digital Techniques
S.Y. Diploma : Sem. III [CO/CM/IF/CD/CW] Digital Techniques Time: 3 Hrs.] Prelim Question Paper Solution [Marks : 100 Q.1(a) Attempt any SIX of the following : [12] Q.1(a) (i) Derive AND gate and OR gate
More informationCombinational Logic Design Combinational Functions and Circuits
Combinational Logic Design Combinational Functions and Circuits Overview Combinational Circuits Design Procedure Generic Example Example with don t cares: BCD-to-SevenSegment converter Binary Decoders
More informationMAHALAKSHMI ENGINEERING COLLEGE TIRUCHIRAPALLI
DEPARTMENT: ECE MAHALAKSHMI ENGINEERING COLLEGE TIRUCHIRAPALLI 6 QUESTION BANK SUBJECT NAME: DIGITAL ELECTRONICS UNIT : Design of Sequential Circuits PART A ( Marks). Draw the logic diagram 4: Multiplexer.(AUC
More informationLOGIC CIRCUITS. Basic Experiment and Design of Electronics
Basic Experiment and Design of Electronics LOGIC CIRCUITS Ho Kyung Kim, Ph.D. hokyung@pusan.ac.kr School of Mechanical Engineering Pusan National University Outline Combinational logic circuits Output
More informationSAU1A FUNDAMENTALS OF DIGITAL COMPUTERS
SAU1A FUNDAMENTALS OF DIGITAL COMPUTERS Unit : I - V Unit : I Overview Fundamentals of Computers Characteristics of Computers Computer Language Operating Systems Generation of Computers 2 Definition of
More informationVidyalankar S.E. Sem. III [EXTC] Digital Electronics Prelim Question Paper Solution ABCD ABCD ABCD ABCD ABCD ABCD ABCD ABCD = B
. (a). (b). (c) S.E. Sem. III [EXTC] igital Electronics Prelim Question Paper Solution ABC ABC ABC ABC ABC ABC ABC ABC = B LHS = ABC ABC ABC ABC ABC ABC ABC ABC But ( ) = = ABC( ) ABC( ) ABC( ) ABC( )
More informationShow that the dual of the exclusive-or is equal to its compliment. 7
Darshan Institute of ngineering and Technology, Rajkot, Subject: Digital lectronics (2300) GTU Question ank Unit Group Questions Do as directed : I. Given that (6)0 = (00)x, find the value of x. II. dd
More informationUNIVERSITI TENAGA NASIONAL. College of Information Technology
UNIVERSITI TENAGA NASIONAL College of Information Technology BACHELOR OF COMPUTER SCIENCE (HONS.) FINAL EXAMINATION SEMESTER 2 2012/2013 DIGITAL SYSTEMS DESIGN (CSNB163) January 2013 Time allowed: 3 hours
More information( c) Give logic symbol, Truth table and circuit diagram for a clocked SR flip-flop. A combinational circuit is defined by the function
Question Paper Digital Electronics (EE-204-F) MDU Examination May 2015 1. (a) represent (32)10 in (i) BCD 8421 code (ii) Excess-3 code (iii) ASCII code (b) Design half adder using only NAND gates. ( c)
More informationUNIT II COMBINATIONAL CIRCUITS:
UNIT II COMBINATIONAL CIRCUITS: INTRODUCTION: The digital system consists of two types of circuits, namely (i) (ii) Combinational circuits Sequential circuits Combinational circuit consists of logic gates
More informationDIGITAL LOGIC CIRCUITS
DIGITAL LOGIC CIRCUITS Introduction Logic Gates Boolean Algebra Map Specification Combinational Circuits Flip-Flops Sequential Circuits Memory Components Integrated Circuits Digital Computers 2 LOGIC GATES
More informationLogic. Combinational. inputs. outputs. the result. system can
Digital Electronics Combinational Logic Functions Digital logic circuits can be classified as either combinational or sequential circuits. A combinational circuit is one where the output at any time depends
More informationChapter 4: Combinational Logic Solutions to Problems: [1, 5, 9, 12, 19, 23, 30, 33]
Chapter 4: Combinational Logic Solutions to Problems: [, 5, 9, 2, 9, 23, 3, 33] Problem: 4- Consider the combinational circuit shown in Fig. P4-. (a) Derive the Boolean expressions for T through T 4. Evaluate
More informationINSTITUTEOFAERONAUTICALENGINEERING (Autonomous) Dundigal, Hyderabad
INSTITUTEOFAERONAUTICALENGINEERING (Autonomous) Dundigal, Hyderabad - 50004 COMPUTER SCIENCE AND ENGINEERING TUTORIAL QUESTION BANK Course Name Course Code Class Branch DIGITAL LOGIC DESIGN A040 II B.
More informationSIR C.R.REDDY COLLEGE OF ENGINEERING ELURU DIGITAL INTEGRATED CIRCUITS (DIC) LABORATORY MANUAL III / IV B.E. (ECE) : I - SEMESTER
SIR C.R.REDDY COLLEGE OF ENGINEERING ELURU 534 007 DIGITAL INTEGRATED CIRCUITS (DIC) LABORATORY MANUAL III / IV B.E. (ECE) : I - SEMESTER DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING DIGITAL
More informationFundamentals of Boolean Algebra
UNIT-II 1 Fundamentals of Boolean Algebra Basic Postulates Postulate 1 (Definition): A Boolean algebra is a closed algebraic system containing a set K of two or more elements and the two operators and
More informationComputers also need devices capable of Storing data and information Performing mathematical operations on such data
Sequential Machines Introduction Logic devices examined so far Combinational Output function of input only Output valid as long as input true Change input change output Computers also need devices capable
More informationCHAPTER 7. Exercises 17/ / /2 2 0
CHAPTER 7 Exercises E7. (a) For the whole part, we have: Quotient Remainders 23/2 /2 5 5/2 2 2/2 0 /2 0 Reading the remainders in reverse order, we obtain: 23 0 = 0 2 For the fractional part we have 2
More informationMAHARASHTRA STATE BOARD OF TECHNICAL EDUCATION
MAHARASHTRA STATE BOARD OF TECHNICAL EDUCATION (Autonomous) (ISO/IEC - 27001-2005 Certified) Subject Code: 12069 SUMMER 13 EXAMINATION Model Answer Important Instructions to examiners: 1) The answers should
More informationChapter 4. Combinational: Circuits with logic gates whose outputs depend on the present combination of the inputs. elements. Dr.
Chapter 4 Dr. Panos Nasiopoulos Combinational: Circuits with logic gates whose outputs depend on the present combination of the inputs. Sequential: In addition, they include storage elements Combinational
More informationMAHARASHTRA STATE BOARD OF TECHNICAL EDUCATION (Autonomous) (ISO/IEC Certified) State any two Boolean laws. (Any 2 laws 1 mark each)
Subject Code: 17333 Model Answer Page 1/ 27 Important Instructions to examiners: 1) The answers should be examined by key words and not as word-to-word as given in the model answer scheme. 2) The model
More informationLOGIC CIRCUITS. Basic Experiment and Design of Electronics. Ho Kyung Kim, Ph.D.
Basic Experiment and Design of Electronics LOGIC CIRCUITS Ho Kyung Kim, Ph.D. hokyung@pusan.ac.kr School of Mechanical Engineering Pusan National University Digital IC packages TTL (transistor-transistor
More informationWORKBOOK. Try Yourself Questions. Electrical Engineering Digital Electronics. Detailed Explanations of
27 WORKBOOK Detailed Eplanations of Try Yourself Questions Electrical Engineering Digital Electronics Number Systems and Codes T : Solution Converting into decimal number system 2 + 3 + 5 + 8 2 + 4 8 +
More informationEE 209 Spiral 1 Exam Solutions Name:
EE 29 Spiral Exam Solutions Name:.) Answer the following questions as True or False a.) A 4-to- multiplexer requires at least 4 select lines: true / false b.) An 8-to- mux and no other logic can be used
More informationPhiladelphia University Faculty of Engineering
Philadelphia University Faculty of Engineering Marking Scheme Exam Paper BSc CE Logic Circuits (630211) Final Exam First semester ate: 03/02/2019 Section 1 Weighting 40% of the module total Lecturer: Coordinator:
More informationTime Allowed 3:00 hrs. April, pages
IGITAL ESIGN COEN 32 Prof. r. A. J. Al-Khalili Time Allowed 3: hrs. April, 998 2 pages Answer All uestions No materials are allowed uestion a) esign a half subtractor b) esign a full subtractor c) Using
More informationMAHARASHTRA STATE BOARD OF TECHNICAL EDUCATION (Autonomous) (ISO/IEC Certified)
WINTER 17 EXAMINATION Subject Name: Digital Techniques Model Answer Subject Code: 17333 Important Instructions to examiners: 1) The answers should be examined by key words and not as word-to-word as given
More informationon candidate s understanding. 7) For programming language papers, credit may be given to any other program based on equivalent concept.
WINTER 17 EXAMINATION Subject Name: Digital Techniques Model Answer Subject Code: 17333 Important Instructions to examiners: 1) The answers should be examined by key words and not as word-to-word as given
More informationELCT201: DIGITAL LOGIC DESIGN
ELCT201: DIGITAL LOGIC DESIGN Dr. Eng. Haitham Omran, haitham.omran@guc.edu.eg Dr. Eng. Wassim Alexan, wassim.joseph@guc.edu.eg Lecture 5 Following the slides of Dr. Ahmed H. Madian ذو الحجة 1438 ه Winter
More informationPhiladelphia University Student Name: Student Number:
Philadelphia University Student Name: Student Number: Faculty of Engineering Serial Number: Final Exam, First Semester: 2017/2018 Dept. of Computer Engineering Course Title: Logic Circuits Date: 29/01/2018
More informationSample Test Paper - I
Scheme G Sample Test Paper - I Course Name : Computer Engineering Group Marks : 25 Hours: 1 Hrs. Q.1) Attempt any THREE: 09 Marks a) Define i) Propagation delay ii) Fan-in iii) Fan-out b) Convert the following:
More informationPG - TRB UNIT-X- DIGITAL ELECTRONICS. POLYTECHNIC-TRB MATERIALS
SRIMAAN COACHING CENTRE-PG-TRB-PHYSICS- DIGITAL ELECTRONICS-STUDY MATERIAL-CONTACT: 8072230063 SRIMAAN PG - TRB PHYSICS UNIT-X- DIGITAL ELECTRONICS POLYTECHNIC-TRB MATERIALS MATHS/COMPUTER SCIENCE/IT/ECE/EEE
More informationPhiladelphia University Student Name: Student Number:
Philadelphia University Student Name: Student Number: Faculty of Engineering Serial Number: Final Exam, Second Semester: 2015/2016 Dept. of Computer Engineering Course Title: Logic Circuits Date: 08/06/2016
More informationDesign of Sequential Circuits
Design of Sequential Circuits Seven Steps: Construct a state diagram (showing contents of flip flop and inputs with next state) Assign letter variables to each flip flop and each input and output variable
More informationKing Fahd University of Petroleum and Minerals College of Computer Science and Engineering Computer Engineering Department
King Fahd University of Petroleum and Minerals College of Computer Science and Engineering Computer Engineering Department Page 1 of 13 COE 202: Digital Logic Design (3-0-3) Term 112 (Spring 2012) Final
More informationUnit II Chapter 4:- Digital Logic Contents 4.1 Introduction... 4
Unit II Chapter 4:- Digital Logic Contents 4.1 Introduction... 4 4.1.1 Signal... 4 4.1.2 Comparison of Analog and Digital Signal... 7 4.2 Number Systems... 7 4.2.1 Decimal Number System... 7 4.2.2 Binary
More informationS.E. Sem. III [ETRX] Digital Circuit Design. t phl. Fig.: Input and output voltage waveforms to define propagation delay times.
S.E. Sem. III [ETRX] Digital ircuit Design Time : 3 Hrs.] Prelim Paper Solution [Marks : 80. Solve following : [20].(a) Explain characteristics of logic families. [5] haracteristics of logic families are
More informationDIGITAL LOGIC DESIGN
DIGITAL LOGIC DESIGN NUMBERS SYSTEMS AND CODES Any number in one base system can be converted into another base system Types 1) decimal to any base 2) Any base to decimal 3) Any base to Any base Complements
More informationSignals and Systems Digital Logic System
Signals and Systems Digital Logic System Prof. Wonhee Kim Chapter 2 Design Process for Combinational Systems Step 1: Represent each of the inputs and outputs in binary Step 1.5: If necessary, break the
More informationTYPICAL QUESTIONS & ANSWERS
TYPICAL QUESTIONS & ANSWERS PART - I OJECTIVE TYPE QUESTIONS Each Question carries 2 marks. Choose correct or the best alternative in the following: Q.1 The NAN gate output will be low if the two inputs
More informationDesign of Combinational Logic
Pune Vidyarthi Griha s COLLEGE OF ENGINEERING, NASHIK 3. Design of Combinational Logic By Prof. Anand N. Gharu (Assistant Professor) PVGCOE Computer Dept.. 30 th June 2017 CONTENTS :- 1. Code Converter
More informationSave from: cs. Logic design 1 st Class أستاذ المادة: د. عماد
Save from: www.uotiq.org/dep cs Logic design 1 st Class أستاذ المادة: د. عماد استاذة المادة: م.م ميساء Contents Lectured One: Number system operation 1- Decimal numbers. 2- Binary numbers. 3- Octal numbers.
More informationSequential Logic. Rab Nawaz Khan Jadoon DCS. Lecturer COMSATS Lahore Pakistan. Department of Computer Science
Sequential Logic Rab Nawaz Khan Jadoon DCS COMSATS Institute of Information Technology Lecturer COMSATS Lahore Pakistan Digital Logic and Computer Design Sequential Logic Combinational circuits with memory
More informationMODEL ANSWER SUMMER 17 EXAMINATION Subject Title: Principles of Digital Techniques
MODEL ANSWER SUMMER 17 EXAMINATION Subject Title: Principles of Digital Techniques Subject Code: Important Instructions to examiners: 1) The answers should be examined by key words and not as word-to-word
More informationDigital Electronics Circuits 2017
JSS SCIENCE AND TECHNOLOGY UNIVERSITY Digital Electronics Circuits (EC37L) Lab in-charge: Dr. Shankraiah Course outcomes: After the completion of laboratory the student will be able to, 1. Simplify, design
More informationCHAPTER1: Digital Logic Circuits Combination Circuits
CS224: Computer Organization S.KHABET CHAPTER1: Digital Logic Circuits Combination Circuits 1 PRIMITIVE LOGIC GATES Each of our basic operations can be implemented in hardware using a primitive logic gate.
More informationMAHALAKSHMI ENGINEERING COLLEGE TIRUCHIRAPALLI
MAHALAKSHMI ENGINEERING COLLEGE TIRUCHIRAPALLI 6 DEPARTMENT: EEE QUESTION BANK SUBJECT NAME: DIGITAL LOGIC CIRCUITS SUBJECT CODE: EE55 SEMESTER IV UNIT : Design of Synchronous Sequential Circuits PART
More informationSRC Language Conventions. Class 6: Intro to SRC Simulator Register Transfers and Logic Circuits. SRC Simulator Demo. cond_br.asm.
Fall 2006 S333: omputer rchitecture University of Virginia omputer Science Michele o SR Language onventions lass 6: Intro to SR Simulator Register Transfers and Logic ircuits hapter 2, ppendix.5 2 SR Simulator
More informationPAST EXAM PAPER & MEMO N3 ABOUT THE QUESTION PAPERS:
EKURHULENI TECH COLLEGE. No. 3 Mogale Square, Krugersdorp. Website: www. ekurhulenitech.co.za Email: info@ekurhulenitech.co.za TEL: 011 040 7343 CELL: 073 770 3028/060 715 4529 PAST EXAM PAPER & MEMO N3
More informationPART-A. 2. Expand ASCII and BCD ASCII American Standard Code for Information Interchange BCD Binary Coded Decimal
PART-A 1. What is radix? Give the radix for binary, octal, decimal and hexadecimal Radix is the total number of digits used in a particular number system Binary - 2 (0,1) Octal - 8 (0 to 7) Decimal - 10
More informationVidyalankar S.E. Sem. III [CMPN] Digital Logic Design and Analysis Prelim Question Paper Solution
. (a) (i) ( B C 5) H (A 2 B D) H S.E. Sem. III [CMPN] Digital Logic Design and Analysis Prelim Question Paper Solution ( B C 5) H (A 2 B D) H = (FFFF 698) H (ii) (2.3) 4 + (22.3) 4 2 2. 3 2. 3 2 3. 2 (2.3)
More informationClass Website:
ECE 20B, Winter 2003 Introduction to Electrical Engineering, II LECTURE NOTES #5 Instructor: Andrew B. Kahng (lecture) Email: abk@ece.ucsd.edu Telephone: 858-822-4884 office, 858-353-0550 cell Office:
More informationELEC Digital Logic Circuits Fall 2014 Sequential Circuits (Chapter 6) Finite State Machines (Ch. 7-10)
ELEC 2200-002 Digital Logic Circuits Fall 2014 Sequential Circuits (Chapter 6) Finite State Machines (Ch. 7-10) Vishwani D. Agrawal James J. Danaher Professor Department of Electrical and Computer Engineering
More informationNumber System. Decimal to binary Binary to Decimal Binary to octal Binary to hexadecimal Hexadecimal to binary Octal to binary
Number System Decimal to binary Binary to Decimal Binary to octal Binary to hexadecimal Hexadecimal to binary Octal to binary BOOLEAN ALGEBRA BOOLEAN LOGIC OPERATIONS Logical AND Logical OR Logical COMPLEMENTATION
More informationCSE 140L Spring 2010 Lab 1 Assignment Due beginning of the class on 14 th April
CSE 140L Spring 2010 Lab 1 Assignment Due beginning of the class on 14 th April Objective - Get familiar with the Xilinx ISE webpack tool - Learn how to design basic combinational digital components -
More informationSequential vs. Combinational
Sequential Circuits Sequential vs. Combinational Combinational Logic: Output depends only on current input TV channel selector (-9) inputs system outputs Sequential Logic: Output depends not only on current
More informationVidyalankar S.E. Sem. III [ETRX] Digital Circuits and Design Prelim Question Paper Solution
S.E. Sem. III [ETRX] Digital Circuits and Design Prelim uestion Paper Solution. (a) Static Hazard Static hazards have two cases: static and static. static- hazard exists when the output variable should
More informationUnit 9. Multiplexers, Decoders, and Programmable Logic Devices. Unit 9 1
Unit 9 Multiplexers, ecoders, and Programmable Logic evices Unit 9 Outline Multiplexers Three state buffers ecoders Encoders Read Only Memories (ROMs) Programmable logic devices ield Programmable Gate
More informationAppendix B. Review of Digital Logic. Baback Izadi Division of Engineering Programs
Appendix B Review of Digital Logic Baback Izadi Division of Engineering Programs bai@engr.newpaltz.edu Elect. & Comp. Eng. 2 DeMorgan Symbols NAND (A.B) = A +B NOR (A+B) = A.B AND A.B = A.B = (A +B ) OR
More informationDigital Logic Design ENEE x. Lecture 14
Digital Logic Design ENEE 244-010x Lecture 14 Announcements Homework 6 due today Agenda Last time: Binary Adders and Subtracters (5.1, 5.1.1) Carry Lookahead Adders (5.1.2, 5.1.3) This time: Decimal Adders
More informationFunction of Combinational Logic ENT263
Function of Combinational Logic ENT263 Chapter Objectives Distinguish between half-adder and full-adder Use BCD-to-7-segment decoders in display systems Apply multiplexer in data selection Use decoders
More informationPart 1: Digital Logic and Gates. Analog vs. Digital waveforms. The digital advantage. In real life...
Part 1: Digital Logic and Gates Analog vs Digital waveforms An analog signal assumes a continuous range of values: v(t) ANALOG A digital signal assumes discrete (isolated, separate) values Usually there
More informationCombinational Logic. Mantıksal Tasarım BBM231. section instructor: Ufuk Çelikcan
Combinational Logic Mantıksal Tasarım BBM23 section instructor: Ufuk Çelikcan Classification. Combinational no memory outputs depends on only the present inputs expressed by Boolean functions 2. Sequential
More informationECEN 248: INTRODUCTION TO DIGITAL SYSTEMS DESIGN. Week 9 Dr. Srinivas Shakkottai Dept. of Electrical and Computer Engineering
ECEN 248: INTRODUCTION TO DIGITAL SYSTEMS DESIGN Week 9 Dr. Srinivas Shakkottai Dept. of Electrical and Computer Engineering TIMING ANALYSIS Overview Circuits do not respond instantaneously to input changes
More informationSchedule. ECEN 301 Discussion #25 Final Review 1. Date Day Class No. 1 Dec Mon 25 Final Review. Title Chapters HW Due date. Lab Due date.
Schedule Date Day Class No. Dec Mon 25 Final Review 2 Dec Tue 3 Dec Wed 26 Final Review Title Chapters HW Due date Lab Due date LAB 8 Exam 4 Dec Thu 5 Dec Fri Recitation HW 6 Dec Sat 7 Dec Sun 8 Dec Mon
More informationSystems I: Computer Organization and Architecture
Systems I: Computer Organization and Architecture Lecture 6 - Combinational Logic Introduction A combinational circuit consists of input variables, logic gates, and output variables. The logic gates accept
More informationCOMBINATIONAL CIRCUITS
OMINTIONL IRUITS pplications Parity Generation and heking Even Parity P e P e P P P P P P5 P P6 ( ) = m(,, ) =, Odd Parity P o P e Three-bit Parity Generator ( ) = m(,,5, ) P P P P P P5 P P6 = 6 Three-bit
More informationDE58/DC58 LOGIC DESIGN DEC 2014
Q.2 a. In a base-5 number system, 3 digit representations is used. Find out (i) Number of distinct quantities that can be represented.(ii) Representation of highest decimal number in base-5. Since, r=5
More informationLecture 2 Review on Digital Logic (Part 1)
Lecture 2 Review on Digital Logic (Part 1) Xuan Silvia Zhang Washington University in St. Louis http://classes.engineering.wustl.edu/ese461/ Grading Engagement 5% Review Quiz 10% Homework 10% Labs 40%
More informationECEN 248: INTRODUCTION TO DIGITAL SYSTEMS DESIGN. Week 7 Dr. Srinivas Shakkottai Dept. of Electrical and Computer Engineering
ECEN 248: INTRODUCTION TO DIGITAL SYSTEMS DESIGN Week 7 Dr. Srinivas Shakkottai Dept. of Electrical and Computer Engineering SEQUENTIAL CIRCUITS: LATCHES Overview Circuits require memory to store intermediate
More informationSection 3: Combinational Logic Design. Department of Electrical Engineering, University of Waterloo. Combinational Logic
Section 3: Combinational Logic Design Major Topics Design Procedure Multilevel circuits Design with XOR gates Adders and Subtractors Binary parallel adder Decoders Encoders Multiplexers Programmed Logic
More informationEE40 Lec 15. Logic Synthesis and Sequential Logic Circuits
EE40 Lec 15 Logic Synthesis and Sequential Logic Circuits Prof. Nathan Cheung 10/20/2009 Reading: Hambley Chapters 7.4-7.6 Karnaugh Maps: Read following before reading textbook http://www.facstaff.bucknell.edu/mastascu/elessonshtml/logic/logic3.html
More informationELCT201: DIGITAL LOGIC DESIGN
ELCT201: DIGITAL LOGIC DESIGN Dr. Eng. Haitham Omran, haitham.omran@guc.edu.eg Dr. Eng. Wassim Alexan, wassim.joseph@guc.edu.eg Lecture 6 Following the slides of Dr. Ahmed H. Madian محرم 1439 ه Winter
More informationGates and Flip-Flops
Gates and Flip-Flops Chris Kervick (11355511) With Evan Sheridan and Tom Power December 2012 On a scale of 1 to 10, how likely is it that this question is using binary?...4? What s a 4? Abstract The operation
More informationCombinational Logic. By : Ali Mustafa
Combinational Logic By : Ali Mustafa Contents Adder Subtractor Multiplier Comparator Decoder Encoder Multiplexer How to Analyze any combinational circuit like this? Analysis Procedure To obtain the output
More informationCHW 261: Logic Design
CHW 26: Logic Design Instructors: Prof. Hala Zayed Dr. Ahmed Shalaby http://www.bu.edu.eg/staff/halazayed4 http://bu.edu.eg/staff/ahmedshalaby4# Slide Digital Fundamentals Digital Concepts Slide 2 What?
More informationDecoding A Counter. svbitec.wordpress.com 1
ecoding A ounter ecoding a counter involves determining which state in the sequence the counter is in. ifferentiate between active-high and active-low decoding. Active-HIGH decoding: output HIGH if the
More informationMODULAR CIRCUITS CHAPTER 7
CHAPTER 7 MODULAR CIRCUITS A modular circuit is a digital circuit that performs a specific function or has certain usage. The modular circuits to be introduced in this chapter are decoders, encoders, multiplexers,
More informationDigital Logic: Boolean Algebra and Gates. Textbook Chapter 3
Digital Logic: Boolean Algebra and Gates Textbook Chapter 3 Basic Logic Gates XOR CMPE12 Summer 2009 02-2 Truth Table The most basic representation of a logic function Lists the output for all possible
More informationDigital Logic Design. Midterm #2
EECS: igital Logic esign r. nthony. Johnson s7m2s_dild7.fm - igital Logic esign Midterm #2 Problems Points. 5 2. 4 3. 6 Total 5 Was the exam fair? yes no EECS: igital Logic esign r. nthony. Johnson s7m2s_dild7.fm
More informationChapter 4: Designing Combinational Systems Uchechukwu Ofoegbu
Chapter 4: Designing Combinational Systems Uchechukwu Ofoegbu Temple University Gate Delay ((1.1).1) ((1.0).0) ((0.1).1) ((0.1).0) ((1.1) = 1 0 s = sum c out carry-out a, b = added bits C = carry in a
More informationBoolean Algebra and Digital Logic 2009, University of Colombo School of Computing
IT 204 Section 3.0 Boolean Algebra and Digital Logic Boolean Algebra 2 Logic Equations to Truth Tables X = A. B + A. B + AB A B X 0 0 0 0 3 Sum of Products The OR operation performed on the products of
More informationMAHARASHTRA STATE BOARD OF TECHNICAL EDUCATION (Autonomous) (ISO/IEC Certified) SUMMER 14 EXAMINATION Model Answer
MAHARASHTRA STATE BOARD OF TECHNICAL EDUCATION (Autonomous) (ISO/IEC 27001 2005 Certified) SUMMER 14 EXAMINATION Model Answer Subject Code : 17320 Page No: 1/34 Important Instructions to examiners: 1)
More informationCSE 140 Lecture 11 Standard Combinational Modules. CK Cheng and Diba Mirza CSE Dept. UC San Diego
CSE 4 Lecture Standard Combinational Modules CK Cheng and Diba Mirza CSE Dept. UC San Diego Part III - Standard Combinational Modules (Harris: 2.8, 5) Signal Transport Decoder: Decode address Encoder:
More informationUNIT 1. BOOLEAN ALGEBRA AND COMBINATIONAL CIRCUITS
UNIT 1. BOOLEAN ALGEBRA AND COMBINATIONAL CIRCUITS Numerical Presentation: In science, technology, business, and, in fact, most other fields of endeavour, we are constantly dealing with quantities. Quantities
More informationSequential Circuits Sequential circuits combinational circuits state gate delay
Sequential Circuits Sequential circuits are those with memory, also called feedback. In this, they differ from combinational circuits, which have no memory. The stable output of a combinational circuit
More informationDigital System Design Combinational Logic. Assoc. Prof. Pradondet Nilagupta
Digital System Design Combinational Logic Assoc. Prof. Pradondet Nilagupta pom@ku.ac.th Acknowledgement This lecture note is modified from Engin112: Digital Design by Prof. Maciej Ciesielski, Prof. Tilman
More informationCSC9R6 Computer Design. Practical Digital Logic
CSC9R6 Computer Design Practical Digital Logic 1 References (for this part of CSC9R6) Hamacher et al: Computer Organization App A. In library Floyd: Digital Fundamentals Ch 1, 3-6, 8-10 web page: www.prenhall.com/floyd/
More informationEE 209 Logic Cumulative Exam Name:
EE 209 Logic Cumulative Exam Name: 1.) Answer the following questions as True or False a.) A 4-to-1 multiplexer requires at least 4 select lines: true / false b.) An 8-to-1 mux and no other logi can be
More informationChapter 2. Review of Digital Systems Design
x 2-4 = 42.625. Chapter 2 Review of Digital Systems Design Numbering Systems Decimal number may be expressed as powers of 10. For example, consider a six digit decimal number 987654, which can be represented
More informationWritten exam with solutions IE Digital Design Friday 21/
Written exam with solutions IE204-5 Digital Design Friday 2/0 206 09.00-3.00 General Information Examiner: Ingo Sander. Teacher: Kista, William Sandvist tel 08-7904487, Elena Dubrova phone 08-790 4 4 Exam
More information