Semiconductor Memory Classification

Transcription

1 Semiconductor Memory Classification Read-Write Memory Non-Volatile Read-Write Memory Read-Only Memory Random Access Non-Random Access EPROM E 2 PROM Mask-Programmed Programmable (PROM) SRAM FIFO FLASH DRAM LIFO Shift Register CAM 1

2 Memory Timing: Definitions Read cycle READ Read access Read access Write cycle WRITE Data valid Write access DATA Data written 2

3 N w o r d s D e c o d e r Memory Architecture: Decoders M bits M bits S 0 S 1 S 2 Word 0 Word 1 Word 2 Storage cell A 0 A 1 S 0 Word 0 Word 1 Word 2 Storage cell S N - 2 Word N - 2 A K - 1 Word N - 2 S N - 1 Word N - 1 K = log 2 N Word N - 1 Input-Output (M bits) Input-Output (M bits) Intuitive architecture for N x M memory Too many select signals: N words => N select signals Decoder reduces the number of select signals K = log 2 N 3

4 Array-Structured Memory Architecture Problem: ASPECT RATIO or HEIGHT >> WIDTH - 2 L 2 K Bit line Storage cell A K A K11 - A L 21 - Row Decoder Word line M.2 K Sense amplifiers / Drivers Amplify swing to rail-to-rail amplitude A 0 A K21 - Column decoder Selects appropriate word Input-Output (M bits) 4

5 Hierarchical Memory Architecture Block 0 Block i Block P Row address Column address Block address Control circuitry Block selector Global amplifier/driver Global data bus I/O Advantages: 1. Shorter wires within blocks (word and bit lines) 2. Block address activates only 1 block => power savings 5

6 Memory Timing: Approaches Address bus Row Address Column Address RAS CAS Address Bus Address Address transition initiates memory operation RAS-CAS timing DRAM Timing Multiplexed Adressing SRAM Timing Self-timed 6

7 Read-Only Memory Cells 1 WL WL WL 0 WL WL WL GND Diode ROM MOS ROM 1 MOS ROM 2 7

8 MOS OR ROM [0] [1] [2] [3] WL[0] WL[1] WL[2] WL[3] V bias Pull-down loads 8

9 MOS NOR ROM Pull-up devices WL[0] WL [1] GND WL [2] GND WL [3] [0] [1] [2] [3] 9

10 Precharged MOS NOR ROM φ pre Precharge devices WL [0] WL [1] GND WL [2] GND WL [3] [0] [1] [2] [3] PMOS precharge device can be made as large as necessary, but clock driver becomes harder to design. 10

11 MOS NAND ROM Pull-up devices [0] [1] [2] [3] WL [0] WL [1] WL [2] WL [3] All word lines high by default with exception of selected row 11

12 Non-Volatile Memories The Floating-gate gate transistor (FAMOS) Source Floating gate Gate Drain D t ox G n + Substrate p t ox n +_ S Device cross-section Schematic symbol 12

13 Floating-Gate Transistor Programming 20 V 0 V 5 V 10 V 5 V 20 V - 5 V 0 V V 5 V S D S D S D Avalanche injection Removing programming voltage leaves charge trapped Programming results in higher V T. 13

14 A Programmable-Threshold Transistor I D 0 -state 1 -state I D ON DV Δ T OFF V WL V GS 14

15 FLOTOX EEPROM Floating gate Source Gate Drain I nm n + Substrate p n + 10 nm -10 V 10 V V GD FLOTOX transistor Fowler-Nordheim I-V characteristic 15

16 EEPROM Cell WL Absolute threshold control is hard Unprogrammed transistor might be depletion 2 transistor cell 16

17 Flash EEPROM: ETOX device Control gate Floating gate erasure n + source programming p-substrate Thin tunneling oxide n + drain 17

18 Basic Operations in a NOR Flash Memory: Write 12 V 0 1 G 6 V 12 V WL 0 S D 0 V 0 V WL 1 6 V 0 V 18

19 Basic Operations in a NOR Flash Memory: Read 5 V G 1 V 5 V 0 1 WL 0 S D 0 V 0 V WL 1 1 V 0 V 19

20 Basic Operations in a NOR Flash Memory: Erase cell array V G 0 V WL 0 S D 12 V 0 V WL 1 open open 20

21 Read-Write Memories (RAM) STATIC (SRAM) Data stored as long as supply is applied Large (6 transistors/cell) Fast Differential DYNAMIC (DRAM) Periodic refresh required Small (1-3 transistors/cell) Slower Single Ended 21

22 6-transistor CMOS SRAM Cell WL M 2 M 4 Q M Q M 5 6 M 1 M 3 22

23 CMOS SRAM Analysis (Write) WL M 4 Q = 0 M 6 M 5 Q = 1 M 1 A 0 is written in the cell by setting to 1 and to 0 23

24 CMOS SRAM Analysis (Read) WL M 4 Q = 0 Q = 1 M 6 M 5 M 1 C bit C bit and are precharged to 24

25 Resistance-load SRAM Cell WL R L R L M 3 Q Q M 4 M 1 M 2 Static power dissipation -- Want R L large Bit lines precharged to to address t p problem 25

26 3-Transistor DRAM Cell 1 2 WWL RWL WWL M 3 RWL M 1 X M 2 X - V T C S V T ΔV No constraints on device ratios Reads are non-destructive Value stored at node X when writing a 1 = V WWL -V Tn 26

27 1-Transistor DRAM Cell WL WL Write 1 Read 1 M 1 x C S X GND 2 - V T /2 V sensing DD /2 C Write: C S is charged or discharged by asserting WL and. Read: Charge redistribution takes places between bit line and storage capacitance Δ V V ( ) = V = V V PRE x PRE C S C + C S Voltage swing is small; typically around 250 mv. 27

28 Sense Amp Operation V V(1) V PRE ΔV(1) Sense amp activated Word line activated V(0) t 28

29 DRAM Cell Observations 1T DRAM requires a sense amplifier for each bit line, due to charge redistribution read-out. DRAM memory cells are single ended in contrast to SRAM cells. The read-out of the 1T DRAM cell is destructive; read and refresh operations are necessary for correct operation. Unlike 3T cell, 1T cell requires presence of an extra capacitance that must be explicitly included in the design. When writing a 1 into a DRAM cell, a threshold voltage is lost. This charge loss can be circumvented by bootstrapping the word lines to a higher value than 29

30 Static CAM Memory Cell Word Bit CAM Bit Bit CAM Bit Bit M4 M8 M6 M9 M7 M5 Bit Word CAM CAM Word Match S M3 int M2 S M1 Wired-NOR Match Line 30

31 Periphery Decoders Input/Output Buffers Sense Amplifiers Control / Timing Circuitry 31

32 Sense Amplifiers t p = C ΔV I av make ΔV as small as possible large small Idea: Use Sense Amplifier small transition s.a. input output 32

33 Differential Sense Amplifier M 3 M 4 y Out bit M 1 M 2 bit SE M 5 Directly applicable to SRAMs 33

34 Latch-Based Sense Amplifier (DRAM) EQ SE SE Initialized in its meta-stable point with EQ Once adequate voltage gap created, sense amp enabled with SE Positive feedback quickly forces output to a stable operating point. 34

35 Single-to to-differential Conversion WL Cell x Diff. S.A. x V ref Output How to make a good V ref? 35

36 Open bitline architecture with dummy cells EQ L L 1 L 0 R 0 SE R 1 L L R C S C S C S SE C S C S C S Dummy cell Dummy cell 36

37 Semiconductor Memory Trends Memory Size as a function of time: x 4 every three years 37

38 Trends in Memory Cell Area 38