Thin Film Transistors (TFT)

Transcription

1 Thin Film Transistors (TFT) a-si TFT - α-si:h (Hydrogenated amorphous Si) deposited with a PECVD system (low temp. process) replaces the single crystal Si substrate. - Inverted staggered structure with bottom-gate scheme. - i-α-si forms a channel. - n + -α-si forms source and drain. - Nitride is used for etch-stop layer for patterning the n + -α-si. - Carrier mobility is very low: < 1cm 2 /V-s 1

2 Thin Film Transistors (TFT) - Subthreshold characteristics 3 µm MOSFET a-si TFT 2

3 Thin Film Transistors (TFT) poly-si TFT - Higher carrier mobility: 10 ~ 1000cm 2 /V-s Better drive capability (I D, g m ) - Top-gate structure scheme. - self-aligned implantation for S/D - LPCVD poly-si : High temp. process (> 600 o C) - Expensive quartz substrate. laser recrystallization process is used by depositing a-si on the glass. 3

4 Thin Film Transistors (TFT) TFT Process Buffer Oxide a-si Glass SiO 2 Gate Oxide LPCVD α-si (500A ) ELC (RT, 400 ) Poly-Si Glass Gate Oxide (1000A ) Gate Gate (Al 3000A ) S/D S/D Ion Doping (n-, n+, p+) LDD Glass Laser Activation Insulator (SiO 2 ) S/D Gate S/D Contact and Metal (Al) Channel Glass 4

5 Thin Film Transistors (TFT) TFT LCD one pixel 300 μm signal electrodes G One Pixel ) CF Substrate Common Electrode control electrodes S D pixel electrode pixel electrode ) TFT Substrate TFT Pixel Electrode Data Line Gate Line pixel electrode pixel electrode 5

6 Thin Film Transistors (TFT) Liquid Crystal Off (Dark) ON (Bright) LC Layer Incident Light 6

7 DRAM - Write cycle: MOSFET is turned on (bias the word line) so that the logic state of the bit line is transferred to the storage capacitor. - Refresh: Data need to be refreshed periodically within an interval (2~50 ms) because the small but non-negligible currents are leaking from the capacitors. 1T-1C cell 7

8 - Charge conservation law and charge sharing WL Before switch (Transistor) on node1 v B L node2 v C S After switch on node1= v, node2 = v C node1 = node2 = v C v by charge conservation law P node1 v B node2 v C C (v v ) + C v = ( C + C )v S C P S L C C S CS C v = (v v ) + v C + C C + C C P S S 8

9 - Vertical structure for typical stack cell BEOL SN cont. cont. landing pad ILD3 ILD2 MEOL WL STI P-well gate STI ILD1 FEOL P-sub 9

10 - Vertical structure for DRAM cells 3.00 μm 10

11 - Parasitic bit line capacitance Total Parasitic bit line capacitance C S C N * (, = C i ) where N is the number of cells/ Components of parasitic capacitance Junction capacitance between and Sub = C,SUB Interlayer capacitance between and WL = C,WL Interlayer capacitance between and SN = C,SN Interlayer capacitance between and PN = C,PN Interlayer capacitance between and = C, 11

12 - Sensing signal voltage v S = ½ (v H - v L ) v = v H when v C = V cc (data1 storage) v = v L when v C = 0 (data0 storage) CS C CS C vh v L = ( VCC v P ) + v ( (0 v P ) + v ) C + C C + C C + C C + C = C S S S S S CS + C V CC v = S 1 VCC 2 C 1 + C S - only dependent on supply voltage(v cc ) and ratio of cap./cell cap.(c /C S ) 12

13 - Change of the voltages of storage node and bit line before and after switch on Before switch on After switch on node2 v C node1 v = 1/2 V CC v C S C C S C Voltage at storage node Precharge voltage at Voltage after charge sharing v C v v v H (V cc ) ½ V cc v S v s 1 V CC = 2 C 1 + C S v L (0) 13

14 SRAM Flip-flop: Two cross-coupled CMOS inverters The output of the inverter is connected to the input of the other inverter. No refresh is required and the operation of the SRAM is static since the logic state is sustained as long as the power is applied. NMOS PMOS PMOS NMOS NMOS NMOS 14

15 Non-volatile MOS devices - EPROM (Erasable Programmable ROM) : Erasing is accomplished by UV - EEPROM (Electrically Erasable Programmable ROM) : : Erasing is accomplished electrically. 15