Nyquist-Rate D/A Converters. D/A Converter Basics.

Transcription

1 Nyquist-Rate D/A Converters David Johns and Ken Martin slide 1 of 20 D/A Converter Basics. B in D/A is a digital signal (or word), B in b i B in = b N 2 N equals a 1 or a 0 (i.e. a binary digit). an analog reference; output. = ( b N 2 N ) (1) (2) Define V LSB to be LSB signal change, V LSB 2 N slide 2 of 20

2 D/A Converter Basics For errors, define units of LSB 1LSB = 1 2 N A multiplying D/A allows to be a varying input proportional to multiplication of and B in. For ideal D/A, output signal is a well defined value no quantization error! V out 1 3/4 1/2 1/ (100) V LSB = 1/4 = 1 LSB B in slide 3 of 20 D/A Resistor-String (Hamadé, JSSC, Dec. 1978) Guaranteed monotonic Integrated with better than 10-bits absolute accuracy. 2 N Resistors Delay through the switch network major speed limitation Resistors might be realized using polysilicon If n-channel only used, can be laid out small Requires 2 N resistors 3-bit slide 4 of 20

3 D/A Resistor-String Digital Decoding Higher speed implementation (less resistance thru transistors) 2 N Resistors 3 to 1 of 8 decoder Large cap load on buffer input Can pipeline digital decoding for faster speed Requires 2 N resistors 3-bit slide 5 of 20 Folded-resistor-string D/A (Abrial, JSSC, Dec. 1988) 2 to 1 of 4 decoder word lines bit lines Less capacitance load over the single bus approach Requires 2 N resistors 2 to 1 of 4 decoder slide 6 of 20

4 Binary-Weighted Resistor D/A s. R F 4R 8R 16R = R F V ref R 8R Only N resistors Resistor and current ratios are on the order of 2 N No guarantee of monotonicity. Prone to glitches (more later). (3) slide 7 of 20 Reduced Spread Binary Resistor D/A R F 4R 4R 4R 3R R 1 V = --( V A 4 ref ) Reduced resistor spread Keep repeating this procedure > R- ladder slide 8 of 20

5 R- Based D/A Converters R 1 R' 1 R 2 R' 2 R 3 R' 3 R 4 R' 4 R R R R R R R' 4 = R 4 = = R R' 3 = R + R 4 = R 3 = R' 3 = R Small size, good matching (only R and ) (4) slide 9 of 20 R- Based Resistor Ladders Example D/A converter R F I r I r I r R 2 R 4 R 8 I r I r I r 2 I r 4 I r 8 Currents through the switches are scaled Should scale switch sizes for good accuracy No node voltage changes except for output > fast slide 10 of 20

6 R- Based Resistor Ladders Slower circuit having equal current through switches R R f R R R V o I I I -5V I Node voltages change slower circuit No need to scale switch sizes (smaller size) slide 11 of 20 Glitches Different delays for switching the different currents MSB change often worst case I 1 R f t I 2 I 1 + I 2 t t τ 1 τ 2 I 1 I 2 Glitches can be minimized by limiting the bandwidth but that slows down circuit Use thermometer code to reduce glitches slide 12 of 20

7 Charge-Redistribution SC D/A s Programmable SC gain amplifier. 16C φ 1 φ 1 ( φ 2 ) 8C 4C 2C C φ 2 ( φ 1 ) φ 1 φ 2 C 2 φ 2 Sign bit realized by interchanging input phases Carefully clock-waveforms required to minimize voltage dependency of clock-feed-through. Digital codes should be changed when input side of capacitors are connected to ground. Requires extra digital complexity. slide 13 of 20 Decimal Thermometer D/A Converters Binary Thermometer Code d 1 d 2 d 3 d 4 d 5 d 6 d Binary-to-thermometer code conversion d 1 d 2 d 3 d 4 d 5 d 6 d 7 R f d 1 d 2 d 3 d 4 d 5 d 6 d 7 R R R R R R R slide 14 of 20

8 Thermometer Code D/A Converter C 2 N C Top Capacitors are Connected to Ground C 0 2 C 2 Bottom Capacitors are Connected to C C C 2 N unit sized caps Guaranteed monotonic Much lower glitching Low DNL slide 15 of 20 Current-Mode D/A s Thermometer-code High-speed, output feeds directly to resistor Important that delay to all the switches are equal. Col. Column Decoder Overlapped clocks much better than having nonoverlapped clocks. Row d i d i Bias d i Row Decoder I - Src Array slide 16 of 20

9 Current-Steered D/A [Colles, 88] Operates as cascode current sources. For max speed, keep voltage swing at source of Q1 small (just turned off) Switching feed-through from the digital input enhances switching speed. + Q 4 Q 3 V bias d d 1 2 Q Q 1 2 V bias V bias R ref 50 Ω slide 17 of 20 Segmented D/A Schoeff, 79; Saul, 85; Grebene, R/2 Combine thermometer binary and Accuracy needed for LSB reduced Glitches reduced Very popular + - R R R R 2 MSB s 4 Bit Binary LSB - Segment slide 18 of 20

10 Dynamically-Matched Current Sources Schouwenaar, 88 Shift Register I d1 I d2 I d3 I d4 I d5 I 64 To Switch D/A Network I ref Dynamic technique with current switching for realizing very well-matched current sources Up to 16 bit accuracy Each current source is calibrated with a single reference 64 used so D/A can continue operating Achieved 92 db SNDR, and 20 mw with 3V. Used for audio application slide 19 of 20 Dynamically-Matched Current Sources I ref S 2 C gs I d1 I out S 1 I ref C gs S 2 I out I d1 0.9I ref Current source 0.9I added so a low gm device used (W/L equal to 10/75) Re-calibrate before leakage causes 0.5LSB error S1 Q 1 0.9I ref Q 1 Calibration Regular Usage Minimize clock-feedthrough and charge-injection by having capacitance C gs and bias voltage large V GS Implies voltage error causes less current deviation. slide 20 of 20