ESE 570: Digital Integrated Circuits and VLSI Fundamentals

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1 ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 21: April 4, 2017 Memory Overview, Memory Core Cells Penn ESE 570 Spring 2017 Khanna

2 Today! Memory " Classification " ROM Memories " RAM Memory " Architecture " Memory core " SRAM " DRAM " Periphery (time permitting) Penn ESE 570 Spring Khanna 2

3 Memory Overview Penn ESE 570 Spring 2017 Khanna

4 CPU Memory Hierarchy CPU Chip L1 on-cpu cache 1k to 64 k SRAM (register file) off-chip cache memory L2 L3 L4 64k to 4M 4M to 32M 8M SRAM or DRAM Penn ESE 570 Spring 2017 Khanna 4

5 Locality and Cacheing! Memory hierarchies exploit locality by cacheing (keeping close to the processor) data likely to be used again! This is done because we can build " large, slow memories OR " small, fast memories BUT " we can t build large, fast memories! If hierarchy works, we get the illusion of SRAM access time with disk based memory capacity. " SRAM (static RAM) ns access time, very expensive (on-cpu faster) " DRAM (dynamic RAM) ns, cheaper " Disk -- access time measured in milliseconds, very cheap Penn ESE 570 Spring 2017 Khanna 5

6 Semiconductor Memory Classification RWM NVRWM ROM Random Access Non-Random Access EPROM E 2 PROM Mask-Programmed Programmable (PROM) SRAM FIFO FLASH DRAM LIFO Shift Register CAM Penn ESE 570 Spring Khanna

7 Memory Architecture: Core M bits M bits N Words S 0 S 1 S 2 S N-2 S N_1 Word 0 Word 1 Word 2 Word N-2 Word N-1 Storage Cell A 0 A 1 A K-1 Decoder S 0 Word 0 Word 1 Word 2 Word N-2 Word N-1 Storage Cell Input-Output (M bits) Input-Output (M bits) N words => N select signals Too many select signals Decoder reduces # of select signals K = log 2 N Penn ESE 570 Spring Khanna

8 Memory Architecture: Decoders M bits M bits N Words S 0 S 1 S 2 S N-2 S N_1 Word 0 Word 1 Word 2 Word N-2 Word N-1 Storage Cell A 0 A 1 A K-1 Decoder S 0 Word 0 Word 1 Word 2 Word N-2 Word N-1 Storage Cell Input-Output (M bits) Input-Output (M bits) N words => N select signals Too many select signals Decoder reduces # of select signals K = log 2 N Penn ESE 570 Spring Khanna

9 Array-Structured Memory Architecture Problem: ASPECT RATIO or HEIGHT >> WIDTH 2 L-K Bit Line Storage Cell A K A K+1 A L-1 Row Decoder Word Line Sense Amplifiers / Drivers M.2 K Amplify swing to rail-to-rail amplitude A 0 A K-1 Column Decoder Selects appropriate word Input-Output (M bits) Penn ESE 570 Spring Khanna

10 Latches/Register Can Store a State! Build master-slave register from pair of latches! Control with non-overlapping clocks Penn ESE 570 Spring Khanna 10

11 ROM Memories Penn ESE 570 Spring Khanna 11

12 MOS NOR ROM Pull-up devices WL[0] WL[1] GND WL[2] WL[3] GND BL[0] BL[1] BL[2] BL[3] Penn ESE 570 Spring Khanna

13 MOS NOR ROM Pull-up devices WL[0] WL[1] GND WL[2] GND WL[3] BL[0] BL[1] BL[2] BL[3] Penn ESE 570 Spring Khanna

14 MOS NOR ROM Pull-up devices WL[0] WL[1] GND WL[2] GND WL[3] BL[0] BL[1] BL[2] BL[3] Penn ESE 570 Spring Khanna

15 MOS NAND ROM BL[0] BL[1] BL[2] BL[3] Pull-up devices WL[0] WL[1] WL[2] WL[3] All word lines high by default with exception of selected row Penn ESE 570 Spring Khanna

16 MOS NAND ROM Pull-up devices WL[0] WL[1] 0 BL[0] BL[1] BL[2] BL[3] WL[2] WL[3] All word lines high by default with exception of selected row Penn ESE 570 Spring Khanna

17 MOS NAND ROM Pull-up devices WL[0] WL[1] WL[2] WL[3] BL[0] BL[1] BL[2] BL[3] All word lines high by default with exception of selected row Penn ESE 570 Spring Khanna

18 Non-Volatile Memory ROM PseudonMOS NOR gate Penn ESE 570 Spring 2017 Khanna 18

19 Contact-Mask Programmable ROM Penn ESE 570 Spring 2017 Khanna 19

20 Contact-Mask Programmable ROM Penn ESE 570 Spring 2017 Khanna 20

21 Read-Write Memories (RAM)! Static (SRAM) " Data stored as long as supply is applied " Large (6 transistors/cell " Fast " Differential! Dynamic (DRAM) " Periodic refresh required " Small (1-3 transistors/cell) " Slower " Single ended Penn ESE 570 Spring Khanna

22 Latches/Register Can Store a State! Build master-slave register from pair of latches! Control with non-overlapping clocks Penn ESE 570 Spring Khanna 22

23 Gate Based Latch! How many transistors in this latch? Penn ESE 570 Spring Khanna 23

24 6T SRAM Cell! Cell size accounts for most of memory array size! 6T SRAM Cell " Used in most commercial chips " Data stored in cross-coupled inverters! Read: " Precharge BL, BL BL bit " Raise WL word WL! Write: " Drive data onto BL, BL " Raise WL BL bit_b Penn ESE 570 Spring 2017 Khanna 24

25 6-transistor CMOS SRAM Cell WL M2 M4 M5 Q Q M6 M1 M3 BL BL Penn ESE 570 Spring Khanna

26 6-transistor CMOS SRAM Cell WL M2 M4 M5 Q Q M6 M1 M3 BL BL Penn ESE 570 Spring Khanna

27 6-transistor CMOS SRAM Cell WL Assume 1 is stored (Q=1) M5 M2 Q 0 M4 Q 1 M6 M1 M3 BL BL Penn ESE 570 Spring Khanna

28 CMOS SRAM Analysis (stored 1) WL BL M4 BL M5 0 Q = 0 1 Q = 1 M6 M1 C bit C bit Penn ESE 570 Spring Khanna

29 6-transistor CMOS SRAM Cell WL Assume 1 is stored (Q=1) Read Operation: - First bitlines get VDD precharged high (Vdd) - Then wordline goes high (Vdd) BL M5 M2 Q 0 M1 M4 M3 Q 1 M6 BL VDD Penn ESE 570 Spring Khanna

30 CMOS SRAM Analysis (Read) VDD WL BL M4 BL M5 0 Q = 0 1 Q = 1 M6 VDD V M1 VDD C bit C bit Penn ESE 570 Spring Khanna

31 CMOS SRAM Analysis (Read) VDD WL BL M4 BL M5 0 Q = 0 1 Q = 1 M6 VDD V M1 VDD C bit C bit ( ) 2 = k n,m1 ( V Tn )ΔV ΔV 2 k n,m5 ΔV V Tn 2 Penn ESE 570 Spring Khanna

32 CMOS SRAM Analysis (Read) VDD WL BL M4 BL M5 0 Q = 0 1 Q = 1 M6 VDD V M1 VDD C bit C bit k n,m5 k n,m1 = W L W L 5 1 = ( V Tn )ΔV ΔV 2 2 ( ΔV V Tn ) 2 Penn ESE 570 Spring Khanna

33 CMOS SRAM Analysis (Read) VDD WL BL M4 BL M5 0 Q = 0 1 Q = 1 M6 VDD V M1 VDD C bit C bit k n,m5 k n,m1 = W L W L Penn ESE 570 Spring Khanna 5 1 = ( V Tn )ΔV ΔV 2 2 ( ΔV V Tn ) 2 ΔV =V Tn W L W L 5 1 = ( 1.5V Tn )V Tn 2V Tn ( ) 2

34 CMOS SRAM Analysis (Read) Voltage Rise (V) Cell Ratio (CR) Penn ESE 570 Spring 2017 Khanna

35 6-transistor CMOS SRAM Cell WL Assume 1 is stored (Q=1) Write Operation: - Want to write a 0 VDD - First drive bitlines with input data - Then wordline goes high (Vdd) BL M5 M2 Q 0 M1 M4 M3 Q 1 M6 BL 0 Penn ESE 570 Spring Khanna

36 CMOS SRAM Analysis (Write) VDD WL M4 M5 0 Q = 0 Q = 1 1 M6 M1 VDD BL = 1 0 BL = 0 Penn ESE 570 Spring Khanna

37 CMOS SRAM Analysis (Write) VDD WL M4 M5 0 Q = 0 Q = 1 1 M6 M1 VDD BL = 1 0 BL = 0 ( ) 2 = k n,m 4 ( V Tp )V Q V Q k n,m 6 V Tn 2 2 Penn ESE 570 Spring Khanna

38 CMOS SRAM Analysis (Write) VDD WL M4 M5 0 Q = 0 Q = 1 1 M6 M1 VDD BL = 1 0 BL = 0 k n,m 4 k n,m 6 = ( V Tn ) 2 ( V Tp )V Q V 2 Q 2 Penn ESE 570 Spring Khanna

39 CMOS SRAM Analysis (Write) VDD WL M5 0 Q = 0 M4 Q = 1 1 M6 PR = W 4 L 4 W 6 L 6 M1 VDD BL = 1 0 BL = 0 k n,m 4 k n,m 6 = ( V Tn ) 2 ( V Tp )V Q V 2 Q 2 Penn ESE 570 Spring Khanna V Q =V Tn k n,m 4 k n,m 6 = ( V Tn ) 2 ( V Tp )V Tn V 2 Tn 2

40 CMOS SRAM Analysis (Write) PR = W 4 L 4 W 6 L 6 Penn ESE 570 Spring 2017 Khanna

41 DRAM! Smaller than SRAM! Require data refresh to compensate for leakage Penn ESE 570 Spring 2017 Khanna 41

42 3-Transistor DRAM Cell BL1 BL2 WWL RWL WWL RWL M1 X M2 M3 X BL1 -V T C S BL2 -V T ΔV No constraints on device ratios Reads are non-destructive Value stored at node X when writing a 1 = V WWL -V Tn Penn ESE 570 Spring 2017 Khanna

43 1-Transistor DRAM Cell BL WL WL Write "1" Read "1" M1 C S X GND V T C BL BL /2 sensing /2 Write: C S is charged or discharged by asserting WL and BL. Read: Charge redistribution takes places between bit line and storage capacitance Penn ESE 570 Spring 2017 Khanna C ΔV V BL V ( PRE V BIT V ) S = = PRE C S + C BL Voltage swing is small; typically around 250 mv.

44 DRAM Cell Observations 1T DRAM requires a sense amplifier for each bit line, due to charge redistribution read-out. DRAM memory cells are single ended in contrast to SRAM cells. The read-out of the 1T DRAM cell is destructive; read and refresh operations are necessary for correct operation. Unlike 3T cell, 1T cell requires presence of an extra capacitance that must be explicitly included in the design. When writing a 1 into a DRAM cell, a threshold voltage is lost. This charge loss can be circumvented by bootstrapping the word lines to a higher value than. Penn ESE 570 Spring 2017 Khanna

45 Memory Periphery Penn ESE 570 Spring 2017 Khanna

46 Periphery! Decoders! Sense Amplifiers! Input/Output Buffers! Control/Timing Circuitry Penn ESE 570 Spring Khanna

47 Array Architecture! 2 n words of 2 m bits each! Good regularity easy to design! Very high density if good cells are used Penn ESE 570 Spring 2017 Khanna 47

48 Array Architecture! 2 n words of 2 m bits each! Good regularity easy to design! Very high density if good cells are used Penn ESE 570 Spring 2017 Khanna 48

49 Array Architecture! 2 n words of 2 m bits each! Good regularity easy to design! Very high density if good cells are used Penn ESE 570 Spring 2017 Khanna 49

50 Array Architecture! 2 n words of 2 m bits each! Good regularity easy to design! Very high density if good cells are used Penn ESE 570 Spring 2017 Khanna 50

51 Decoders Penn ESE 570 Spring 2017 Khanna

52 Decoders! n:2 n decoder consists of 2 n n-input AND gates " One output needed for each row of memory " Build AND from NAND or NOR gates Static CMOS A1 A0 word0 word1 A1 A word word2 word3 Penn ESE 570 Spring 2017 Khanna 52

53 Large Decoders! For n > 4, NAND gates become slow " Break large gates into multiple smaller gates A3 A2 A1 A0 word0 word1 word2 word3 word15 Penn ESE 570 Spring 2017 Khanna 53

54 Predecoding! Many of these gates are redundant " Factor out common gates into predecoder " Saves area " Same path effort A3 A2 A1 A0 predecoders 1 of 4 hot predecoded lines word0 word1 word2 word3 word15 Penn ESE 570 Spring 2017 Khanna 54

55 Row Select: Precharge NAND Penn ESE 570 Spring 2017 Khanna 55

56 Row Select: Precharge NOR Penn ESE 570 Spring 2017 Khanna 56

57 Column Circuitry & Bit-line Conditioning Penn ESE 570 Spring 2017 Khanna

58 Array Architecture! 2 n words of 2 m bits each! Good regularity easy to design! Very high density if good cells are used Penn ESE 570 Spring 2017 Khanna 58

59 Column Circuitry! Some circuitry is required for each column " Bitline conditioning " Precharging " Driving input data to bitline " Sense amplifiers " Column multiplexing (AKA Column Decoders) Penn ESE 570 Spring 2017 Khanna 59

60 Bitline Conditioning! Precharge bitlines high before reads BL bit φ BL bit_b Penn ESE 570 Spring 2017 Khanna 60

61 Bitline Conditioning! Precharge bitlines high before reads BL bit φ BL bit_b Penn ESE 570 Spring 2017 Khanna 61

62 Bitline Conditioning! Precharge bitlines high before reads BL bit φ BL bit_b! What if pre-charged to Vdd/2? " Pros: reduces read-upset " Challenge: generate Vdd/2 voltage on chip Penn ESE 570 Spring 2017 Khanna 62

63 Sense Amplifiers! Bitlines have many cells attached " Ex: 32-kbit SRAM has 128 rows x 256 cols " 128 cells on each bitline! t pd (C/I) ΔV " Even with shared diffusion contacts, 64C of diffusion capacitance (big C) " Discharged slowly through small transistors in each memory cell (small I)! Sense amplifiers are triggered on small voltage swing V (ΔV) BL V(1) V PRE ΔV Penn ESE 570 Spring 2017 Khanna Sense amp activated Word line activated V(0) t 63

64 Idea! Memory for compact state storage! Share circuitry across many bits " Minimize area per bit # maximize density! Aggressively use: " Pass transistors, Ratioing " Precharge, Amplifiers to keep area down Penn ESE 570 Spring Khanna 64

65 Admin! Homework 7 due Thursday " Extra Credit due Sunday! Project partners due Thursday " your team names to me " Final Project " Design and layout memory " Handout posted before Thursday class " Due 4/25 (last day of class) " Everyone gets an extension until 5/3 (day of final exam) Penn ESE 570 Spring Khanna 65

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