CMPE12 - Notes chapter 1. Digital Logic. (Textbook Chapter 3)
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1 CMPE12 - Notes chapter 1 Digital Logic (Textbook Chapter 3)
2 Transistor: Building Block of Computers Microprocessors contain TONS of transistors Intel Montecito (2005): 1.72 billion Intel Pentium 4 (2000): 48 million IBM PowerPC 750FX (2002): 38 million IBM/Apple PowerPC G5 (2003): 58 million Intel 8080 (1974): 6000 Intel 4004 (1971): 2500 CMPE12 Winter 2008 J. Ferguson 2-2
3 Moore s Law The number of active components per chip will double every 18 months CMPE12 Winter 2008 J. Ferguson 2-3
4 Metal-Oxide-Semiconductor (MOS) transistor CMPE12 Winter 2008 J. Ferguson 2-4
5 How big is a transistor? If a CPU die was as big as this whole classroom, a transistor would be CMPE12 Winter 2008 J. Ferguson 2-5
6 Transistors = switches Logically, each transistor is used as a switch Combined to implement logic functions AND, OR, NOT Combined to build higher-level structures Adder, multiplexer, decoder, register, memory Combined to build processor LC-3 CMPE12 Winter 2008 J. Ferguson 2-6
7 Nature of Digital Signals/Information Our world is analog: real number values of energy, mass, time. However a computer signal can only have one of two values: 0 voltage and high voltage. We will call these 0 and 1. This simplification leads to tremendous advantages for computation: detection, self-restoration, etc. CMPE12 Winter 2008 J. Ferguson 2-7
8 Combinational logic is used to create a digital function CMPE12 Winter 2008 J. Ferguson 2-8
9 Basic one and two-input logic gates and functions CMPE12 Winter 2008 J. Ferguson 2-9
10 Use transistors to make combinational logic or Simplification: one output for now CMPE12 Winter 2008 J. Ferguson 2-10
11 Each signal is connected to either a 0 or a 1 1 or Vcc 1 or Vcc Or But never both! 0 or Ground 0 or Ground Transistors make those paths depending the inputs to the gate! CMPE12 Winter 2008 J. Ferguson 2-11
12 n-type MOS transistor n-type MOS (nmos) makes path towards 0 when gate is 1. when Gate has positive voltage, short circuit between #1 and #2 (switch closed) when Gate has zero voltage (0), open circuit between #1 and #2 (switch open) Gate = 1 Gate = 0 CMPE12 Winter 2008 J. Ferguson 2-12
13 p-type MOS transistor p-type is complementary to n-type makes path to 1 when gate is 0 when Gate has positive voltage, open circuit between #1 and #2 (switch open) when Gate has zero voltage, short circuit between #1 and #2 (switch closed) Gate = 1 Gate = 0 CMPE12 Winter 2008 J. Ferguson 2-13
14 CMOS circuit Complementary MOS Uses both n-type and p-type MOS transistors p-type Connects path towards 1 when gate input is 0 n-type Connects path towards 0 when gate input is 1 CMPE12 Winter 2008 J. Ferguson 2-14
15 Inverter (NOT gate) In Out In Out 0 V 2.9 V V 0 V 1 0 Truth Table CMPE12 Winter 2008 J. Ferguson 2-15
16 Truth Table The most basic representation of a logic function. Brute force representation listing the output for all possible input combinations. CMPE12 Winter 2008 J. Ferguson 2-16
17 Truth table Example Inputs A B Outputs X Y 2 #inputs CMPE12 Winter 2008 J. Ferguson 2-17
18 Static CMOS gate rules All potential paths to Vcc (1) must go up through pmos transistors. All potential paths to Gnd (0) must go down through nmos transistors. Implication: all 1s on inputs must put 0 on output and all 0s on inputs must put 1 on output. CMPE12 Winter 2008 J. Ferguson 2-18
19 NAND gate (NOT-AND) Note: Parallel structure on top, serial on bottom. A B C CMPE12 Winter 2008 J. Ferguson 2-19
20 AND gate A B 0 C Add an inverter to a NAND. CMPE12 Winter 2008 J. Ferguson 2-20
21 NOR gate Note: Serial structure on top, parallel on bottom. A B CMPE12 Winter 2008 J. Ferguson C
22 OR gate A B 0 C Add an inverter to a NOR gate. CMPE12 Winter 2008 J. Ferguson 2-22
23 Basic logic gates CMPE12 Winter 2008 J. Ferguson 2-23
24 Axioms of Boolean algebra 0 * 0 = = 1 * 1 = = 0 * 1 = 1 * 0 = = = = = if x = 0 then x = if x = 1 then x = CMPE12 Winter 2008 J. Ferguson 2-24
25 Single-variable theorems x * 0 = x + 1 = x * 1 = x + 0 = x * x = x + x = x * x = x + x = (x ) = CMPE12 Winter 2008 J. Ferguson 2-25
26 Commutative: x* y = x + y = Associative x * (y * z) = x + (y + z) = Distributive x*(y + z ) = x + Y * z = Properties CMPE12 Winter 2008 J. Ferguson 2-26
27 More properties Absorption: x + x * Y = x * (x + y) = Combining: x * Y + x * y = (x + y) * (x + y ) = De Morgan s (x* y) = (x + y) = Other: x + x *y = x * (x + y) = CMPE12 Winter 2008 J. Ferguson 2-27
28 DeMorgan's Law (1/2) (A + B) = A B conversely (AB) = A + B A B A+B A A+B A B AB CMPE12 Winter 2008 J. Ferguson 2-28
29 DeMorgan's Law (2/2) (A + B) = A B conversely (AB) = A + B A B AB A AB A B A+B CMPE12 Winter 2008 J. Ferguson 2-29
30 DeMorgan's Law and SoP Turns AND/OR into NAND/NAND: CMPE12 Winter 2008 J. Ferguson 2-30
31 Product of Sums A second standard way of synthesizing simple circuits. Ex: A B Z CMPE12 Winter 2008 J. Ferguson 2-31
32 DeMorgan's Law and PoS Turns OR/AND into NOR/NOR: CMPE12 Winter 2008 J. Ferguson 2-32
33 DeMorgan's Law: SoP or PoS? Can also generate NOR/NOR circuits, But we prefer NAND/NAND ones. NANDs are faster CMPE12 Winter 2008 J. Ferguson 2-33
34 More than 2 inputs? AND/OR can take any number of inputs. AND = 1 if all inputs are 1. OR = 1 if any input is 1. Similar for NAND/NOR Can implement with multiple two-input gates, or with single CMOS circuit. NAND?? NOR?? CMPE12 Winter 2008 J. Ferguson 2-34
35 CMOS 3-input NAND CMPE12 Winter 2008 J. Ferguson 2-35
36 Example: Logic minimization A B C Y CMPE12 Winter 2008 J. Ferguson 2-36
37 Building functions from logic gates Combinational Logic Circuit output depends only on the current inputs stateless Sequential Logic Circuit output depends on the sequence of inputs (past and present) stores information (state) from past inputs CMPE12 Winter 2008 J. Ferguson 2-37
38 Diversion: Unsigned Integers Represent Positive Integers String of digits: A n-1, A n-2, A 1, A 0 Contribution of A X is A X * base X Values range from 0 to A n 1 Most common bases: 10, 2 CMPE12 Winter 2008 J. Ferguson 2-38
39 n inputs, 2 n outputs Decoder exactly one output is asserted for each possible input pattern 2-to-4 decoder CMPE12 Winter 2008 J. Ferguson 2-39
40 About the little circle It is a logical idea stating that instead of the 1 being true, a 0 is true. When in Boolean logic it can be thought of as an inverter CMPE12 Winter 2008 J. Ferguson 2-40
41 Decoder block A 1 A 0 Sel CMPE12 Winter 2008 J. Ferguson 2-41
42 Abstraction: Decoder Lowest Level (for us): CMOS transistors Highest Level: 2 n Truth Tables or Diagram of previous slide Intermediate Level: Actual Gates making up the decoder CMPE12 Winter 2008 J. Ferguson 2-42
43 Multiplexer 2-way multiplexer: the output is equal to one of the two inputs, based on a selector S A B Z CMPE12 Winter 2008 J. Ferguson 2-43
44 4-way multiplexer n-bit selector and 2 n inputs, one output output equals one of the inputs, depending on selector 4-to-1 MUX CMPE12 Winter 2008 J. Ferguson 2-44
45 Binary addition = = = =... CMPE12 Winter 2008 J. Ferguson 2-45
46 Full Adder Add two bits and carry-in, produce one-bit sum and carry-out. A B 0 0 C in 0 S C out CMPE12 Winter 2008 J. Ferguson 2-46
47 Four-bit Adder CMPE12 Winter 2008 J. Ferguson 2-47
48 Logical completeness Can implement ANY truth table with AND, OR, NOT. A B C D AND combinations that yield a "1" in the truth table. 2. OR the results of the AND gates CMPE12 Winter 2008 J. Ferguson 2-48
49 Recommended exercises on combinational circuits Ex 3.5, 3.6, 3.7, 3.8, 3.9 Ex 3.12, 3.13, 3.14, 3.18 Ex 3.20, 3.22, 3.23, 3.24 with TA/Tut Ex 3.30, 3.31, 3.35 Ex 3.44 CMPE12 Winter 2008 J. Ferguson 2-49
50 Combinational vs. sequential Combinational circuit always gives the same output for a given set of inputs ex: adder always generates sum and carry, regardless of previous inputs CMPE12 Winter 2008 J. Ferguson 2-50
51 Sequential circuit stores information output depends on stored information (state) plus input so a given input might produce different outputs, depending on the stored information example: ticket counter advances when you push the button output depends on previous state useful for building memory elements and state machines CMPE12 Winter 2008 J. Ferguson 2-51
52 An R-S Latch Static Sequential circuits require feedback to hold state. S means set to 1 R means reset to 0 CMPE12 Winter 2008 J. Ferguson 2-52
53 An R-S Latch The input S,R = 0,0 is considered illegal or undefined. S-R latch CMPE12 Winter 2008 J. Ferguson 2-53
54 R-S Latch Summary R = S = 1 hold current value in latch S = 0, R=1 set value to 1 R = 0, S = 1 set value to 0 R = S = 0 both outputs equal one final state determined which input is 0 last, so 00->11 transition is illegal. CMPE12 Winter 2008 J. Ferguson 2-54
55 Not all feedback circuits form latches CMPE12 Winter 2008 J. Ferguson 2-55
56 D-Latch Two inputs: D (data) and WE (write enable) when WE = 1, latch is set to value of D S = NOT(D), R = D when WE = 0, latch holds previous value S = R = 1 the inverter and gate R-S Latch CMPE12 Winter 2008 J. Ferguson 2-56
57 Register A register stores a multi-bit value. We use a collection of D-latches, all controlled by a common WE. When WE=1, n-bit value D is written to register. CMPE12 Winter 2008 J. Ferguson 2-57
58 Memory Now that we know how to store bits, we can build a memory a logical k m array of stored bits. Address Space: number of locations (usually a power of 2) Addressability: number of bits per location (e.g., byte-addressable) k = 2 n locations m bits CMPE12 Winter 2008 J. Ferguson 2-58
59 2 2 x 3 Memory address word select word WE input bits write enable address decoder output bits CMPE12 Winter 2008 J. Ferguson 2-59
60 More about Memory This is a not the way actual memory is implemented. fewer transistors, much more dense, relies on electrical properties But the logical structure is very similar. address decoder word select line word write enable Many kinds of RAM (Random Access Memory) CMPE12 Winter 2008 J. Ferguson 2-60
61 State Machine The basic type of sequential circuit Combines combinational logic with storage Remembers state, and changes output (and state) based on inputs and current state State Machine Inputs Combinational Logic Circuit Outputs Storage Elements CMPE12 Winter 2008 J. Ferguson 2-61
62 Combinational vs. Sequential Two types of combination locks Combinational Success depends only on the values, not the order in which they are set. Sequential Success depends on the sequence of values (e.g, R-13, L-22, R-3). CMPE12 Winter 2008 J. Ferguson 2-62
63 State The state of a system is a snapshot of all the relevant elements of the system at the moment the snapshot is taken. Examples: The state of a basketball game can be represented by the scoreboard. Number of points, time remaining, possession, etc. The state of a tic-tac-toe game can be represented by the placement of X s and O s on the board. CMPE12 Winter 2008 J. Ferguson 2-63
64 State of Sequential Lock Our lock example has four different states, labelled A-D: A: The lock is not open, and no relevant operations have been performed. B: The lock is not open, and the user has completed the R-13 operation. C: The lock is not open, and the user has completed R-13, followed by L-22. D:The lock is open. CMPE12 Winter 2008 J. Ferguson 2-64
65 State Diagram Shows states and actions that cause a transition between states. CMPE12 Winter 2008 J. Ferguson 2-65
66 Finite State Machine A description of a system with the following components: 1. A finite number of states 2. A finite number of external inputs 3. A finite number of external outputs 4. An explicit specification of all state transitions 5. An explicit specification of what determines each external output value Often described by a state diagram. Inputs trigger state transitions. Outputs are associated with each state (or with each transition). CMPE12 Winter 2008 J. Ferguson 2-66
67 The Clock Frequently, a clock circuit triggers transition from one state to the next. 1 0 One Cycle time At the beginning of each clock cycle, state machine makes a transition, based on the current state and the external inputs. Not always required. In lock example, the input itself triggers a transition. CMPE12 Winter 2008 J. Ferguson 2-67
68 Implementing a Finite State Machine Combinational logic Determine outputs and next state. Storage elements Maintain state representation. State Machine Inputs Combinational Logic Circuit Outputs Clock Storage Elements CMPE12 Winter 2008 J. Ferguson 2-68
69 Example of sequential machine A 2-bit counter that counts the number of times that an input is logic 1. When the counter gets to 3, it signals that it is full. State table: how many states? CMPE12 Winter 2008 J. Ferguson 2-69
70 Representing Multi-bit Values Number bits from right (0) to left (n-1) just a convention -- could be left to right, but must be consistent Use brackets to denote range: D[l:r] denotes bit l to bit r, from left to right 15 A = A[14:9] = A[2:0] = 101 May also see A<14:9>, especially in hardware block diagrams. CMPE12 Winter 2008 J. Ferguson 2-70
71 An LC-3 architecture s sneak preview CMPE12 Winter 2008 J. Ferguson 2-71
72 LC-3 Data Path Combinational Logic Storage State Machine CMPE12 Winter 2008 J. Ferguson 2-72
73 Recommended exercises on Sequential Circuits Ex 3.21, 3.34, 3.35 Ex 3.40, 3.41, 3.43 CMPE12 Winter 2008 J. Ferguson 2-73
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