CPE100: Digital Logic Design I

Transcription

1 Chapter 3 Professor Brendan Morris, SEB 3216, brendan.morris@unlv.edu CPE1: Digital Logic Design I Section 14: Dr. Morris Sequential Logic Design Chapter 3 <1>

2 Chapter 3 :: Topics Introduction Latches and Flip-Flops Synchronous Logic Design Finite State Machines Timing of Sequential Logic Parallelism Chapter 3 <2>

3 Introduction Previously, Combinational Logic design had outputs only depend on current value of inputs Outputs of sequential logic depend on current and prior input values it has memory. Some definitions: State: all the information about a circuit necessary to explain its future behavior Latches and flip-flops: state elements that store one bit of state Synchronous sequential circuits: combinational logic followed by a bank of flip-flops Chapter 3 <3>

4 Sequential Circuits Give sequence to events (i.e. a notion of time) Have memory (short-term) Use feedback from output to input to store information Need to remember past output Chapter 3 <4>

5 State Elements The state of a circuit influences its future behavior State elements store state Bistable circuit SR Latch D Latch D Flip-flop Chapter 3 <5>

6 Bistable Circuit Fundamental building block of other state elements Two outputs:, (state) No inputs 1 I2 I1 1 1 I1 I2 Chapter 3 <6> Redrawn circuit to emphasize symmetry

7 Bistable Circuit Analysis Consider the two possible cases: = : then = 1, = (consistent) 1 I1 I2 1 Chapter 3 <7>

8 Bistable Circuit Analysis Consider the two possible cases: = : then = 1, = (consistent) 1 I1 I2 1 = 1: then =, = 1 (consistent) I1 1 1 I2 Stores 1 bit of state in the state variable, (or ) But there are no inputs to control the state Chapter 3 <8>

9 SR (Set/Reset) Latch SR Latch S set =1 R N1 R reset = S N2 Chapter 3 <9>

10 SR (Set/Reset) Latch SR Latch R N1 S N2 Consider the four possible cases: S = 1, R = S =, R = 1 S =, R = S = 1, R = 1 Chapter 3 <1>

11 SR Latch Analysis S = 1, R = : then = 1 and = R N1 1 S 1 N2 Chapter 3 <11>

12 SR Latch Analysis S = 1, R = : then = 1 and = R N1 1 S 1 N2 Chapter 3 <12>

13 SR Latch Analysis S = 1, R = : then = 1 and = R N1 1 S 1 N2 S =, R = 1: then = and = 1 R 1 1 N1 S N2 1 Chapter 3 <13>

14 SR Latch Analysis S = 1, R = : then = 1 and = Set the output R S 1 N1 N2 1 S =, R = 1: then = and = 1 Reset the output R S 1 1 N1 N2 1 Chapter 3 <14>

15 SR Latch Analysis S =, R = : prev = prev = 1 then = prev R N1 R N1 1 S N2 S N2 Chapter 3 <15>

16 SR Latch Analysis S =, R = : prev = prev = 1 then = prev R N1 R N1 1 S N2 S N2 Chapter 3 <16>

17 SR Latch Analysis S =, R = : prev = prev = 1 then = prev R N1 R N1 1 S N2 S N2 S = 1, R = 1: then =, = R S 1 1 N1 N2 Chapter 3 <17>

18 SR Latch Analysis S =, R = : prev = prev = 1 then = prev R N1 R N1 1 S N2 S N2 S = 1, R = 1: then =, = R S 1 1 N1 N2 Chapter 3 <18>

19 SR Latch Analysis S =, R = : prev = prev = 1 then = prev Memory! R N1 R N1 S N2 S N2 S = 1, R = 1: then =, = Invalid State NOT R S 1 1 N1 N2 Chapter 3 <19>

20 SR Latch Symbol SR stands for Set/Reset Latch Stores one bit of state () Control what value is being stored with S, R inputs Set: Make the output 1 (S = 1, R =, = 1) Reset: Make the output (S =, R = 1, = ) SR Latch Symbol R S Chapter 3 <2>

21 D Latch Two inputs:, D : controls when the output changes D (the data input): controls what the output changes to Function When = 1, D passes through to (transparent) When =, holds its previous value (opaque) Avoids invalid case when NOT Chapter 3 <21> D Latch Symbol D

22 D Latch Internal Circuit D R R D S S D D X D S R Chapter 3 <22>

23 D Latch Internal Circuit D R R D S S D D X D X 1 S R prev prev Chapter 3 <23>

24 D Flip-Flop Inputs:, D Function Samples D on rising edge of When rises from to 1, D passes through to Otherwise, holds its previous value changes only on rising edge of Called edge-triggered Activated on the clock edge D D Flip-Flop Symbols Chapter 3 <24>

25 D Flip-Flop Internal Circuit Two back-to-back latches (L1 and L2) controlled by complementary clocks When = L1 is transparent L2 is opaque D passes through to N1 D D L1 N1 D L2 Chapter 3 <25>

26 D Flip-Flop Internal Circuit Two back-to-back latches (L1 and L2) controlled by complementary clocks When = L1 is transparent L2 is opaque D passes through to N1 When = 1 L2 is transparent L1 is opaque N1 passes through to D D L1 N1 D L2 Chapter 3 <26>

27 D Flip-Flop Internal Circuit Two back-to-back latches (L1 and L2) controlled by complementary clocks When = L1 is transparent L2 is opaque D passes through to N1 When = 1 L2 is transparent L1 is opaque N1 passes through to D D L1 N1 D L2 Thus, on the edge of the clock (when rises from 1) D passes through to Chapter 3 <27>

28 D Latch vs. D Flip-Flop D D D (latch) (flop) Chapter 3 <28>

29 D Latch vs. D Flip-Flop D D D (latch) (flop) Chapter 3 <29>

30 Review SR Latch Symbol SR Latch D Latch D Flip-flop R D D S S = 1, R = : = 1 S =, R= 1: = = 1: = D = : = prev = 1: = D Otherwise: = prev Chapter 3 <3>

31 Registers D D D 1 D 1 D 3: 4 4 3: D 2 D 2 D 3 D 3 Chapter 3 <31>

32 Enabled Flip-Flops Inputs:, D, EN The enable input (EN) controls when new data (D) is stored Function EN = 1: D passes through to on the clock edge EN = : the flip-flop retains its previous state EN Internal Circuit Symbol D 1 D D EN Chapter 3 <32>

33 Enabled Flip-Flops Inputs:, D, EN The enable input (EN) controls when new data (D) is stored Function EN = 1: D passes through to on the clock edge EN = : the flip-flop retains its previous state EN Internal Circuit Symbol D 1 D D EN Chapter 3 <33>

34 Resettable Flip-Flops Inputs:, D, Reset Function: Reset = 1: is forced to Reset = : flip-flop behaves as ordinary D flip-flop Symbols D Reset r Chapter 3 <34>

35 Resettable Flip-Flops Two types: Synchronous: resets at the clock edge only Asynchronous: resets immediately when Reset = 1 Asynchronously resettable flip-flop requires changing the internal circuitry of the flip-flop Synchronously resettable flip-flop? Chapter 3 <35>

36 Resettable Flip-Flops Two types: Synchronous: resets at the clock edge only Asynchronous: resets immediately when Reset = 1 Asynchronously resettable flip-flop requires changing the internal circuitry of the flip-flop Synchronously resettable flip-flop? Internal Circuit D Reset D Chapter 3 <36>

37 Settable Flip-Flops Inputs:, D, Set Function: Set = 1: is set to 1 Set = : the flip-flop behaves as ordinary D flipflop Symbols D Set s Chapter 3 <37>

38 Synchronous Sequential Logic Design Registers inserted between combinational logic Registers contain state of the system State changes at clock edge: system synchronized to the clock Chapter 3 <38>

39 Synchronous Sequential Logic Design Rules of synchronous sequential circuit composition: Every circuit element is either a register or a combinational circuit At least one circuit element is a register All registers receive the same clock signal Every cyclic path contains at least one register Chapter 3 <39>

40 Synchronous Sequential Logic Design Rules of synchronous sequential circuit composition: Every circuit element is either a register or a combinational circuit At least one circuit element is a register All registers receive the same clock signal Every cyclic path contains at least one register Two common synchronous sequential circuits Finite State Machines (FSMs) Pipelines Chapter 3 <4>

41 Finite State Machine (FSM) Consists of: State register Stores current state Loads next state at clock edge Combinational logic Computes the next state Computes the outputs S S Next State Current State Next State Logic Output Logic C L Next State C L Outputs Chapter 3 <41>

42 Finite State Machines (FSMs) Next state determined by current state and inputs Two types of finite state machines differ in output logic: Moore FSM: outputs depend only on current state Mealy FSM: outputs depend on current state and inputs Moore FSM inputs M next state logic k next state k state output logic N outputs Mealy FSM inputs M next state logic k next state k state output logic N outputs Chapter 3 <42>

43 FSM Design Procedure 1. Identify inputs and outputs 2. Sketch state transition diagram 3. Write state transition table 4. Select state encodings 5. Rewrite state transition table with state encodings 6. Write output table 7. Write Boolean equations for next state and output logic 8. Sketch the circuit schematic Chapter 3 <43>

44 Bravado Blvd. FSM Example Traffic light controller Traffic sensors: T A, T B (TRUE when there s traffic) Lights: L A, L B Dining Hall L B L A T B L A Academic T A T A Ave. Labs T B L B Dorms Fields Chapter 3 <44>

45 FSM Design Procedure 1. Identify inputs and outputs 2. Sketch state transition diagram 3. Write state transition table 4. Select state encodings 5. Rewrite state transition table with state encodings 6. Write output table 7. Write Boolean equations for next state and output logic 8. Sketch the circuit schematic Chapter 3 <45>

46 FSM Black Box Inputs:, Reset, T A, T B Outputs: L A, L B Note: multiple bits for output T A T B Traffic Light Controller L A L B Reset Chapter 3 <46>

47 FSM Design Procedure 1. Identify inputs and outputs 2. Sketch state transition diagram 3. Write state transition table 4. Select state encodings 5. Rewrite state transition table with state encodings 6. Write output table 7. Write Boolean equations for next state and output logic 8. Sketch the circuit schematic Chapter 3 <47>

48 Bravado Blvd. FSM State Transition Diagram Moore FSM: outputs labeled in each state States: Circles Transitions: Arcs Dining Hall Reset S L A : green L B : red L B L A T B L A Academic T A T A Ave. Labs T B L B Dorms Fields Chapter 3 <48>

49 Bravado Blvd. FSM State Transition Diagram Moore FSM: outputs labeled in each state States: Circles Transitions: Arcs Dining Hall Reset S L A : green L B : red T A TA S1 L A : yellow L B : red L B L A T B L A Academic Labs T A T B T A L B Ave. Dorms S3 L A : red L B : yellow S2 L A : red L B : green Fields T B T B Chapter 3 <49>

50 FSM Design Procedure 1. Identify inputs and outputs 2. Sketch state transition diagram 3. Write state transition table 4. Select state encodings 5. Rewrite state transition table with state encodings 6. Write output table 7. Write Boolean equations for next state and output logic 8. Sketch the circuit schematic Chapter 3 <5>

51 FSM State Transition Table Reset T A TA Current State Inputs Next State S T A T B S' S L A : green L B : red S3 L A : red L B : yellow T B T B S1 L A : yellow L B : red S2 L A : red L B : green S X S 1 X S1 X X S2 X S2 X 1 S3 X X Chapter 3 <51>

52 FSM State Transition Table Reset T A TA Current State Inputs Next State S T A T B S' S L A : green L B : red S3 L A : red L B : yellow T B T B S1 L A : yellow L B : red S2 L A : red L B : green S X S1 S 1 X S S1 X X S2 S2 X S3 S2 X 1 S2 S3 X X S Chapter 3 <52>

53 FSM Design Procedure 1. Identify inputs and outputs 2. Sketch state transition diagram 3. Write state transition table 4. Select state encodings 5. Rewrite state transition table with state encodings 6. Write output table 7. Write Boolean equations for next state and output logic 8. Sketch the circuit schematic Chapter 3 <53>

54 FSM Encoded State Transition Table Current State Inputs Next State S 1 S T A T B S' 1 S' X 1 X 1 X X 1 X 1 X X X State Encoding S S1 1 S2 1 S3 11 Two bits required for 4 states Reset S L A : green L B : red T A TA S1 L A : yellow L B : red Chapter 3 <54> S3 L A : red L B : yellow T B T B S2 L A : red L B : green

55 FSM Encoded State Transition Table Current State Inputs Next State S 1 S T A T B S' 1 S' X 1 1 X 1 X X 1 1 X X X X State Encoding S S1 1 S2 1 S3 11 Two bits required for 4 states S' 1 = S 1 S Reset S L A : green L B : red T A TA S1 L A : yellow L B : red S' = S 1 S T A + S 1 S T B Chapter 3 <55> S3 L A : red L B : yellow T B T B S2 L A : red L B : green

56 FSM Design Procedure 1. Identify inputs and outputs 2. Sketch state transition diagram 3. Write state transition table 4. Select state encodings 5. Rewrite state transition table with state encodings 6. Write output table 7. Write Boolean equations for next state and output logic 8. Sketch the circuit schematic Chapter 3 <56>

57 FSM Output Table Current State Outputs S 1 S L A1 L A L B1 L B Output Encoding green yellow 1 red 1 Two bits required for 3 outputs Reset S L A : green L B : red T A TA S1 L A : yellow L B : red Chapter 3 <57> S3 L A : red L B : yellow T B T B S2 L A : red L B : green

58 FSM Output Table Current State Outputs S 1 S L A1 L A L B1 L B Output Encoding green yellow 1 red 1 Two bits required for 3 outputs L A1 = S 1 L A = S 1 S L B1 = S 1 Reset S L A : green L B : red T A TA S1 L A : yellow L B : red L B = S 1 S Chapter 3 <58> S3 L A : red L B : yellow T B T B S2 L A : red L B : green

59 FSM Design Procedure 1. Identify inputs and outputs 2. Sketch state transition diagram 3. Write state transition table 4. Select state encodings 5. Rewrite state transition table with state encodings 6. Write output table 7. Write Boolean equations for next state and output logic 8. Sketch the circuit schematic Chapter 3 <59>

60 FSM Schematic: State Register S' 1 S 1 S' r Reset S state register S' 1 = S 1 S L A1 = S 1 L B1 = S 1 S' = S 1 S T A + S 1 S T B L A = S 1 S L B = S 1 S Chapter 3 <6>

61 FSM Schematic: Next State Logic S' 1 S 1 T A T B S' r Reset S S 1 S inputs next state logic state register S' 1 = S 1 S S' = S 1 S T A + S 1 S T B Chapter 3 <61>

62 FSM Schematic: Output Logic L A1 S' 1 S 1 L A T A S' r S L B1 T B Reset S 1 S L B inputs next state logic state register output logic outputs L A1 = S 1 L B1 = S 1 L A = S 1 S L B = S 1 S Chapter 3 <62>

63 FSM Timing Diagram Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 Cycle 8 Cycle 9 Cycle 1 Reset T A T B S' 1:?? S () S1 (1) S2 (1) S3 (11) S () S1 (1) S 1:?? S () S1 (1) S2 (1) S3 (11) S () L A1:?? Green () Yellow (1) Red (1) Green () L B1:?? Red (1) Green () Yellow (1) Red (1) t (sec) Reset S L A : green L B : red T A TA S1 L A : yellow L B : red S3 L A : red L B : yellow T B T B S2 L A : red L B : green Chapter 3 <63>

64 FSM State Encoding Binary encoding: i.e., for four states,, 1, 1, 11 One-hot encoding One state bit per state Only one state bit HIGH at once i.e., for 4 states, 1, 1, 1, 1 Requires more flip-flops Often next state and output logic is simpler Chapter 3 <64>

65 FSM Design Procedure 1. Identify inputs and outputs 2. Sketch state transition diagram 3. Write state transition table 4. Select state encodings 5. Rewrite state transition table with state encodings 6. Write output table 7. Write Boolean equations for next state and output logic 8. Sketch the circuit schematic Chapter 3 <65>

66 FSM Problems 1. Design a circuit to detect 3 or more 1 s in a row in a bit stream 2. Vending machine: Release an item after receiving 15 cents Single coin slot but tells if you put in dime or nickel No change given 1. Identify inputs and outputs 2. Sketch state transition diagram 3. Write state transition table 4. Select state encodings 5. Rewrite state transition table with state encodings 6. Write output table 7. Write Boolean equations for next state and output logic 8. Sketch the circuit schematic Chapter 3 <66>

67 Timing Flip-flop samples D at clock edge D must be stable when sampled Similar to a photograph, D must be stable around clock edge Moving right before or after shutter click results in blurry photo If not, metastability can occur Chapter 3 <67>

68 Input Timing Constraints Setup time: t setup = time before clock edge data must be stable (i.e. not changing) Hold time: t hold = time after clock edge data must be stable Aperture time: t a = time around clock edge data must be stable (t a = t setup + t hold ) D t setup t hold t a Chapter 3 <68>

69 Output Timing Constraints Propagation delay: t pcq = time after clock edge that the output is guaranteed to be stable (i.e., to stop changing) Contamination delay: t ccq = time after clock edge that might be unstable (i.e., start changing) t ccq t pcq Chapter 3 <69>

70 Dynamic Discipline Synchronous sequential circuit inputs must be stable during aperture (setup and hold) time around clock edge Specifically, inputs must be stable: at least t setup before the clock edge at least until t hold after the clock edge Previously, static discipline: With logically valid inputs, every circuit element must produce logically valid outputs Chapter 3 <7>

71 Dynamic Discipline The delay between registers has a minimum and maximum delay, dependent on the delays of the circuit elements 1 C L D2 (a) R1 R2 T c 1 D2 (b) Chapter 3 <71>

72 Setup Time Constraint Depends on the maximum delay from register R1 through combinational logic to R2 The input to register R2 must be stable at least t setup before clock edge 1 C L D2 T c R1 R2 T c 1 D2 t pcq t pd t setup Chapter 3 <72>

73 Setup Time Constraint Depends on the maximum delay from register R1 through combinational logic to R2 The input to register R2 must be stable at least t setup before clock edge R1 1 C L T c D2 R2 T c t pcq + t pd + t setup t pd 1 D2 t pcq t pd t setup Chapter 3 <73>

74 Setup Time Constraint Depends on the maximum delay from register R1 through combinational logic to R2 The input to register R2 must be stable at least t setup before clock edge R1 1 C L T c D2 R2 T c t pcq + t pd + t setup t pd T c (t pcq + t setup ) 1 D2 (t pcq + t setup ): sequencing overhead t pcq t pd t setup Chapter 3 <74>

75 Hold Time Constraint Depends on the minimum delay from register R1 through the combinational logic to R2 The input to register R2 must be stable for at least t hold after the clock edge R1 1 C L D2 R2 t hold < 1 D2 t ccq t cd t hold Chapter 3 <75>

76 Hold Time Constraint Depends on the minimum delay from register R1 through the combinational logic to R2 The input to register R2 must be stable for at least t hold after the clock edge R1 1 D2 1 C L D2 R2 t hold < t ccq + t cd t cd > t ccq t cd t hold Chapter 3 <76>

77 Hold Time Constraint Depends on the minimum delay from register R1 through the combinational logic to R2 The input to register R2 must be stable for at least t hold after the clock edge 1 D2 R1 1 C L D2 R2 t hold < t ccq + t cd t cd > t hold - t ccq t ccq t cd t hold Chapter 3 <77>

78 Timing Analysis A B C X' X Timing Characteristics t ccq t pcq = 3 ps = 5 ps t setup = 6 ps t hold = 7 ps D t pd = t cd = Setup time constraint: T c f c = Y' Y per gate t pd t cd Hold time constraint: t ccq + t cd > t hold? = 35 ps = 25 ps Chapter 3 <78>

79 Timing Analysis A B C X' X Timing Characteristics t ccq t pcq = 3 ps = 5 ps t setup = 6 ps t hold = 7 ps D t pd = 3 x 35 ps = 15 ps t cd = 25 ps Setup time constraint: T c ( ) ps = 215 ps f c = 1/T c = 4.65 GHz Y' Y per gate t pd t cd = 35 ps = 25 ps Hold time constraint: t ccq + t cd > t hold? (3 + 25) ps > 7 ps? No! Chapter 3 <79>

80 Timing Analysis Add buffers to the short paths: A B C X' X Timing Characteristics t ccq t pcq = 3 ps = 5 ps t setup = 6 ps t hold = 7 ps D t pd = Y' Y per gate t pd t cd = 35 ps = 25 ps t cd = Setup time constraint: Hold time constraint: T c t ccq + t cd > t hold? f c = Chapter 3 <8>

81 Timing Analysis Add buffers to the short paths: A B C X' X Timing Characteristics t ccq t pcq = 3 ps = 5 ps t setup = 6 ps t hold = 7 ps D t pd = 3 x 35 ps = 15 ps Y' Y per gate t pd t cd = 35 ps = 25 ps t cd = 2 x 25 ps = 5 ps Setup time constraint: Hold time constraint: T c ( ) ps = 215 ps t ccq + t cd > t hold? f c = 1/T c = 4.65 GHz (3 + 5) ps > 7 ps? Yes! Chapter 3 <81>

82 Parallelism Two types of parallelism: Spatial parallelism duplicate hardware performs multiple tasks at once Temporal parallelism task is broken into multiple stages also called pipelining for example, an assembly line Chapter 3 <82>

83 Parallelism Definitions Token: Group of inputs processed to produce group of outputs Latency: Time for one token to pass from start to end Throughput: Number of tokens produced per unit time Parallelism increases throughput Chapter 3 <83>

84 Parallelism Example Ben Bitdiddle bakes cookies to celebrate traffic light controller installation 5 minutes to roll cookies 15 minutes to bake What is the latency and throughput without parallelism? Chapter 3 <84>

85 Parallelism Example Ben Bitdiddle bakes cookies to celebrate traffic light controller installation 5 minutes to roll cookies 15 minutes to bake What is the latency and throughput without parallelism? Latency = = 2 minutes = 1/3 hour Throughput = 1 tray/ 1/3 hour = 3 trays/hour Chapter 3 <85>

86 Parallelism Example What is the latency and throughput if Ben uses parallelism? Spatial parallelism: Ben asks Allysa P. Hacker to help, using her own oven Temporal parallelism: two stages: rolling and baking He uses two trays While first batch is baking, he rolls the second batch, etc. Chapter 3 <86>

87 Spatial Parallelism Latency: time to first tray Spatial Parallelism Tray 1 Tray 2 Tray 3 Tray 4 Ben 1 Ben 1 Alyssa 1 Alyssa 1 Ben 2 Ben 2 Alyssa 2 Alyssa 2 Roll Bake Legend Time Latency =? Throughput =? Chapter 3 <87>

88 Spatial Parallelism Latency: time to first tray Spatial Parallelism Tray 1 Tray 2 Tray 3 Tray 4 Ben 1 Ben 1 Alyssa 1 Alyssa 1 Ben 2 Ben 2 Alyssa 2 Alyssa 2 Roll Bake Legend Time Latency = = 2 minutes = 1/3 hour Throughput = 2 trays/ 1/3 hour = 6 trays/hour Chapter 3 <88>

89 Temporal Parallelism Latency: time to first tray Temporal Parallelism Tray 1 Tray 2 Tray 3 Ben 1 Ben 1 Ben 2 Ben 2 Ben 3 Ben 3 Time Latency =? Throughput =? Chapter 3 <89>

90 Temporal Parallelism Latency: time to first tray Temporal Parallelism Tray 1 Tray 2 Tray 3 Ben 1 Ben 1 Ben 2 Ben 2 Ben 3 Ben 3 Time Latency = = 2 minutes = 1/3 hour Throughput = 1 trays/ 1/4 hour = 4 trays/hour Using both spatial and temporal techniques, the throughput would be 8 trays/hour Chapter 3 <9>