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1 UNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences Last modified on April 14, 2004 by Brian Leibowitz Jan Rabaey Homework #8 EECS141 Due Thursday, April 22, Cory Problem 1 Activity Factor Consider the decimal counter shown below. The static logic block is a 4-bit binary incrementor. Its input is a 4-bit binary number IN<3:0>, where IN<3> represents the most significant bit of the input number. Its output is a 4-bit binary number OUT<3:0> that has a numeric value 1 greater than, unless the input is 9, in which case the output is 0. I.e., if the input is 5 (0101), the output will be 6 (0110). If the input is 9 (1001), the output is (0000). X<0:3> Incrementor OUT<0:3> IN<0:3> Y<0:3> 4 Register D<0:3> Q<0:3> 4 CLK a) What are p 0 and p 1, the probabilities of a 0 and of a 1, for each of the four bits X<0> through X<3>? Soln: X<0>: p 1 = Prob(X = 1, 3, 5, 7, or 9) = 0.5 (5 out of 10 cases), p 0 = 0.5 X<1>: p 1 = Prob(X = 2, 3, 6, or 7) = 0.4, p 0 = 0.6 X<2>: p 1 = Prob(X = 4, 5, 6, or 7) = 0.4, p 0 = 0.6 X<3>: p 1 = Prob(X = 8 or 9) = 0.2, p 0 = 0.8 b) What are the activity factors α 0 through α 3 for each of the four bits X<0> through X<3>? Soln: Cannot use p 0 p 1 here because successive logic values are correlated with each other. Note that X follows the repeating pattern 0, 1, 2,, 9, 0, 1, and look at the soln s to the previous part to count how many transisitions there are for each bit in one cycle. X<0>: 0 1 occurs every other cycle, α 0 = 0.5 X<1>: 0 1 occurs when X changes from 2-3, and from 5-6, or 2 times every 10 cycles, α 1 = 0.2 X<2>: 0 1 occurs when X changes from 3-4, or once every 10 cycles, α 2 = 0.1

2 X<3>: 0 1 occurs when X changes from 7-8, or once every 10 cycles, α 3 = 0.1 c) If the capacitance at each node for X is 5 ff, the capacitance at each node for Y is 4 ff, and the circuit is clocked at 250 MHz, what is the dynamic power consumption of this circuit? Ignore all other capacitances, assume there is no glitching, and V DD = 2.5 V. Soln: Note that X and Y nodes go through all of the same transitions, so just count their capacitances together. P = f ΣCV DD 2 α i = 250 MHz 9 ff 6.25 V 2 ( ) = 12.7 µw d) In addition to the incrementor logic, you wish to add logic that detects when X<3:0> has a value 7. Recognizing that X<3:0> is never 15, this can be accomplished with a 3-input AND of bits <0> through <2>. If this is to be accomplished with only 2-input AND gates, which of the two choices below is preferable? Why? X<0> X<1> X<1> X<2> Design A X<2> X<0> Design B Soln: Design B is better because it consumes less dynamic power. Note that the intermediate node in A is 1 when X = 3 or 7, and thus has an activity factor of 0.2 (2 0 1 transistions every 10 cycles). The intermediate node in B is 1 when X = 6 or 7, thus only has an activity factor of 0.1, leading to less dynamic power consumption. All other nodes have the same activity factors in both designs (assuming no glitching).

3 Problem 2 Flip Flops After pulling an all nighter before a 10 am design review, you finish designing the flip-flop shown below. The key feature is that by using tri-state inverters, you can avoid using pass transistor switches. Tri-state inverters labeled 1-4 in the diagram act as normal inverters when their control input is high, but their outputs are high impedance (or open circuit, often referred to as logic Z ) when their control input is low. A! in a signal name indicates logical compliment, or negative logic. 3 4 D 1 clk clk! Q clk! 2 clk Q! a) What type of memory is this (latch or register)? Soln: The master/slave design makes this a register. Note that there is no value of clk for which the circuit is transparent, so it is not a latch. b) Your lazy coworker gets into the office at 9:45 am, just before your design review, and while strolling by your desk comments cute circuit, but it has a race condition problem. What is the problem he is referring to? Soln: On the rising clock edge, the value of D is supposed to be stored by inverters 2 and 3. However, if all clocks change at the same time, inverter 2 input is initially D!, and inverter 3 input is initially Q, and there is a race between the two inverters to determine which value will get latched by the bi-stable pair. We would like inverter 2 to win this race to make sure that the value of D is properly latched. c) At 9:55, with just five minutes left, you decide that you can alleviate the race condition by adding the inverter chain shown below to create several clock signals with edges that occur in a well defined sequence. Which clock signal would you use for each of the four tri-state inverters? clk! clk clkd! clkd Soln: Since we want inverter 2 to have a head start relative to inverter 3, we use clk for the control on inverter 2, and clkd for the control on inverter 3. Inverter 4 should be controlled by clk! to make sure it is off before inverter 2 turns on, but it could also work with clkd! Inverter 1 can be controlled by clk! or clkd! since inverter 3 won t be turned on until clkd, which is later than both of these.

4 Inverter Control Signal 1 clk! or clkd! 2 clk 3 clkd 4 clk! or clkd! d) At the end of the review your boss is pleased with the design, but apologizes for not telling you at the beginning that you must also provide an asynchronous clear input. When the asynchronous clear input (CLR) is raised, the output should be set to 0 regardless of the clock signals, and should remain at 0 after the clear signal is removed (until the next time at 1 is stored). After this stressful morning, you head for an early lunch and then decide to take a nap to help you relax. Just as you are about to doze off, you realize that you can add the asynchronous clear function by adding a single transistor to the existing schematic. Show how this is done, and describe any sizing constraints on this transistor (no calculations just explain it). Soln: 3 4 D 1 clkd clkd! Q clk! 2 Q! clk CLR Whether clk is high or low, raising the CLR input will change the stored state to 0. This will be done by flipping the left cross coupled inverter pair if clk is high, or by flipping the right pair if clk is low. This clear transistor must be strong enough to drive the internal node to 0 when either inverter 2 or inverter 4 is trying to hold it at a 1, so it must be stronger than the pull up networks of each of these tri-state inverters.

5 Problem 3 Timing and Clock Skew Consider the pipelined logic structure below, where signals advance from one latch to the next in each clock cycle. Assume latches L1 L3 are all on the same clock and are positive transparent. The latches have a propagation delay given by t latch = 0.3 ns when the clock is high. Combinational logic blocks A and B are static, and have logic delays that depend on their inputs. Minimum and maximum delays for each logic block are listed below. Block A: t pmin = 1.7 ns; t pmax = 2.1 ns Block B: t pmin = 1.2 ns; t pmax = 1.6 ns Block C: t pmin = 1.0 ns; t pmax = 1.2 ns (this is for all inputs) L1 A L2 B C L3 a) Determine t on,max, the maximum time that the clock pulse can be high (i.e. longest time the latches can be open for). Assume there is NO clock skew. Soln: If the clock is high for too long, data can flow from the L1 input through A and reach L2 in the same pulse. Similarly, it could from from the L2 input through B, C, to L3, or from the L3 input through C and to L3 again. All of these cases must be prevented. For the L1-L2 flow through hazard, we want to make sure that the ON pulse is short enough that the fastest possible path through A doesn t allow new data from L1 to reach L2 while it is still open. T ON < t latch,1 + t pmin,a = 0.3 ns ns = 2.0 ns For the other hazards we have T ON < t latch,2 + t pmin,b + t pmin,c = 0.3 ns ns ns = 2.5 ns T ON < t latch,3 + t pmin,c = 0.3 ns ns = 1.3 ns Thus, overall we require T ON < 1.3 ns. A more liberal solution is to add 0.3 ns to each result, and obtain a final answer of 1.6 ns, since it may be ok for data to reach the next latch as long as it doesn t have time to flow through. It is not clear which approach is more accurate without more information about the latch. b) Determine the minimum clock period t min and the worst case latency t pipeline from the input of L1 to the output of C. Assume NO clock skew. Soln: The minimum clock period is determined by the worst case (longest) delay through a latch and the following logic before the next latch.

6 T > t latch + t pmax,a = 0.3 ns ns = 2.4 ns T > t latch + t pmax,b + t pmax,c = 0.3 ns ns ns = 3.1 ns T > t latch + t pmax,c = 0.3 ns ns = 1.5 ns The minimum possible clock period is thus 3.1 ns. The worst case latency from the input of L1 to the output of C is equal to one clock period to get from the input of L1 to the input of L2, followed by the propagation delay of L2 and the worst case delay of B and C. Thus, tpipeline = 3.1 ns ns ns ns = 6.2 ns. c) Now assume that the clock is routed from latch 1 (L1) to latch 3 (L3) in ascending order. Assume that the clock skew between subsequent latches is the same (i.e. the skew from L1 to L2 is the same as the skew from L2 to L3). Find the MINIMUM clock skew needed to safely run the clock with a 2.5 ns period. Soln: The first pipeline stage can operate with a 2.5 ns clock without any skew. The problem is the second pipeline stage, which has a worst case delay from the L2 clock to the C output of 3.1 ns. If the clock period is 2.5 ns, then a 0.6 ns or greater skew is required to insure that there is a 3.1 ns window from the L2 clock edge to the L3 clock edge. d) What is the minimum clock period t min and worst case latency t pipeline from the input of L1 to the output of C if an additional latch is added between logic blocks B and C? Soln: This is just like part (b), but replace the L2-L3 timing constraint with two new constraints: T > t latch + t pmaxb = 0.3 ns ns = 1.9 ns T > t latch + t pmaxc = 0.3 ns ns = 1.5 ns Thus, the L1-L2 constraint from part (b) is now the limiting factor, so the minimum clock period is 2.4 ns. Now the worst case pipeline latency is now two clock periods to get from the input of L1 to the input of the new latch between B and C, plus the propagation delay of that latch and the worst case delay of C: t pipeline = 2*2.4 ns ns ns = 6.3 ns Note that the clock period got shorter, but the latency still got longer.

7 Bonus Problem Wave Pipelining It s another late night at the office, and you are struggling to meet throughput and latency requirements for the two stage pipelined logic path shown below. Your boss is insisting that the logic operate at 800 MHz so that you can beat the evil competitor s expected product at 666 MHz, and this is the last logic block that doesn t meet the timing specification. The registers have t hold = 0 ns, t c-q = 0.3 ns, and t su = 0.2 ns. The minimum and maximum logic delays for logic blocks A and B are given below. These blocks have multiple inputs and outputs, so these delays mean that starting from the time the last input is setup, some outputs may be available as soon as t pmin, and others may take as long as t pmax. This implies that the inputs to each block must be stable for at least t pmax to guarantee that a correct output is ever generated. Unfortunately, you are convinced that t pmax cannot be reduced for either logic block. Block A: t pmin = 1.0 ns, t pmax = 1.2 ns Block B: t pmin = 0.6 ns, t pmax = 0.7 ns R1 A R2 B R3 CLK Waiting for the second pot of coffee to finish brewing, you have a stroke of brilliance. You realize that the registers actually take up a lot of the timing budget. If you could get rid of the middle register, and operate the logic as shown below, you could save a little bit of time. In this case, the registers are clocked faster than the total delay through A and B, and there are two different groups of data flowing through the logic at any time. I.e., on one clock edge data is launched into logic block A. As that data flow progresses into logic block B, a new set of data is launched into block A. Two clocks after it is launched, the first set of data has reached the output of B and is latched, and the second set of data is progressing from A to B. This is referred to as wave pipelining, since multiple waves of data flow through a logic path without registers to separate them. R1 A B R3 CLK a) What is the minimum clock period you can achieve with this technique? Soln: See the logic timing diagram below (not perfectly to scale), where X, Y, and Z correspond to the three nodes between registers R1 and R3. Shaded areas represent times when signals are uncertain. At the first clock edge X0 is loaded by register R1, which then evaluates to Y0 after logic block A and to Z0 after logic block B. Z0 must be available at time t su before the third clock

8 edge where it will be latched by R3, and must remain valid until time t hold after the clock edge (in this case t hold = 0). The minimum clock period is determined by the latest time at which Z0 may become available. From the diagram, this constraint is seen to be 2T > t c-q + t pmaxa + t pmaxb + t su = 0.3 ns ns ns ns = 2.4 ns T > 1.2 ns, just fast enough to run at 800 MHz b) What is the maximum clock period that will operate correctly? Soln: Referring to the timing diagram again, we see that if the clock period is too long, Z0 might get replaced by Z1 before it is latched by R3. The earliest possible time that this can happen is determined by the shortest path through A and B (the shortest path for Y0 to be replaced by Y1, and then the shortest path for Z0 to be replaced by Z1). Thus, the maximum clock period is constrained by T < t c-q + t pmina + t pminb + t hold = 0.3 ns ns ns + 0 ns = 1.9 ns c) What is the MINIMUM value of t pmin for block A for this pipeline to operate correctly at 800 MHz? Soln: Referring to the timing diagram again, consider what happens if t pmina is reduced. The length of time when Y0 is valid is reduced because Y1 might arrive sooner after the second clock edge. Similarly, Z1 might also arrive sooner, and if it arrives within t hold of the third clock edge, Z0 won t be latched correctly. This is the same constraint as in part (b), but taken from the perspective of t pmina having a lower limit for a given T, instead of T having an upper limit for a given t pmina. t pmina > T - t c-q - t pminb - t hold = 1.2 ns 0.3 ns 0.6 ns 0 ns = 0.3 ns

9 However, there is another issue here as well. It was given that Y0 must be stable for at least t pmaxb in order for logic block B to ever evaluate to the correct output. In other words, Z0 must be produced before Y0 can be removed. This leads to another constraint that Y0 be stable for at least 0.7 ns: t c-q + t pmaxa ns < T + t c-q + t pmina or, t pmina > t pmaxa + t pmaxb T = 1.2 ns ns 1.2 ns = 0.7 ns This also shows a constraint that was not considered in part (a) above: T > t pmaxa t pmina + t pmaxb = 1.2 ns 1.0 ns ns = 0.9 ns, which is less strict than the original constraint found in that part. d) What are some drawbacks/limits of the wave pipelining technique? Hints: think about previous questions, what if there were more logic blocks, etc? The general drawback is that timing is much trickier. Minimum and maximum timing delays must be well characterized, and they must be close to each other. It s not always trivial to design a combinational circuit where the shortest path is almost as long as the longest path. The more logic stages are added between two registers, or the greater the number of waves that flow through a path at one, the tighter all of the timing constraints become. Some of this may be alleviated if you can find correlations between the delays in logic blocks. For example, if you know that the worst case delay for A results in an output that does not lead to the worst case delay for B, then the worst case delay through A and B is actually less than t pmaxa + t pmaxb. But finding the actual worst case delay in this case may be not be trivial.

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