ASIC FPGA Chip hip Design Pow Po e w r e Di ssipation ssipa Mahdi Shabany


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1 ASIC/FPGA Chip Design Power Di ssipation Mahdi Shabany Department tof Electrical ti lengineering i Sharif University of technology
2 Outline Introduction o Dynamic Power Dissipation Static Power Dissipation
3 Outline Introduction o Dynamic Power Dissipation Static Power Dissipation 3
4 Why Power Matters? Packaging costs Power supply rail design Chip and system cooling costs Noise immunity and system reli ability Battery life (in portable systems) Environmental concerns
5 Why worry about power? Chip Power Density Sun s Surface Power Density (W/ /cm) Nuclear Reactor 8086 Hot Plate Year Rocket Nozzle P6 Pentium chips might ihbecome hot Source: Borkar, De Intel
6 Why worry about power? Standby Power Year Power supply V dd (V) 1.5 Threshold V T (V) 0.4 Drain leakage will increase as V T decreases to maintain noise margins and meet frequency demands, leading to excessive battery draining standby power consumption. 50% KW 40% 1.7KW by Power Stand 30% 0% 10% 1W 88W 400W 0%
7 Power and Energy Figures of Merit Power consumption in Watts Determines battery life in hours Peak power Determines power ground wiring designs Sets packaging limits Impacts signal noise margin and reliab bility analysis Energy efficiency in Joules Rate at which power is consumed over time Energy = power * delay Joules = Watts * seconds Lower energy number means less power to perform a computation at the same frequency Power is the rate at which energy is delivered or exchanged; Power dissipation is the rate at which energy is taken from the source and converted into heat
8 Power vs. Energy Watts Power is the height of curve Lower po ower design could simply be slower Approach 1 Approach Watts time Energy is the area under curve Two approaches require the same energy Approach 1 Approach time
9 Power and Energy Power is drawn from a voltage source attached to the V DD pin(s) of a chip. Instantaneous Power: Energy: Average Power: P () t I () t V () t E P T avg 0 P () t dt T E 1 T T 0 P () t dt
10 Power in Circuit Elements P t I t V VDD DD DD t VR PR t IR t R R dv EC I t V t dt C V t dt dt 0 0 V C 0 1 C V t dv CV C
11 Power Dissipation Power: Due to the current flowing from supply to ground Power Dissipation: P I D V Dynamic Power : Occurs only when t he gate switches Charging/discharging of load capacitances Short circuit power during switching (when both NMOS and PMOS are ON) Static Power: Due to the presence of a V DD a path in the gate b/w the power supply & GND In CMOS, when circuit is quiescent (no switching) one of the transistors is OFF thus ideally no current flows through an OFF transistor so no current b/w VDD and GND thus zero static power
12 Power Dissipation Power Dissipation Dynamic Power Static Power (Leakage) Main Dynamic Power Short circuit Power
13 CMOS Total Energy & Power Equations E = C V L DD α 01 + α V sc DD C L + V DD I static f 01 = α 01 * f Clk P = C L V DD f 01 + α s c V DD C L f Clk + V DD I static Dynamic Power (~90% today and decreasing relatively) Short circuit Power (~8% today and decreasing absolutely) Static Power (~% today and increasing)
14 Outline Introduction o Dynamic Power Dissipation Static Power Dissipation 14
15 Power Dissipation Power Dissipation Dynamic Power Static Power (Leakage) Main Dynamic Power Short circuit Power
16 Power Dissipation: Main Dynamic Power Due to the charging/discharging the load capacitances V out P avg 1 T T 0 v(t)i(t)dt V DD T/ T P avg 1 T dv 1 T/ out (Vout)CL 0 dt dt T T/ V out ( C L dv out dt ) dt P avg 1 T T/ V out Vout C L 0 C L T T/ 1 T V DD C L C L V DD f Clk
17 Power Dissipation: Dynamic Power Average Dynamic Power: Linearly dependent to f Clk (Clock frequency) Independent of the transistor sizing Considering the utilization factor: P avg αc L V DD f Clk In general, a chip with higher area b urns morepower unlessits utilization factor is lower Power Delay Dl Product: (dissipated i d as PDP C L α : Activity heat tin transistors) t L V DD Factor
18 Charging a Capacitor When the gate output rises Energy stored in capacitor is E CV 1 C L DD But energy drawn from the supply is dv EVDD I t VDD dt CL VDD dt dt 0 0 VDD CV L DD dv CV L DD 0 Half the energy from V DD is dissipated in the PMOS transistor as heat, other half stored in the capacitor When the gate output falls Energy in capacitor is dumped to GND Dissipated as heat in the NMOS transistor
19 Dynamic Power Consumption f 01 Energy/transition = C L * V DD * α 01 L DD 01 P dyn = Energy/transition * f = C L * V DD * α 01 * f P dyn = C eff * V DD * f where C eff = α 01 C L Not a function of transistor sizes! Data dependent a function n of switching activity!
20 Lowering Dynamic Power Capacitance: Function of fan out, wire length, transistor sizes Supply Voltage: Has been dropping with successive generations P dyn = C L V DD α 01 f Activity factor: How often, on average, do wires switch? Clock frequency: Increasing
21 Lowering Dynamic Power Try to minimize: Activity factor Capacitance Supply voltage Frequencyq y P dyn = C L V DD α 01 f
22 Lowering Dynamic Power Activity Factor Probability that output is zero in one cycle and will be one in the next cycle where α 01 P 0 P 1 N 0 N N 1 N N 0 N 0 : Number of zero entries in the output column of the function truth table N 1 : Number of one entries in the output column of the function truth table ( N N N 0 ) Example: A input NOR α 3(4 3) 01 P 4 avg C L V DD f Clk
23 Example A 4 input AND is built out of two levels of gates Estimate the activity factor at each node if the inputs have P = 0.5
24 Lowering Dynamic Power: Clock Gating The best way to reduce the activity is to turn off the clock to registers in unused blocks Saves clock activity (α = 1) Eliminates all switching activity in the block Requires determining if block will be used
25 Lowering Dynamic Power: Capacitance Gate capacitance Fewer stages of logic Small gate sizes Wire capacitance Good floorplanning to keep communicating blocks close to each other Drive long wires with inverters or buffers rather than complex gates
26 Lowering Dynamic Power: Voltage / Frequency Run each block at the lowest possible voltage and frequency that meets performance requirement s Voltage Domains Provide separate supplies to different blocks Level converters required when crossing from low to high h V DD domains Dynamic Voltage Scaling Adjust V DD and f according to wo rkload
27 Power Dissipation: Dynamic Power In a digital CMOS circuit: t t p p I sat CV K(V DD V ) t CV t p (V CV (V DD DD f max DD V t ) V DD V ) t V DD Therefore, it can be shown that P CV avg DD 3 f V DD V DD delay Power Throughput can be compromised for power
28 PDP and EDP Power delay product (PDP) = P av * t p = C L V DD PDP is the average energy consumed per switching event (Watts * sec = Joule) Lower power design could simply be a slower design For a given structure the PDP may be made arbitrarily low by reducing the supply voltage that comes at the expense of performance. Energy delay product (EDP) = PDP * t p = P av * t p EDP is the average energy consume ed multiplied by the computation time required Takes into account that one can trade increased delay for lower energy/operation (e.g., via supply voltage scaling that increases delay, but decreases energy consumption)
29 PDP and EDP alized) EnergyD e lay ( norm energy delay energy delay Vdd (V) Rule of thumb: V Opt DD 3 V t Sat DS V
30 Understanding Tradeoffs Which design is the best (fastest, coolest, Constant EDP s are the straight lines in both)? the graph b Lower EDP d c a Slope=EDP (a better than c) (c better than b) (How about b, d?) 1/Delay better
31 Power Dissipation Power Dissipation Dynamic Power Static Power (Leakage) Main Dynamic Power Short circuit Power
32 Short Circuit Power Consumption Finite slope of the input signal causes a direct current path between V DD and GND for a short period of time during switching when both the NMOS and PMOS transistors are condu ucting. V DD V DD  V tp V tn I SC V out C L t SC Rise Time Fall Time
33 Short Circuit Currents Determinates t sc t r sc t f sc I C dv dt t I sc sc,avg C sc V DD I sc t sc I sc,avg T Peak and duration ofi sc bothincrease asthe input slope decreases P sc I sc V DD t I sc sc,avg V DD f P sc C sc V DD f α sc C L V DD f E sc C sc V DD α sc C L V DD
34 Short Circuit Currents Determinates P sc α sc C L V DD f E sc α sc C L V DD I peak determined by Saturation current of the P an nd N transistors, which depend on their sizes, process technology, temperature, etc. Strong function of the ratio between input and output slopes Function of C L
35 Impact of C L on I sc V DD V DD I SC ~0 I SC ~I max V in C L V out V in C L V out Large capacitive load Small capacitive load Output fall time significantly larger than input rise time. As the source drain voltage of the PMOS is approximately 0 during transition, the device shuts off without ever delivering any current, so I sc is close to zero. Output fall time substantially smaller than the input rise time. Drain source voltage of PMOS equals VDD for most of the transition period, giving maximum I sc
36 I peak as a Function of C L.5 x 10 4 C L = 0 ff When load capacitance is small, I peak is large C L = 100 ff L C L = 500 ff 0 4 time (sec) Short circuit dissipation is minimized by matching the rise/fall times of the input and output signals slope engineering. 6 x 10 10
37 P sc as a Function of Rise/Fall Times V DD = 3.33 V 5 4 When load capacitance is small (t sin /t sout > for V DD > V) the power is dominated by P sc If V DD < V Tn + V Tp then P sc is eliminated since both devices are never ON at the same time V DD =.5 V V DD = 1.5V 0 t sin /t sout 4 For large capacitance values, all the epower dsspato dissipation is devoted to charging and discharging the load capacitance. When the rise/fall times of inputs and outputs are equalized, most power dissipation is associated with dynamic power and only a minor fraction (<10%) is devoted to P sc.
38 Dynamic Power Example 1 billion transistor chip 50M logic transistors sto s Average width: 1 L min Activity factor = M memory transistors Average width: 4 L min Activity factor = V 5 nm process C = 1 ff/mm (gate) ff/ /mm (diffusion) Estimate dynamic power 1 GHz. Neglect wire capacitance and short circuit current.
39 Dynamic Power Example 6 C logic m / 1.8 ff / m 7 nf 6 C mem m / 1.8 ff / m 171 nf P dynamic Clogic C mem GHz 61W 6.1 7: Power 39
40 Outline Introduction o Dynamic Power Dissipation Static Power Dissipation 40
41 Power Dissipation Power Dissipation Dynamic Power Static Power (Leakage) Main Dynamic Power Short circuit Power
42 Power Dissipation: Static Power Non ideal Effects: small leakage current flows through the OFF transistor (I static ) Sources of Leakage: T 1 Pstatic i T 0 static V DD dt I static Sub threshold Conduction: Exponentially increases as V T scales down Tunneling through the gate oxide: Exponentially increases as oxide thickness decreases (Important for 130nm and smaller technologies) Leakage through reverse biased diodes V DD Static power dissipation an issue in deep sub micron processes
43 Power Dissipation: Static (Leakage) Power Sub threshold current is the dominant factor. All increase exponentially with tempera ture! Vout Drain junction leakage Gate leakage Sub threshold current
44 Leakage as a Function of V T Continued scaling of supply voltage and the subsequent scaling of threshold h voltage will make sub threshold conduction a dominate component of power dissipation. 10 ID (A) 10 7 An 90mV/decade V T roll off so each 55mV increase in V T gives 3 orders of magnitude reduction in leakage (but adversely affects performance) 10 1 VT=0.4V VT=0.1V VGS (V)
45 TSMC Processes Leakage and V T CL018 G CL018 LP CL018 ULP CL018 HS CL015 HS CL013 HS V dd 1.8 V 1.8 V 1.8 V V 1.5 V 1. V T ox (effective) 4 Å 4 Å 4 Å 4 Å 9 Å 4 Å L gate 0.16 m 0.16 m 0.18 m 0.13 m 0.11 m m I DSat (n/p) (A/m) 600/60 500/180 30/ / /370 90/400 I off (leakage) (A/m) ,800 13,000 V Tn 0.4 V 0.63 V 0.73 V 0.40 V 0.9 V 0.5 V FET Perf. (GHz) (G: generic, LP: low power, ULP: ultra low power, HS: high speed)
46 Exponential Increase in Leakage Currents m) akage(na/ I le Temp(C)
47 Leakage Control Leakage and delay trade off Aim for low leakage in sleep and low delay in active mode To reduce leakage: Increase V t : multiple V t Use low V t only in critical circuits Increase V s : stack effect Input vector control in sleep Decrease V b Reverse body bias in sleep Or forward dbody bias in active mode
48 Gate Leakage Extremely strong function of t ox and V gs Negligible gg for older processess Approaches sub threshold leakage at 65 nm and below in some processes An order of magnitude less for PMOS than NMOS Control leakage in the process using t ox > 10.5 Å High k gate dielectrics i hl help Some processes provide multiple t ox eg e.g. thicker oxide for 3.33 V I/Otransistors Control leakage in circuits by limiting V DD
49 Static Power Example Revisit power estimation for 1 billion transistor chip Estimate static power consumpti on Subthreshold leakage Normal V t : 100 na/mm High V t : 10 na/ /mm High Vt used in all memories and in 95% of logic gates Gate leakage 5 na/m mm Junction leakage negligible
50 Solution m / W W normalv highv t t m / m I sub WnormalV 100 na/ m+ W t highv 10 na/ m t / 584 ma Igate WnormalV W t highv 5 na/ m / 75 ma t P 584 ma 75 ma 1.0 V static 859 mw m
51 Review: Designing Fast CMOS Gates Transistor sizing Progressive transistor sizing MOS closest to the output is smallest of series MOS transistors Transistor ordering put latest arriving signal clos est to the output Logic structure reordering replace large fan in gates wit th smaller fan in gate network Apply logical effort Buffer (inverter) insertion separate large fan in from large C L with buffers uses buffers so there are no more than four TGs in series
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