Variation-Resistant Dynamic Power Optimization for VLSI Circuits

Transcription

1 Process-Variation Variation-Resistant Dynamic Power Optimization for VLSI Circuits Fei Hu Department of ECE Auburn University, AL Ph.D. Dissertation Committee: Dr. Vishwani D. Agrawal Dr. Foster Dai Dr. Darrel Hankerson November 16, 2005

2 Outline Introduction Background Dynamic power dissipation Glitch reduction Previous LP model Process-variation variation-resistant resistant LP model Process variation Delay model LP model based on worst-case timing LP model based on statistical timing Input-specific optimization Without process-variation With process-variation Experimental results Conclusion Fei Hu, PhD Dissertation 2

3 Introduction Power component for CMOS circuits P avg = P static + P dynamic P dynamic 1/2 kc L V dd dd2 f clk Power dissipation problem For constant die size, total capacitance increases by 40% when transistor size is reduced by 70% Clock frequency is scaled up faster than the minimum feature size (MFS) Leakage power increases dramatically as MFS reduces into submicron region Architecture trend is towards programmability and reusability leads to more hunger for power Fei Hu, PhD Dissertation 3

4 VLSI Chip Power Density Power Density (W/cm 2 ) Source: Intel Nuclear Reactor Hot Plate Rocket Nozzle P6 Pentium Sun s Surface Year Fei Hu, PhD Dissertation 4

5 Outline Introduction Background Dynamic power dissipation Glitch reduction Previous LP model Process-variation variation-resistant resistant LP model Process variation Delay model LP model based on worst-case timing LP model based on statistical timing Input-specific optimization Without process-variation With process-variation Experimental results Conclusion Fei Hu, PhD Dissertation 5

6 Background Dynamic power dissipation P dyn = P switching + P short-circuit Switching power dissipation P switching = 1/2 kc L V dd dd2 f clk V dd 1 0 off 1 0 on i c C L Gnd Fei Hu, PhD Dissertation 6

7 Background Short-circuit power dissipation Short-circuit current when both PMOS and NMOS are on Very much affected by the rising and falling times of input signals significant when input rise/fall time much longer than the output rise/fall time Can be kept to a insignificant portion of P dyn Fei Hu, PhD Dissertation 7

8 Background Glitch reduction A important dynamic power reduction technique Static glitch Glitch power consumes 30~70% P dyn for typical circuits Related techniques Balanced delay Hazard filtering Transistor/Gate sizing Linear Programming approach Fei Hu, PhD Dissertation 8

9 Glitch reduction Original circuit Balanced path/ path balancing Equalize delays of all path incident on a gate Balancing requires insertion of delay buffers Hazard/glitch filtering Utilize glitch filtering effect of gate Not necessary to insert buffer Fei Hu, PhD Dissertation 9

10 Glitch reduction Transistor/gate sizing Find transistor sizes in the circuit to realize the delay No need to insert buffer Suffers from nonlinearity of delay model large solution space, numeric convergence and global optimization not guaranteed Linear programming approach Adopt both path balancing and hazard filtering Find the optimal delay assignments of gates Use technology mappings to map the gate delay assignments to transistor/gate dimensions. Guaranteed optimal solution, a convenient way to solve a large scale optimization problem Fei Hu, PhD Dissertation 10

11 Previous LP approach Timing window (t, T) t 6 t 5 T 6 T 5 t 7 T 7 d 7 Gate constraints: T 7 T 5 + d 7 T 7 T 6 + d 7 t 7 t 5 + d 7 t 7 t 6 + d 7 d 7 > T 7 t 7 Circuit delay constraints: T 11 maxdelay T 12 maxdelay Objective: Minimize sum of buffer delays Fei Hu, PhD Dissertation 11

12 Outline Introduction Background Dynamic power dissipation Glitch reduction Previous LP model Process-variation variation-resistant resistant LP model Process variation Delay model LP model based on worst-case timing LP model based on statistical timing Input-specific optimization Without process-variation With process-variation Experimental results Conclusion Fei Hu, PhD Dissertation 12

13 Process-variation variation-resistant resistant optimization Motivation Gate delay assumed fixed in previous models Variation of gate delay in real circuits Environmental factors: temperature, V dd Physical factors: process variations Effect of delay variation Glitch filtering conditions corrupted Power dissipation increases from the optimized value Leakage variation possible, requires separate investigation Our proposal Consider delay variations in dynamic power optimization Only consider process variations (major source of delay variation) Fei Hu, PhD Dissertation 13

14 Process and delay variations Process variations Variations Variations due to semiconductor process V T, t ox, L eff, W wire, TH wire, etc. Inter-die variation Constant within a die, vary from one die to another die of a wafer or wafer lot Intra-die variation Variation within a die Due to equipment limitations or statistical effects in the fabrication process, e.g., variation in doping concentration Spatial correlations and deterministic variation due to CMP and optical proximity effect Fei Hu, PhD Dissertation 14

15 Process and delay variations Delay variation First order gate delay model CL Vdd CL Vdd Td = = I μc ( W ox ) L ( V dd V t ) 2 Gate delay sensitive to process-variations Related previous work Static timing analysis Worst case timing analysis Statistical timing analysis Power optimization under process-variations Voltage scaling, multi-v dd /V th considering critical delay variations Gate sizing using statistical delay model No work on glitch power optimization 2 Fei Hu, PhD Dissertation 15

16 Delay model and implications Random gate delay model D = D +Δ D +ΔD total, i nom, i inter,i intra,i Truncated normal distribution Assume independence Variation in terms of σ/d nom,i ratio Effect of inter-die variations Depends on its effect to switching activities Definition of glitch-filtering probability P glt = P {t 2 -t 1 < d} Signal arrival time t 1, t 2 Gate inertial delay d Theorem 1 states the change of P glt due to inter-die variation 1 k k Δ Pglt = erf( ) erf( ) ( r k) erf(), the error function k, a path and gate dependent constant r, σ/d nom,i ratio for inter-die variations Fei Hu, PhD Dissertation 16

17 Delay model and implications Effect of inter-die variations For a large inter-die variation,, r = 0.15, ΔP glt < Negligible effect on switching activity Fei Hu, PhD Dissertation 17

18 Delay model and implications Process-variation variation-resistant resistant design Can be achieved by path balancing and glitch filtering Critical delay may increase Theorem 2 states that a solution is guaranteed only if circuit delay d is allowed to increase Proved by example, assuming 10% variation Fei Hu, PhD Dissertation 18

19 LP model based on worst-case timing Timing model Fei Hu, PhD Dissertation 19

20 LP model based on worst-case timing Constraints Gate constraints Tb Tb Tb Glitch filtering constraints Tb tb < d (1 3 r) α where r < 0.33 (33%) Delay constraints for POs Ta D Parameter i i i Ta ; 1 Ta j; Ta ; k tb tb tb i i i i i i i max ta ; 1 ta j; ta ; k Tai = Tbi + di (1 + 3 r); ta = tb + d (1 3 r); i i i r, σ/d nom,i ratio D max, circuit delay parameter α,, optimism factor [1, ]; 1 all glitches filtered, no glitch filtered Objective Minimize #buffer inserted sum of buffer delays Fei Hu, PhD Dissertation 20

21 LP model based on statistical timing Worst-case timing tends to be too pessimistic Statistical timing model with random variables Gate 1 ta 1 Ta Gate j ta j Ta j Gate i ta i Ta i ta k Ta k d i Gate k tb i Tb i Fei Hu, PhD Dissertation 21

22 LP model based on statistical timing Minimum-maximum maximum statistics needed for tb i, Tb i Previous works tb Tb i 1 j k Min, Max for two normal random variable not necessarily distributed ted as normal Can be approximated with a normal distribution Requiring complex operations, e.g., integration, exponentiation, etc. Challenges for LP approach = Min( ta, ta, ta ); = Max( Ta, Ta, Ta ); i 1 j k Require simple approximation w/o nonlinear operations Our approximation for C=Max( Max(A,B), A, B, and C are Gaussian RVs μc = Max( μa, μb) μ + 3σ = Max( μ + 3 σ, μ + 3 σ ) C C A A B B Fei Hu, PhD Dissertation 22

23 LP model based on statistical timing Min-Max Max statistics approximation error Negligible when μ A -μ B > 3(σ A + σ B ) Largest when μ A =μ B P CDF A CDF B Actual CDF for Max(A,B) Approximated CDF for Max(A,B) μ = Max( μ, μ ) C A B 1 σ C = Max( μa + 3 σ A, μb + 3 σ B ) μc 3 ( ) A B x Fei Hu, PhD Dissertation 23

24 LP model based on statistical timing Variables Timing, delay variables with mean μ and std dev σ Auxiliary variables, T, t, W = Tb tb, μ, σ Constraints Gate constraints Tb tb i i i W W i i i i Timing window at the inputs for a two-input gate i μ μ ; T μ + 3 σ ; μ μ ; t μ 3 σ ; Tb Ta Tb Ta Ta i 1 i 1 1 μ μ ; T μ + 3 σ ; σ Tb Ta Tb Ta Ta i 2 i 2 2 = ( T μ )/3; Tb Tb Tb i i i tb ta tb ta Ta i 1 i 1 1 μ μ ; t μ 3 σ ; σ tb ta tb ta Ta i 2 i 2 2 = ( μ t )/3; tb tb tb i i i Timing window at outputs μ = μ + μ ; σ = k( σ + r μ ); Ta Tb d Ta Tb d i i i i i i μ = μ + μ ; σ = k( σ + r μ ); ta tb d ta tb d i i i i i i Fei Hu, PhD Dissertation 24

25 LP model based on statistical Constraints Gate constraint Linear approximation timing σ = σ + ( r μ ) σ = k( σ + r μ ) 2 2 Ta Tb d Ta Tb d i i i i i i k [0.707, 1]; choose k=0.85, since Glitch filtering constraints μ = μ μ W Tb tb i i i σ = k( σ + σ ); W Tb tb i i i μ μ > 3 k( σ + r μ ); d W W d i i i i ; A+ B σ P 2 2 A B A B ; Circuit delay constraint μ (1 + 3 r) Ta i D max d i -W i Fei Hu, PhD Dissertation 25

26 LP model based on statistical timing Parameter ratio max, circuit delay parameter α,, optimism factor r, σ/d nom,i D max Objective μ μ > 3 k( σ + r μ ) α; d W W d i i i i α=1, no relaxation α<1, optimistic about the actual glitch width α=0, reduce to previous model Minimize #buffer inserted sum of buffer delays Fei Hu, PhD Dissertation 26

27 Outline Introduction Background Dynamic power dissipation Glitch reduction Previous LP model Process-variation variation-resistant resistant LP model Process variation Delay model LP model based on worst-case timing LP model based on statistical timing Input-specific optimization Without process-variation With process-variation Experimental results Conclusion Fei Hu, PhD Dissertation 27

28 Input-specific optimization Motivation Previous LP models guarantees glitch filtering for any input vector sequence T i - t i < d i for all gates Redundancy in optimization Insertion of more buffers Increased the overhead in power/area In reality, circuit under embedded environments Optimization for input vector sequence that is possible to the circuit, e.g., functional vectors Same reduction in power dissipation w/ less trade-offs in overheads Fei Hu, PhD Dissertation 28

29 Input-specific optimization Glitch generation pattern Input vector pair that can potentially generate a glitch AND gate example: Glitch generation probability P g [i] Probability glitch-generation generation pattern occurs at input of gate i Steady state signal values match the pattern Fei Hu, PhD Dissertation 29

30 Input-specific optimization Application to Previous model w/o process-variation Static optimization Only static glitches/hazards considered Relaxation of constraints Relax glitch filtering constraints where glitches unlikely happen T i - t i < d i => (T i t i )*β i < d i Selective relaxation 0 if Pg [ i] = 0 βi = 1 if Pg [ i] > 0 Generalized relaxation β = i P [] i g 1 e τ Fei Hu, PhD Dissertation 30

31 Input-specific optimization Application to process-variation variation-resistant resistant LP model based on statistical timing Static optimization Relaxation of constraints μ > [ μ + 3 k( σ + r μ ) α] β ; Selective relaxation Generalized relaxation Tuning factor Original objective Current objective d W W d i i i i i Minimize d j; ( j buffers) j 1 Minimize d j + TF ( di); ( j buffers, i other gates) N j i Fei Hu, PhD Dissertation 31

32 Input-specific optimization Why need a tuning factor Dominating path affected critical delay distribution Dominating path 41 Can be [1,41] Fei Hu, PhD Dissertation 32

33 Outline Introduction Background Dynamic power dissipation Glitch reduction Previous LP model Process-variation variation-resistant resistant LP model Process variation Delay model LP model based on worst-case timing LP model based on statistical timing Input-specific optimization Without process-variation With process-variation Experimental results Conclusion Fei Hu, PhD Dissertation 33

34 Experimental results Experimental procedure Flow chart Power estimation Event driven logic simulation Fanout weighted sum of switching activities Variations of C L and V dd ignored Monte-Carlo simulation with 1,000 samples of delays under process-variation Results analysis Un-Opt., unit-delay circuit Opt, previous optimization Opt1, Proc-var var-rstrst optimization worst-case timing Opt2, Proc-var var-rstrst optimization statistical timing D max r, Circuit Data extraction AMPL Circuit generation Logic simulations Results Constraint set data Gate delays Optimized circuit LP models Fei Hu, PhD Dissertation 34

35 Experimental results small variation Power dissipation under no process variation UnOpt Opt (w/o proc var.) Opt1 (worst case proc) Opt2 (statistical proc) c432 c499 c880 c1355 c1908 c2670 c3540 c5315 c6288 c7552 Pwr. Pwr Buf maxdelay Pwr Buf Dmax Pwr Buf Dmax Fei Hu, PhD Dissertation 35

36 Experimental results small variation Power distribution under 5% inter-die, 5% intra-die variation Circuit c432 c499 c880 c1355 c1908 c2670 c3540 c5315 c6288 c7552 Maxdelay Un-Opt Mean Max. Dev. Pwr. (%) Opt (w/o proc var.) Mean Max. Dev. Pwr. (%) Opt1 (worst case proc) Mean Max. Dev. Pwr. (%) Opt2 (statistical proc) Mean Max. Dev. Pwr. (%) Fei Hu, PhD Dissertation 36

37 Experimental results small variation Power timing analysis Example c432 maxdelay=17 maxdelay=26 Complete suppression of power variation Fei Hu, PhD Dissertation 37

38 Experimental results small variation Critical delay distribution Nominal delay Max. Deviation Similar nominal delay Reduced variation by Opt2 for c880, c2670, c5315, c7552 Fei Hu, PhD Dissertation 38

39 Experimental results large variation Power dissipation under no process-variation c432 c499 c880 c1355 c1908 c2670 c3540 c5313 c6288 c7552 Un-opt. Pwr Opt (w/o proc var.) Pwr. Buf. maxdelay Opt1 (worst case proc) Pwr. Buf. Dmax Opt2 (statistical proc) Pwr. Buf. Dmax Fei Hu, PhD Dissertation 39

40 Experimental results large variation Power distribution under 15% intra-die and 5% inter-die variation Circuit c432 c499 c880 c1355 c1908 c2670 c3540 c5313 c6288 c7552 Maxdelay Un-opt Mean Max. Dev. Pwr. (%) Opt (w/o proc var.) Mean Max. Dev. Pwr. (%) Opt1 (worst case proc) Mean Max. Dev. Pwr. (%) Opt2 (statistical proc) Mean Max. Dev. Pwr. (%) Fei Hu, PhD Dissertation 40

41 Experimental results large variation Critical delay distribution Nominal delay Max. Deviation (%) Similar nominal delay Reduced delay variation by Opt2 Fei Hu, PhD Dissertation 41

42 Experimental results input-specific optimization Application to Opt under no process-variation, IS-Opt c432 c499 c880 c1355 c1908 c2670 c3540 c5315 c6288 c7552 maxdelay Un-Opt Pwr. Pwr Opt (w/o proc var.) Delay Buffers IS-Opt (input-specific w/o proc) Pwr Delay Buffers Fei Hu, PhD Dissertation 42

43 Experimental results input-specific optimization Application to Opt2 under process-variation, IS-Opt2 under 15% intra-die and 5% inter-die variation Cir. D Max c c c c c c c c c c Un-opt. Nom. Pwr. Nom. Pwr Opt2 (statistical proc) IS-Opt2 (input-specific statistical proc) Mean Max Dev. No. Nom. Mean Max Dev. No. Pwr. (%) Buf. Pwr. Pwr. (%) Buf Fei Hu, PhD Dissertation 43

44 Experimental results input-specific optimization Trade-off by generalized relaxation c432 circuit with varying τ value Reduction of #buffers with degradation of power distribution Fei Hu, PhD Dissertation 44

45 Experimental results input-specific optimization Critical delay Nominal delay Max. deviation Similar performance for Opt2 and IS-Opt2 Fei Hu, PhD Dissertation 45

46 Outline Introduction Background Dynamic power dissipation Glitch reduction Previous LP model Process-variation variation-resistant resistant LP model Process variation Delay model LP model based on worst-case timing LP model based on statistical timing Input-specific optimization Without process-variation With process-variation Experimental results Conclusion Fei Hu, PhD Dissertation 46

47 Conclusions Proposed a dynamic power optimization technique that is resistant t to the process variation Consider process-variation in terms of the delay variations inter-die and intra-die variations Prove inter-die variation has negligible effect on switching activity and power Construct two new LP models Worst case timing analysis Statistical timing analysis Input-specific optimization to reduce number of buffers Circuit optimized for certain input vector sequence Experimental results Complete suppression of power variation for small circuit and variations Significant reduction of power and delay variations for larger circuit c and variations 53% reduction in power deviation, 40% reduction in delay deviation under 15% intra-die and 5% inter-die variation Input-specific optimization reduces trade-off (buffers) significantly w/ equivalent power and delay performance IS-Opt2 vs. Opt2, Up to 63% reduction of buffer Fei Hu, PhD Dissertation 47

48 Questions For more questions, contact me at Fei Hu, PhD Dissertation 48