Lecture Outline. ESE 570: Digital Integrated Circuits and VLSI Fundamentals. Classification of Digital CMOS Circuits. Digital CMOS Basics
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1 EE 570: iital Interated Circuits and VLI Fundamentals Lec 2: January 19, 2016 MO Fabrication pt. 1: Physics and Methodoloy Lecture Outline! iital CMO asics! VLI Fundamentals! Fabrication Process 2 Classification of iital CMO Circuits iital CMO asics! tatic Circuit " In steady-state the output is evaluated via a low-impedance path between the output and V or N, respectively.! ynamic Circuit " In steady-state the output is evaluated due to the presence or absence of chare, respectively, stored on the output node capacitance. 3 4 MO Transistors MO Transistors 5 6 1
2 Ideal nmo and pmo Characteristics Complementary CMO witch Hih Impedance or Hih Z = 0 = 1 = 1 = a b a = 0 = 0 = 1 b a = Ideal CMO Inverter CMO ates Inverter Truth Table Inverter ymbol A C Inputs A C V PUN PN PUN and PN are ual Networks When the PUN is conductin, the output F will be 1. Hence,the PUN is determined by a oolean expression for the un-complemented output F in terms of the complemented inputs (A,,C,). F = f(a,,c,) Output When the PN is conductin, the output F will be 0. Hence,the PN is determined by a oolean expression for the complemented output F in terms of the un-complemented inputs (A,,C,) CMO ates What ate is this? a b f! Complementary Metal Oxide emiconductor
3 tatic CMO ate tructure Two-Input CMO NOR ate! rives rail-to-rail " Power rails are V dd and nd NOR " output is V dd or nd! Input connects to ates # load is capacitive! Once output node is chared doesn t use enery (no static current)! Output actively driven A F Two-Input CMO NAN ate ate esin Example! esin ate to perform: f = (a + b) c! tratey: A F Z = Hih Impedance (open circuit) 1. Use static CMO structure 2. esin PMO pullup for f 3. Use emoran s Law to determine f 4. esin NMO pulldown for f ate esin Example tatic CMO ource/rains! esin ate to perform: f = (a + b) c! With PMO on top, NMO on bottom " PMO source always at top (near V dd ) " NMO source always at bottom (near nd) a b c f " Why not use NMO for pullup network? Convince yourself with a truth table
4 Multiplexor (MUX) Constructin Compound CMO ates F = (A + C ) output = A s + s Oracle PARC M7 Processor VLI Fundamentals 22 VLI Hierarchical Representations Y-Chart: Abstractions in 3 omains fabricated? - Circuit - Component
5 Y-Chart: Abstractions in 3 omains oal of All VLI esin Enterprises ystem Level! Alorithmic Level ehavioral omain Reister-Transfer Level tructural omain ystem pecification CPU, AIC Loic Level Alorithm Processor, ub-system Reister-Transfer pec. ALU, Reister, MUX Circuit Level oolean Expression ate/flip-flop Transistor symbols Transistor Model Equation! Transistor Layout tandard-cell/ub-cell Layout Convert system pecs into an IC desin in MINIMUM TIME and with MAXIMUM LIKLIHOO that the esin will PEFORM A PECIFIE when fabricated. MAX YIEL + MIN EVELOPMENT TIME + MIN IE AREA=> MIN COT Macro-cell/Module Layout lock/ie Layout Chip/oC/oard Physical omain ilicon Inot and Wafer Manufacturin Fabrication etails Crystal Puller with rotation mechanism inle-crystal ilicon Quartz Crucible Crystal eed Molten Polysilicon Heat hield Heatin Water Element Imae from Quirk & erdajacket ilicon Wafer Manufacturin ilicon Lattice i Inots 300 mm (12 in.)! 28! Forms into crystal lattice i Wafers The ROI of 450mm wafers is compellin: " " A 450mm fab with equal wafer capacity to a 300mm fab can produce 2x the amount of die. A 14nm die from a 450mm wafer will cost 23% less than the same die from a 300mm wafer. 29 Penn 570 prin Khanna Khanna PennEE EE370 Fall
6 ilicon Lattice opin! Cartoon two-dimensional view! Add impurities to ilicon Lattice " Replace a i atom at a lattice site with another opin Elements opin with P (N-type)! End up with extra electrons " onor electrons! (periodic table)! Not tihtly bound to atom " Low enery to displace " Easy for these electrons to move opin with (P-type) IC Manufacturin teps! End up with electron vacancies -- Holes " Acceptor electron sites! Easy for electrons to shift into these sites " Low enery to displace " Easy for the electrons to move " Movement of an electron best viewed as movement of hole
7 Fabrication Photolithoraphy! tart with ilicon wafer! ope! row Oxide (io 2 )! eposit Metal! Mask/Etch to define where features o Time Code: 2:00-4: CMO Processin Technoloy Fabricated n-mo Transistor oron atoms deposited on surface time = 0 s time = 60 s n-mo Transistor Representations nmo Transistor from a 3 Perspective Physical tructure poly ate field oxide L drawn metal 1 n + ate oxide n L effective + p substrate (bulk) Layout Representation n+ n+ L drawn chematic Representation W drawn ate Oxide Field Oxide P-Type ource/rain Reions Field Oxide
8 Fabrication Process Typical N-Well CMO Process row field oxide. Create contact window, deposit & pattern metal film Typical N-Well CMO Process i Idea! ystematic construction of any ate from transistors with CMO PUN and PN! Hierarchical desin process in three domains (behavioural, structural, and physical) allows for complicated desins motivated cost as a function of performance, yield and desin time Admin! Enroll in Piazza site " piazza.com/upenn/sprin2016/ese570! Homework 1 due Thursday " Journal articles will come back in Journal Review Thursdays 47 8
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