Lecture Outline. ESE 570: Digital Integrated Circuits and VLSI Fundamentals. Classification of Digital CMOS Circuits. Digital CMOS Basics

Transcription

1 EE 570: iital Interated Circuits and VLI Fundamentals Lec 2: January 17, 2017 MO Fabrication pt. 1: Physics and Methodoloy Lecture Outline iital CMO asics VLI Fundamentals Fabrication Process 2 Classification of iital CMO Circuits iital CMO asics tatic Circuit " In steady-state the output is evaluated via a low-impedance path between the output and V or N, respectively. ynamic Circuit " In steady-state the output is evaluated due to the presence or absence of chare, respectively, stored on the output node capacitance. 3 4 MO Transistors MO Transistors 5 6 1

2 Ideal nmo and pmo Characteristics Complementary CMO witch Hih Impedance or Hih Z = 0 = 1 = 1 = a b a = 0 = 0 = 1 b a = Ideal CMO Inverter CMO ates Inverter Truth Table Inverter ymbol Complementary Metal Oxide emiconductor 9 10 CMO ates tatic CMO ource/rains A C Inputs A C V PUN PN PUN and PN are ual Networks When the PUN is conductin, the output F will be 1. Hence,the PUN is determined by a oolean expression for the un-complemented output F in terms of the complemented inputs (A,,C,). F = f(a,,c,) Output When the PN is conductin, the output F will be 0. Hence,the PN is determined by a oolean expression for the complemented output F in terms of the un-complemented inputs (A,,C,). With PMO on top, NMO on bottom " PMO source always at top (near V dd ) " NMO source always at bottom (near nd) " Why not use NMO for pullup network?

3 What ate is this? a b f tatic CMO ate tructure rives rail-to-rail " Power rails are V dd and nd " output is V dd or nd Input connects to ates # load is capacitive Once output node is chared doesn t use enery (no static current) Output actively driven Two-Input CMO NOR ate Two-Input CMO NAN ate NOR A F 1 0 A F Z = Hih Impedance (open circuit) Z = Hih Impedance (open circuit) ate esin Example ate esin Example esin ate to perform: f = (a + b) c esin ate to perform: f = (a + b) c tratey: 1. Use static CMO structure 2. esin PMO pullup for f 3. Use emoran s Law to determine f 4. esin NMO pulldown for f a b c f Convince yourself with a truth table

4 Constructin Compound CMO ates F = (A + C ) VLI Fundamentals 19 Oracle PARC M7 Processor VLI Hierarchical Representations fabricated? - Circuit - Component Y-Chart: Abstractions in 3 omains Y-Chart: Abstractions in 3 omains ystem Level ehavioral omain Alorithmic Level Reister-Transfer Level tructural omain ystem pecification Loic Level CPU, AIC Alorithm Processor, ub-system Reister-Transfer pec. Circuit Level ALU, Reister, MUX oolean Expression ate/flip-flop Transistor Model Equation Transistor symbols Transistor Layout tandard-cell/ub-cell Layout Macro-cell/Module Layout lock/ie Layout Chip/oC/oard Physical omain

5 oal of All VLI esin Enterprises Convert system specs into an IC desin in MINIMUM TIME and with MAXIMUM LIKLIHOO that the esin will PEFORM A PECIFIE when fabricated. Fabrication etails MAX YIEL + MIN EVELOPMENT TIME + MIN IE AREA=> MIN COT 25 ilicon Inot and Wafer Manufacturin ilicon Wafer Manufacturin i Inots Crystal Puller with rotation mechanism inle-crystal ilicon Quartz Crucible Crystal eed 300 mm (12 in.) Molten Polysilicon Heat hield Heatin Water Element Imae from Quirk & erdajacket The ROI of 450mm wafers is compellin: " " 27 ilicon Lattice A 450mm fab with equal wafer capacity to a 300mm fab can produce 2x the amount of die. A 14nm die from a 450mm wafer will cost 23% less than the same die from a 300mm wafer. 28 ilicon Lattice Forms into crystal lattice Penn 570 prin Khanna Khanna PennEE EE370 Fall2015 i Wafers 29 Cartoon two-dimensional view 30 5

6 opin Add impurities to ilicon Lattice " Replace a i atom at a lattice site with another opin Elements (periodic table) opin with P (N-type) opin with (P-type) End up with extra electrons End up with electron vacancies -- Holes " onor electrons " Acceptor electron sites Not tihtly bound to atom Easy for electrons to shift into these sites " Low enery to displace " Low enery to displace " Easy for these electrons to move " Easy for the electrons to move " Movement of an electron best viewed as movement of hole IC Manufacturin teps Fabrication tart with ilicon wafer ope row Oxide (io 2 ) eposit Metal Mask/Etch to define where features o Time Code: 2:00-4:

7 Photolithoraphy CMO Processin Technoloy oron atoms deposited on surface time = 0 s time = 60 s Fabricated n-mo Transistor n-mo Transistor Representations Physical tructure poly ate field oxide L drawn metal 1 n + ate oxide n L effective + p substrate (bulk) Layout Representation n+ n+ L drawn chematic Representation W drawn nmo Transistor from a 3 Perspective Fabrication Process ate Oxide Field Oxide P-Type ource/rain Reions Field Oxide 41 row field oxide. Create contact window, deposit & pattern metal film. 42 7

8 Typical N-Well CMO Process Typical N-Well CMO Process i Idea Admin ystematic construction of any ate from transistors with CMO PUN and PN Hierarchical desin process in three domains (behavioural, structural, and physical) allows for complicated desins motivated cost as a function of performance, yield and desin time Enroll in Piazza site " piazza.com/upenn/sprin2017/ese570 Homework 1 due Thursday " Journal articles will come back in lecture