CMOS Devices. PN junctions and diodes NMOS and PMOS transistors Resistors Capacitors Inductors Bipolar transistors

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1 CMOS Devices PN junctions and diodes NMOS and PMOS transistors Resistors Capacitors Inductors Bipolar transistors

2 PN Junctions Diffusion causes depletion region D.R. is insulator and establishes barrier This leads to 1-directional current flow Forms junction capacitor Capacitance highly voltage dependent Can be nuisance or benefits

3 PN Junctions

4 pn junction 1. Doped atoms near the metallurgical junction lose their free carriers by diffusion. 2. As these fixed atoms lose their free carriers, they build up an electric field, which opposes the diffusion mechanism. 3. Equilibrium conditions are reached when: Current due to diffusion = Current due to electric field

5 PN Junctions Initial impurity concentration

6 PN Junctions qn ε si A x p = qn ε si D x n qn A x 2ε si 2 p{ qn D x } 2 n 2ε si

7 φ o PN Junctions 2 q qn 2 2 Ax p v D = ( N Ax p + N Dxn ) = (1 + 2ε 2ε si si N N A D ) Depletion region widths: x x p Built-in potential: n 1/2 2 ε ( φ v ) N ( + ) 1 x 1/2 d 2 ε ( φ v ) N N si 0 D A = qnd N A ND si 0 D D = qn A( N A + ND) x / x = N / N n p A D kt N N N N ϕ o = ln( ) = V ln( ) q n n A D A D 2 t 2 i i

8 Example NA=10^15 atoms/cm^3, ND=10^16, vd=-10 Ni=2.25*10^20 Phi_o=26ln(10^15*10^16/2.25/10^20)=638 mv xp= µm xn= 0.35 µm Max field = q*na*xp/ε = -5.4*10^4 V/cm Note the large magnitude of the field

9 Excercise Suppose that v D = 0, ψ o = 0.637V and N D = atoms/cm3. If N A = atoms/cm3 p-side depletion width =?? n-side depletion width =?? If N A = atoms/cm3: p-side depletion width =?? n-side depletion width =??

10 The depletion charge PN Junctions 2ε siqn AN D Q j = AqN Axp = AqNDxn = A ( φ0 vd) NA + ND The junction capacitance C j dq 2ε qn N 1 = = = dv N N v 1/2 j si A D j0 A 1/2 ( 0 ) m D A + D φ v D (1 D ) φ0 1/2 C 1/2

11 Can be used as voltage controlled capacitor Here m = 1/2 for the step change in impurity concentration. For gradual concentration change, m = 1/3.

12 Impurity concentration profile for diffused pn junction v / D/ V xl t { ( ) } 2 ni p pn ( x) = 1+ e 1 e N D

13 Current density at boundary due to wholes: Total: J Diode current: dpn ( ) ( x J ) p x = qdp dx x= p 2 qd n (0) = p i v V 1 N L D p 0 { / } D t e J J J qn D D e { / } D t 2 (0) (0) (0) p n = v V p + n = i + 1 NDLp NAL n i AJ D qn A D e I e { / } { / } D t D t 2 p n v V v V D = (0) = i + 1 = S 1 NDLp NAL n

14 D S { v / 1} D Vt i = I e

15 Reverse-Biased PN Junctions

16 Our book shows that Breakdown Voltage

17 Metal-Semiconductor Junctions Ohmic Junctions: A pn junction formed by a highly doped semiconductor and metal Behaves like resistor Schottky Junctions: A pn junction formed by a lightly doped semiconductor and metal Behaves like a diode

18 The MOS Transistors

19 Capacitors Two conductor plates separated by an insulator form a capacitor Intentional capacitors vs parasitic capacitors Linear vs nonlinear capacitors Linear capacitors:

20 Capacitor specifications 1. Dissipation (quality factor) of a capacitor 2. Parasitic capacitors to ground from each node of the capacitor. 3. The density of the capacitor in Farads/area. 4. The absolute and relative accuracies of the capacitor. 5. The Cmax/Cmin ratio which is the largest value of capacitance to the smallest when the capacitor is used as a variable capacitor (varactor). 6. The variation of a variable capacitance with the control voltage (is it linear). 7. Linearity, q = Cv.

21 PMOS on Substrate Gate Capacitors High density, good matching, but nonlinear

22 NMOS in p-well Gate Capacitor Gate as one terminal of the capacitor Some combination of the source, drain, and bulk as the other terminal

23 Gate Capacitor vsv GS with D=S=B

24 3-seg Approximation

25 Gate Capacitor in Inversion Mode

26 Inversion Mode NMOS Capacitor E. Pedersen, RF CMOS Varactors for 2GHz Applications, Analog Integrated Circuits and Signal Processing, vol. 26, pp , Jan

27 Accumulation NMOS Gate Cap in n-well

28 Accumulation Mode NMOS Gate Cap E. Pedersen, RF CMOS Varactors for 2GHz Applications, Analog Integrated Circuits and Signal Processing, vol. 26, pp , Jan

29 PN Junction Capacitors in a Well

30 PN-Junction Capacitors E. Pedersen, RF CMOS Varactors for 2GHz Applications, Analog Integrated Circuits and Signal Processing, vol. 26, pp , Jan

31 Poly-poly cap on FOX High density, good matching, good linearity, but require two-poly processes

32 Very linear Poly-poly cap on STI Small bottom plate parasitics

33 Metal-insulator-metal cap

34 Fringe Capacitors

35 R. Aparicio and A. Hajimiri, Capacity Limits and Matching Properties of Integrated Capacitors, IEEE J. of Solid-State Circuits, vol. 37, no. 3, March 2002, pp

36

37 Comparison

38 Non-ideal Behavior Dielectric gradients Edge effects Process biases Parasitics Voltage dependence Temperature dependence

39 Parasitic Capacitors

40

41 Proper layout of capacitors For achieving C A = 2C B, which one is better?

42 Various Capacitor Errors

43

44 Temperature and Voltage Dependence MOSFET Gate Capacitors: Absolute accuracy ±10% Relative accuracy ±0.2% Temperature coefficient +25 ppm/c Voltage coefficient -50ppm/V Polysilicon-Oxide-Polysilicon Capacitors: Absolute accuracy ±10% Relative accuracy ±0.2% Temperature coefficient +25 ppm/c Voltage coefficient -20ppm/V Metal-Dielectric-Metal Capacitors: Absolute accuracy ±10% Relative accuracy ±0.6% Temperature coefficient +40 ppm/c Voltage coefficient -20ppm/V, 5ppm/V2 Accuracies depend upon the size of the capacitors.

45 Improving Cap Matching Divide each cap into even # of unit caps Each unit cap is square, has identical construction, has identical vicinity, has identical routing The unit caps for matching critical caps are laid out with inter-digitation, common centroid, or other advanced techniques. Same comments apply to resistors and transistors

46 Resistors in CMOS Diffusion resistor polysilicon resistor well resistor metal layer resistor contact resistor

47 Resistor specs

48 Diffusion resistor in n-well

49 Source/Drain Resistor

50 Polysilicon resistor on FOX

51 Polysilicon Resistor

52 n-well resistor on p-substrate

53 N-well Resistor

54 Metal Resistor

55 Thin Film Resistors

56 Thermoelectric (Seebeck) Effects When two materials form a junction, a voltage difference is generated, which depends on the temperature But a single junction voltage cannot be measured It needs at least two junctions The voltage difference is: V = (S B S A )T 2 (S B S A )T 1 = (S B S A )(T 2 T 1 )

57 Seebeck Coefficients S A and S B are called Seebeck coefficients of material A and material B Roughly speaking S is inversely related to the conductivity of the material Metals have low S, semiconductors have high S High resistivity materials (with light doping) pose serious thermoelectric problems

58 Moffat, R., Notes on Using Thermocouples, ElectronicsCooling, Vol. 3, No. 1, 1997

59 Resistor Layout But what about horizontal temperature gradient? Use antiparallel layout

60 X X X X X X X X X X X X X X X X X X X X X X X X HW1: Prove that if following the arrow, all the metal to poly contacts have the same centroid as all the poly to metal contacts, then the thermoelectric effect due to linear thermo gradient is cancelled. HW2: Generalize HW1 to design a layout pattern so that thermo-electric effects due to both linear and nonlinear thermo gradients are cancelled.

61 Suggestions Use larger area (increase both W and L) to improve accuracy Use metal to make turns, i.e., use straight strips only Use unit resistors Use dummies Use identical structures and vivinities Interdigitate, common centroid, and other techniques for good matching

62 Passive RC Performance

63 Parasitic Bipolar in CMOS Vertical PNP Horizontal NPN

64 Latch-up problem

65 Preventing Latch-up

66 Guard Rings Collect carriers flowing in the silicon Bypass unwanted currents to VDD or VSS Isolate sensitive circuits from noise and/or interferences

67 Butted Contacts and Guard Rings To reduce sensitivity To prevent latch up

68 Intentional Bipolar It is desirable to have the lateral collector current much larger than the vertical collector current. Lateral BJT generally has good matching. The lateral BJT can be used as a photodetector with reasonably good efficiency. Triple well technology allows the current of the vertical collector to avoid the substrate.

69 Donut PMOS as bipolar A Field-Aided Lateral BJT Use minimum channel length enhance beta to 50 to 100 Can be done in ON0.5 or TSMC0.18 No STI

70 ESD protection A very serious problem Not enough theoretical study Many trade secrets Learn from experienced designers

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