ELEC 3908, Physical Electronics, Lecture 26. MOSFET Small Signal Modelling


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1 ELEC 3908, Physical Electronics, Lecture 26 MOSFET Small Signal Modelling
2 Lecture Outline MOSFET small signal behavior will be considered in the same way as for the diode and BJT Capacitances will be considered in more detail for the MOSFET structure, and depletion, extrinsic and intrinsic components will be identified More attention will be paid to incorporating features of the process into quantities which can be scaled to absolute values for a particular device based on its geometry for the diode and BJT, only the active 1D area was used for scaling Page 262
3 Low Frequency Parameters The transconductance is defined as the rate of change of I D with respect to V GS with V DS fixed in saturation g m di C W D = μ $ dv L V V 1+ V ( )( λ ) GS V n ox GS T DS DS The output conductance is defined as the rate of change of I D with respect to V DS with V GS fixed in saturation g o did = μ dv C$ DS V n ox GS W L ( V V ) GS 2 T 2 λ Page 263
4 Low Frequency Small Signal Equivalent Circuit Using the definitions of g m and g o, the small signal equivalent circuit can be constructed as shown Note there is no equivalent of g π in the MOSFET small signal equivalent circuit, since (ideally) no gate current flows due to the electrical isolation of the gate oxide Page 264
5 MOSFET Capacitance There are three origins of capacitance in the MOSFET structure Depletion capacitance associated with the sourcesubstrate and drainsubstrate depletion regions, modelled as sidewall and bottom components Extrinsic capacitance due to physical overlaps in the structure Intrinsic capacitance due to the fundamental chargevoltage relationships in the device Page 265
6 Physical Origin of Sidewall Depletion Capacitance The depletion capacitance associated with the external sides of the source and drain depletion regions is termed sidewall capacitance The same voltage dependence model is used as for the pnjunction A per unit peripheral length term is used instead of a per unit area term because the junction depth is not a parameter which can be varied The total capacitance is the per unit periphery term multiplied by the source perimeter P S or the drain perimeter P D Page 266
7 Sidewall Depletion Capacitance Model The sidewall components of the sourcebulk and drainbulk depletion capacitance are modelled as C C SB sidewall DB sidewall = = C depsw ( 1+ V V ) SB C depsw ( 1+ V V ) DB The primed quantity C denotes a per unit length term Note that P S and P D are the outside perimeters, not counting the part facing the channel P S bisb P D bidb z SB z DB Page 267
8 Physical Origin of Bottom Depletion Capacitance The depletion capacitance associated with the bottom source and drain depletion regions is termed bottom capacitance Again, the same voltage dependence model is used as for the pnjunction A per unit area term is used because the source and drain areas are quantities which can be varied in layout The total capacitance is the per unit area term multiplied by the source area A S or the drain area A D Page 268
9 Bottom Depletion Capacitance Model The bottom components of the sourcebulk and drainbulk depletion capacitance are modelled as C$ depbot AS CSB = bottom zsb ( 1+ VSB VbiSB ) C$ depbot AD CDB = bottom zdb ( 1+ VDB VbiDB) A S and A D are the junction areas as defined by the active region mask NOTE: really should have written V BS and V BD to be consistent with pnjunction expressions, however these are always reverse biases in normal operation Page 269
10 Final Depletion Capacitance Model The final models for the absolute sourcebulk and drainbulk depletion capacitances are the sum of the sidewall and bottom components C C SB DB = = C depsw P zsb ( 1+ V V ) ( 1+ V V ) C S P zdb ( 1+ V V ) ( 1+ V V ) The model parameters are usually determined from measurements C$ depbot SB bisb SB bisb 2 sidewall bottom depsw D C$ A depbot DB bidb DB bidb 2 sidewall bottom + + S A z D SB z DB Page 2610
11 Example 26.1: Depletion Capacitance Calculation For the MOSFET structure shown below, what are C SB and C DB? The substrate has N A =2x10 16 /cm 3. Use /cm 3 as the source/drain doping, and assume grading coefficients of 0.4 for both junctions C = 3 10 Fcm C$ = 4 10 Fcm 2 depsw depbot Page 2611
12 Example 26.1: Solution The source and drain perimeters, not counting the channel side, are P S = P = = 16 μm D The source and drain areas are A S = A = 4 8 = 32μm 2 D The sourcebulk and drain bulk built in potentials are given by V bisb = VbiDB = ln ( ) 10 2 = 089. V Page 2612
13 Example 26.1: Solution (con t) The source bulk junction potential is 1V of reverse bias, so the capacitance is C SB = ( 1 ( 1) 089) ( ) = F ( ) The drain bulk junction potential is 4V of reverse bias, so the capacitance is C DB = ( 1 ( 4) 089) ( ) = F ( ) Page 2613
14 Extrinsic MOSFET Capacitance Extrinsic MOSFET capacitance arises from overlaps in the fabricated structure These are usually due to processing limitations or rules imposed by processing limitations, so in principle extrinsic capacitance can be minimised by better processing techniques Page 2614
15 Gate/Source and Gate/Drain Overlap Capacitance When the source and drain are implanted, lateral diffusion of dopants causes the source and drain regions to extend under the gate (leading to the effective channel length) This creates a region of overlap between the gate and source at one end, and the gate and drain at the other end The capacitance is defined by the channel width W, the extent of the overlap x ovl and the oxide thickness t ox Page 2615
16 G/S and G/D Overlap Capacitance Model The capacitances are modeled as parallel plate structures, with separation t ox and area x ovl W For symmetrical lateral diffusion, the overlap capacitances can be written as C = CGD ovl = ε t GS, ovl, ox ox x ovl W Page 2616
17 G/S and G/D Overlap Capacitance Model (con t) The only factor in the model equations which is variable by a circuit designer is W, so the remaining terms are lumped into a per unit width overlap capacitance ε ox C GS, ovl = C GD, ovl xovl ( Fcm) t The total capacitance is then the per unit width factor W ox C = C W GS, ovl GS, ovl C = C W GD, ovl GD, ovl Page 2617
18 GateSubstrate Overlap Capacitance To ensure that the source and drain are separated (recall the selfaligned process), the gate is usually required to overlap the active region This leads to a capacitance between the gate extension over the field oxide and the substrate Page 2618
19 GateSubstrate Overlap Capacitance Model Because of the illcontrolled spatially varying nature of the dielectric thickness, the gatebulk (substrate) capacitance is very difficult to predict analytically Measurements are usually done to extract a per unit length capacitance C GB,ovl, which is then multiplied by the drawn gate length The total capacitance is then C = C L GB, ovl GB, ovl Page 2619
20 Example 26.2: Extrinsic Capacitance Calculation Calculate the extrinsic capacitances for the structure below. Measurements give C GB,ovl = 1.1x1012 F/cm. t ox is 20nm, and the lateral diffusion is 0.1 μm. Page 2620
21 Example 26.2: Solution The gatesource and gatedrain overlaps are the amount of lateral diffusion, 0.1 μm. The per unit width capacitances are therefore C = C = GS, ovl GD, ovl = Fcm From the layout, the channel width is 8 μm, so the total overlap capacitances are C = C GS, ovl GD, ovl = = F Page 2621
22 Example 26.2: Solution (con t) The drawn gate length is 2 μm, so the given per unit length gatebulk overlap capacitance can be used to find the total gatebulk overlap capacitance as C = C L GB, ovl GB, ovl = = F Page 2622
23 Intrinsic MOSFET Capacitance Intrinsic MOSFET capacitance arises from the inherent charge voltage relationship in the device itself More sophisticated processing can reduce the source drain depletion and extrinsic capacitances, but the intrinsic capacitances will always be present Although there are in principle 9 independent intrinsic capacitance components in the MOSFET, the most important are the gate source and gate drain capacitances, since they load a previous stage Page 2623
24 Intrinsic MOSFET Capacitance Model The detailed analysis of intrinsic capacitance involves expressing the channel charge in terms of the terminal potentials and performing the appropriate derivatives C C GS GD dq dv G GS dq dv G GD Although Q G will balance both depletion and inversion charge, inversion charge is assumed to dominate, so that the derivatives are those of the inversion charge with respect to the appropriate voltage Page 2624
25 MOSFET Intrinsic Capacitance (con t) Below threshold, no mobile charge exists, so the inversion layer charge dependent capacitances are zero In triode, the capacitances can be shown to be (note: C ox is the per unit area term multiplied by WL) C GS = 2 3 C ox 1 2 ( VGS VT ) ( V V ) GS T V V DS DS 2, C GD = 2 3 C ox ( V ) ( ) GS VT VGS VT VDS For heavy triode operation (V DS << V GS V T ) C GS C GD C ox /2 At pinchoff (V DS = V GS  V T ), C GS = 2/3C ox and C GD = 0 In saturation, the capacitances are assumed to stay at their pinchoff values Page 2625
26 MOSFET Intrinsic Capacitance (con t) The intrinsic capacitances are plotted below In the left hand plot, triode is x < 1, saturation x > 1 In the right hand plot, cutoff is x < 0, saturation 0 < x < 1, triode x > 1 The values in saturation are those at the pinchoff point C/Cox CGS CGD VDS/(VGSVT) C/Cox CGS CGD (VGSVT)/VDS Page 2626
27 Example 26.3: Intrinsic Capacitance Calculation Calculate the intrinsic gate source and gate drain capacitances for the same device as the previous examples assuming saturation operation Page 2627
28 Example 26.3: Solution For saturation (V DS >> V GS V T ) C C GS GD = = = F Page 2628
29 Summary of Example Capacitances The table below shows all capacitances calculated for the example structure For this example, the largest capacitances are associated with the source and drain sidewalls (but note these are not connected to the gate) CAPACITANCE COMPONENT VALUE (ff) Depletion (Sidewall) SB 35.5 DB 24.3 Depletion (Bottom) SB 9.5 DB 6.5 Extrinsic (Overlap) GS 1.38 GD 1.38 GB 0.22 Intrinsic (saturation) GS 16.6 GD 0 Page 2629
30 High Frequency Small Signal Equivalent Circuit If all the capacitance components are added to the low frequency small signal equivalent circuit, the resulting high frequency small signal equivalent circuit shown below is obtained Page 2630
31 Lecture Summary The low frequency MOSFET small signal behavior is determined by a transconductance and output conductance A large number of capacitive components have been identified, but they fall into only a few categories based on their physical origin Depletion capacitances associated with the bottom and sidewall of the source and drain regions (same functional model as diode/bjt) Overlap capacitances, which are simple parallel plate structures Intrinsic capacitances, based on charge/voltage relationships in the structure (similar idea to the diffusion capacitance C π in the BJT) Per unit area and per unit periphery quantities were introduced to allow absolute values to be determined for a particular device based on its geometry Page 2631
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