VLSI Design I; A. Milenkovic 1
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1 Course Administration CPE/EE 47, CPE 57 SI Design I 0: IC Manufacturing & MOS Transistor Theory Department of Electrical and Computer Engineering University of Alabama in Huntsville Aleksandar Milenkovic ( ) Instructor: Aleksandar Milenkovic milenka@ece.uah.edu EB 17 Mon. 5:0 PM 6:0 PM, Wen. 1:0 1:0 PM UR: TA: Joel Wilder abs: Accounts on Solaris machines, ab#1 next week Text: CMOS SI Design, rd ed., Weste, Harris Review: Introduction, Design Metrics, IC Fabrication (Read Chapter 1) Today: IC Fabrication (slides, Chapter ) 8/1/005 SI Design I; A. Milenkovic Review: Fundamental Design Metrics Design Abstraction evels Functionality Cost NRE (fixed) costs design effort RE (variable) costs cost of parts, assembly, test Reliability, robustness Noise margins Noise immunity Performance Speed (delay) Power consumption; energy Timetomarket in out S n SYSTEM MODUE GATE CIRCUIT DEICE G D n 8/1/005 SI Design I; A. Milenkovic 8/1/005 SI Design I; A. Milenkovic 4 The MOS Transistor Aluminum The NMOS Transistor Cross Section n areas have been doped with donor ions (arsenic) of concentration N D electrons are the majority carriers W Gate Source n Gate oxide Drain n FieldOxide (SiO ) stopper Bulk (Body) p areas have been doped with acceptor ions (boron) of concentration N A holes are the majority carriers 8/1/005 SI Design I; A. Milenkovic 5 8/1/005 SI Design I; A. Milenkovic 6 SI Design I; A. Milenkovic 1
2 Switch Model of NMOS Transistor Switch Model of PMOS Transistor GS Gate GS Gate Source (of carriers) Drain (of carriers) Source (of carriers) Drain (of carriers) Open (off) (Gate = 0 ) Closed (on) (Gate = 1 ) R on Open (off) (Gate = 1 ) Closed (on) (Gate = 0 ) R on GS < T GS > T GS > DD T GS < DD T 8/1/005 SI Design I; A. Milenkovic 7 8/1/005 SI Design I; A. Milenkovic 8 CMOS Inverter: A First ook CMOS Inverter: Steady State Response DD DD DD O = 0 OH = DD M = f(r n, R p ) R p in out out = 1 out = 0 C R n in = 0 in = DD 8/1/005 SI Design I; A. Milenkovic 9 8/1/005 SI Design I; A. Milenkovic 10 CMOS Fabrication CMOS transistors are fabricated on silicon wafer ithography process similar to printing press On each step, different materials are deposited or etched Easiest to understand by viewing both top and crosssection of wafer in a simplified manufacturing process Inverter Crosssection Typically use ptype substrate for nmos transistors Requires nwell for body of pmos transistors GND A Y DD SiO n diffusion diffusion metal1 nmos transistor pmos transistor 8/1/005 SI Design I; A. Milenkovic 11 8/1/005 SI Design I; A. Milenkovic 1 SI Design I; A. Milenkovic
3 Well and Substrate Taps Substrate must be tied to GND and nwell to DD Metal to lightlydoped semiconductor forms poor connection called Shottky Diode Use heavily doped well and substrate contacts / taps GND A Y DD Inverter Mask Set Transistors and wires are defined by masks Crosssection taken along dashed line A Y n substrate tap well tap GND substrate tap nmos transistor pmos transistor well tap DD 8/1/005 SI Design I; A. Milenkovic 1 8/1/005 SI Design I; A. Milenkovic 14 Detailed Mask iews Fabrication Steps Six masks nwell n diffusion diffusion Contact Metal n Diffusion Diffusion Contact Start with blank wafer Build inverter from the bottom up First step will be to form the nwell Cover wafer with protective layer of SiO (oxide) Remove layer where nwell should be built Implant or diffuse n dopants into exposed wafer Strip off SiO Metal 8/1/005 SI Design I; A. Milenkovic 15 8/1/005 SI Design I; A. Milenkovic 16 Oxidation Grow SiO on top of Si wafer C with H O or O in oxidation furnace Photoresist Spin on photoresist Photoresist is a lightsensitive organic polymer Softens where exposed to light Photoresist SiO SiO 8/1/005 SI Design I; A. Milenkovic 17 8/1/005 SI Design I; A. Milenkovic 18 SI Design I; A. Milenkovic
4 ithography Expose photoresist through nwell mask Strip off exposed photoresist Etch Etch oxide with hydrofluoric acid (HF) Seeps through skin and eats bone; nasty stuff!!! Only attacks oxide where resist has been exposed Photoresist SiO Photoresist SiO 8/1/005 SI Design I; A. Milenkovic 19 8/1/005 SI Design I; A. Milenkovic 0 Strip Photoresist Strip off remaining photoresist Use mixture of aci called piranah etch Necessary so resist doesn t melt in next step nwell nwell is formed with diffusion or ion implantation Diffusion Place wafer in furnace with arsenic gas Heat until As atoms diffuse into exposed Si Ion Implanatation Blast wafer with beam of As ions Ions blocked by SiO, only enter exposed Si SiO SiO 8/1/005 SI Design I; A. Milenkovic 1 8/1/005 SI Design I; A. Milenkovic Strip Oxide Strip off the remaining oxide using HF Back to bare wafer with nwell Subsequent steps involve similar series of steps Deposit very thin layer of oxide < 0 Å (67 atomic layers) Chemical apor Deposition (CD) of silicon layer Place wafer in furnace with Silane gas (SiH 4 ) Forms many small crystals called Heavily doped to be good conductor Thin oxide 8/1/005 SI Design I; A. Milenkovic 8/1/005 SI Design I; A. Milenkovic 4 SI Design I; A. Milenkovic 4
5 Patterning Use same lithography process to pattern SelfAligned Process Use oxide and masking to expose where n dopants should be diffused or implanted Ndiffusion forms nmos source, drain, and nwell contact Thin oxide 8/1/005 SI Design I; A. Milenkovic 5 8/1/005 SI Design I; A. Milenkovic 6 Ndiffusion Pattern oxide and form n regions Selfaligned process where blocks diffusion is better than metal for selfaligned s because it doesn t melt during later processing Ndiffusion cont. Historically dopants were diffused Usually ion implantation today But regions are still called diffusion n Diffusion n 8/1/005 SI Design I; A. Milenkovic 7 8/1/005 SI Design I; A. Milenkovic 8 Ndiffusion cont. Strip off oxide to complete patterning step PDiffusion Similar set of steps form diffusion regions for pmos source and drain and substrate contact Diffusion n n 8/1/005 SI Design I; A. Milenkovic 9 8/1/005 SI Design I; A. Milenkovic 0 SI Design I; A. Milenkovic 5
6 Contacts Now we need to wire together the devices Cover chip with thick field oxide Etch oxide where contact cuts are needed Metalization Sputter on aluminum over whole wafer Pattern to remove excess metal, leaving wires Metal Contact Metal n Thick field oxide n Thick field oxide 8/1/005 SI Design I; A. Milenkovic 1 8/1/005 SI Design I; A. Milenkovic ayout Chips are specified with set of masks Minimum dimensions of masks determine transistor size (and hence speed, cost, and power) Feature size f = distance between source and drain Set by minimum width of Feature size improves 0% every years or so Normalize for feature size when describing design rules Express rules in terms of λ = f/ E.g. λ = 0. µm in 0.6 µm process Simplified Design Rules Conservative rules to get you started 8/1/005 SI Design I; A. Milenkovic 8/1/005 SI Design I; A. Milenkovic 4 Inverter ayout Transistor dimensions specified as Width / ength Minimum size is 4λ / λ, sometimes called 1 unit In f = 0.6 µm process, this is 1. µm wide, 0.6 µm long Summary MOS Transistors are stack of, oxide, silicon Can be viewed as electrically controlled switches Build logic s out of switches Draw masks to specify layout of transistors Now you know everything necessary to start designing schematics and layout for a simple chip! 8/1/005 SI Design I; A. Milenkovic 5 8/1/005 SI Design I; A. Milenkovic 6 SI Design I; A. Milenkovic 6
7 Design Rules Interface between the circuit designer and process engineer Guidelines for constructing process masks Unit dimension: minimum line width scalable design rules: lambda parameter absolute dimensions: micron rules Rules constructed to ensure that design works even when small fab errors (within some tolerance) occur A complete set includes set of layers intralayer: relations between objects in the same layer interlayer: relations between objects on different layers Why Have Design Rules? To be able to tolerate some level of fabrication errors such as 1. Mask misalignment. Dust. Process parameters (e.g., lateral diffusion) 4. Rough surfaces 8/1/005 SI Design I; A. Milenkovic 7 8/1/005 SI Design I; A. Milenkovic 8 Intraayer Design Rule Origins Intraayer Design Rules Minimum dimensions (e.g., widths) of objects on each layer to maintain that object after fab minimum line width is set by the resolution of the patterning process (photolithography) Minimum spaces between objects (that are not related) on the same layer to ensure they will not short after fab micron 0. micron Well Active Select Same Potential 10 0 or 6 Different Potential 9 Contact or ia Hole Metal1 Metal 4 8/1/005 SI Design I; A. Milenkovic 9 8/1/005 SI Design I; A. Milenkovic 40 Interayer Design Rule Origins Transistor ayout 1. Transistor rules transistor formed by overlap of active and poly layers Transistors Catastrophic error Transistor 1 Unrelated Poly & Diffusion Thinner diffusion, but still working 5 8/1/005 SI Design I; A. Milenkovic 41 8/1/005 SI Design I; A. Milenkovic 4 SI Design I; A. Milenkovic 7
8 Select ayer Interayer Design Rule Origins, Con t 1 Select. Contact and via rules M1 contact to pdiffusion M1 contact to ndiffusion M1 contact to poly Contact Mask Mx contact to My ia Masks 5 both materials 0. Contact: 0.44 x 0.44 mask misaligned 0.14 Substrate Well 8/1/005 SI Design I; A. Milenkovic 4 8/1/005 SI Design I; A. Milenkovic 44 ias and Contacts CMOS Process ayers ia 1 Metal to 1 Active Contact 1 Metal to Poly Contact 4 5 Mask/ayer name nwell pwell active ndiffusion implant pdiffusion implant contact metal1 Derivation from drawn layers =nwell =pwell =pdiffndiff =poly =grow(ndiff) =grow(pdiff) =contact =m1 Alternative names for mask/layer bulk, substrate, tub, ntub, moat bulk, substrate, tub, ptub, moat thin oxide, thinox, island, oxide poly, ndiff, nselect, nplus, n pdiff, pselect, pplus, contact cut, poly contact, diffusion contact firstlevel metal MOSIS mask label CWN CWP CAA CPG CSN CSP CCP and CCA CMF metal via metal =m =via =m secondlevel metal metal/metal via thirdlevel metal CMS CS CMT glass =glass passivation, overglass, pad COG 8/1/005 SI Design I; A. Milenkovic 45 8/1/005 SI Design I; A. Milenkovic 46 Outline CMOS Transistor Theory Introduction MOS Capacitor nmos I Characteristics pmos I Characteristics Gate and Diffusion Capacitance Pass Transistors RC Delay Models 8/1/005 SI Design I; A. Milenkovic 48 SI Design I; A. Milenkovic 8
9 Introduction So far, we have treated transistors as ideal switches An ON transistor passes a finite amount of current Depen on terminal voltages Derive currentvoltage (I) relationships Transistor, source, drain all have capacitance I = C ( / t) > t = (C/I) Capacitance and current determine speed Also explore what a degraded level really means MOS Capacitor Gate and body form MOS capacitor Operating modes Accumulation g < 0 Depletion (a) Inversion (b) silicon dioxide insulator 0 < g < t depletion region g > t inversion region depletion region (c) 8/1/005 SI Design I; A. Milenkovic 49 8/1/005 SI Design I; A. Milenkovic 50 Terminal oltages nmos Cutoff Mode of operation depen on g, d, s gs = g s g gd = g d = d s = gs gd gs gd s Source and drain are symmetric diffusion terminals d By convention, source is terminal at lower voltage Hence 0 nmos body is grounded. First assume source is 0 too. Three regions of operation Cutoff inear Saturation No channel I = 0 gs = 0 s b g gd d 8/1/005 SI Design I; A. Milenkovic 51 8/1/005 SI Design I; A. Milenkovic 5 nmos inear Channel forms Current flows from d to s e from s to d I increases with Similar to linear resistor gs > t s gs > t s g b g gd = gs d = 0 gs > gd > t d I 0 < < gs t nmos Saturation Channel pinches off I independent of We say current saturates Similar to current source gs > t s g b gd < t d I > gs t b 8/1/005 SI Design I; A. Milenkovic 5 8/1/005 SI Design I; A. Milenkovic 54 SI Design I; A. Milenkovic 9
10 I Characteristics In inear region, I depen on How much charge is in the channel? How fast is the charge moving? Channel Charge MOS structure looks like parallel plate capacitor while operating in inversion Gate oxide channel Q channel = t ox W SiO oxide (good insulator, ε ox =.9) g source gs C g gd drain s channel d n n 8/1/005 SI Design I; A. Milenkovic 55 8/1/005 SI Design I; A. Milenkovic 56 Channel Charge MOS structure looks like parallel plate capacitor while operating in inversion Gate oxide channel Q channel = C C = t ox W SiO oxide (good insulator, ε ox =.9) g source C g gd drain gs s channel d n n Channel Charge MOS structure looks like parallel plate capacitor while operating in inversion Gate oxide channel Q channel = C C = C g = ε ox W/t ox = C ox W C ox = ε ox / t ox = t ox W SiO oxide (good insulator, ε ox =.9) g source C g gd drain gs s channel d n n 8/1/005 SI Design I; A. Milenkovic 57 8/1/005 SI Design I; A. Milenkovic 58 Channel Charge MOS structure looks like parallel plate capacitor while operating in inversion Gate oxide channel Q channel = C C = C g = ε ox W/t ox = C ox W C ox = ε ox / t ox = gc t = ( gs /) t t ox W SiO oxide (good insulator, ε ox =.9) g source C g gd drain gs s channel d n n Carrier velocity Charge is carried by e Carrier velocity v proportional to lateral Efield between source and drain v = 8/1/005 SI Design I; A. Milenkovic 59 8/1/005 SI Design I; A. Milenkovic 60 SI Design I; A. Milenkovic 10
11 Carrier velocity Charge is carried by e Carrier velocity v proportional to lateral Efield between source and drain v = µe µ called mobility E = Carrier velocity Charge is carried by e Carrier velocity v proportional to lateral Efield between source and drain v = µe µ called mobility E = / Time for carrier to cross channel: t = 8/1/005 SI Design I; A. Milenkovic 61 8/1/005 SI Design I; A. Milenkovic 6 Carrier velocity Charge is carried by e Carrier velocity v proportional to lateral Efield between source and drain v = µe µ called mobility E = / Time for carrier to cross channel: t = / v nmos inear I Now we know How much charge Q channel is in the channel How much time t each carrier takes to cross I = 8/1/005 SI Design I; A. Milenkovic 6 8/1/005 SI Design I; A. Milenkovic 64 nmos inear I Now we know How much charge Q channel is in the channel How much time t each carrier takes to cross nmos inear I Now we know How much charge Q channel is in the channel How much time t each carrier takes to cross I Q = t = channel I Qchannel = t W = µ C = β gs t ox gs t W β = µcox 8/1/005 SI Design I; A. Milenkovic 65 8/1/005 SI Design I; A. Milenkovic 66 SI Design I; A. Milenkovic 11
12 nmos Saturation I If gd < t, channel pinches off near drain When > at = gs t Now drain voltage no longer increases current nmos Saturation I If gd < t, channel pinches off near drain When > at = gs t Now drain voltage no longer increases current I = I = β at gs t at 8/1/005 SI Design I; A. Milenkovic 67 8/1/005 SI Design I; A. Milenkovic 68 nmos Saturation I nmos I Summary If gd < t, channel pinches off near drain When > at = gs t Now drain voltage no longer increases current I = β at β = ( ) gs t gs t at Shockley 1 st order transistor models 0 gs < t I = β < β ( ) > gs t at gs t at cutoff linear saturation 8/1/005 SI Design I; A. Milenkovic 69 8/1/005 SI Design I; A. Milenkovic 70 For a 0.6 µm process From AMI Semiconductor t ox = 100 Å µ = 50 cm /*s t = 0.7 Plot I vs. gs = 0, 1,,, 4, 5 Use W/ = 4/ λ Example 14 W W W β = µ Cox = ( 50) 10 µ A/ = I (ma) gs = gs = 5 gs = 4 gs = gs = pmos I All dopings and voltages are inverted for pmos Mobility µ p is determined by holes Typically x lower than that of electrons µ n 10 cm /*s in AMI 0.6 µm process Thus pmos must be wider to provide same current In this class, assume µ n / µ p = *** plot I here 8/1/005 SI Design I; A. Milenkovic 71 8/1/005 SI Design I; A. Milenkovic 7 SI Design I; A. Milenkovic 1
13 Capacitance Any two conductors separated by an insulator have capacitance Gate to channel capacitor is very important Creates channel charge necessary for operation Source and drain have capacitance to body Across reversebiased diodes Called diffusion capacitance because it is associated with source/drain diffusion Gate Capacitance Approximate channel as connected to source C gs = ε ox W/t ox = C ox W = C permicron W C permicron is typically about ff/µm t ox n n W SiO oxide (good insulator, ε ox =.9ε 0 ) 8/1/005 SI Design I; A. Milenkovic 7 8/1/005 SI Design I; A. Milenkovic 74 Diffusion Capacitance C sb, C db Undesirable, called parasitic capacitance Capacitance depen on area and perimeter Use small diffusion nodes Comparable to C g for contacted diff ½ C g for uncontacted aries with process 8/1/005 SI Design I; A. Milenkovic 75 SI Design I; A. Milenkovic 1
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