Lecture 7 MOS Capacitor

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1 EE 471: Transport Phenomena in Solid State Devices Spring 2018 Lecture 7 MOS Capacitor Bryan Ackland Department of Electrical and Computer Engineering Stevens Institute of Technology Hoboken, NJ Adapted from Modern Semiconductor Devices for Integrated Circuits, Chenming Hu,

2 MOS Metal-Oxide-Semiconductor V g V g metal SiO 2 gate metal SiO 2 N + N + gate Si body P body MOS capacitor MOS transistor Gate oxide film can be as thin as 1.5nm After 1970, gate usually made from heavily doped polysilicon Trend today is to return to metal gates 2

3 MOS Capacitor - Energy Band Diagram Three different materials: N+ poly SiO 2 P-body χχ SSSSSS2 = 0.95 ev Vacuum level E 0 E c χχ SSSS = 4.05 ev E c, E F E v E g 1.1ev E g 9ev E g 1.1ev E c E F E v E v 3

4 MOS Capacitor Thermal Equilibrium (V g =0) What happens when we bring these materials together? N+ poly SiO 2 P-body E 0 E c, E F E v 3.1 ev 4.8 ev 9 ev 3.1 ev 4.8 ev E c E F E v Potential difference between N + gate and P body at zero bias analogous to built-in voltage of PN junction 4

5 Flat Band Condition Necessary to apply small negative voltage V fb on gate to make energy bands flat at oxide surface E 0 N+ poly SiO 2 P-body 0.95 ev 3.1 ev E c, E Fn E v q.v fb 9 ev E c E Fp E v 4.8 ev Flat-band voltage VV ffff is equal to difference in Quasi-Fermi levels between two terminals under flat-band conditions For heavily doped N+ gate: VV ffff EE FFpp EE cc qq = (EE FFpp EE vv EE gg )/qq 5

6 Surface Accumulation What happens if we take VV gg < VV ffff? Band diagram on gate side pushed upward EE cc on body side bends up towards oxide surface Surface potential ss is a measure of amount of band bending note that ss is negative if band bend upwards VV oooo is potential across the oxide also negative in accumulation VV gg is the potential of gate relative to the body N+ poly SiO 2 P-body VV gg = VV ffff + ss + VV oooo In flat-band, ss = VV oooo = 0 6

7 Charge Accumulation Negative voltage on gate attracts majority holes to surface Because EE vv is closer to EE FF at surface (compared to bulk), surface concentration is higher then pp 0 qq pp ss = NN aa. ee ss kkkk ss = kkkk qq. llll pp ss NN aa If ss = 100 mmmm, pp ss 50 NN aa If ss = 200 mmmm, pp ss 2200 NN aa In accumulation, ss is small and can be ignored in a first order model which gives: VV oooo = VV gg VV ffff 7

8 Accumulation Capacitance Gauss s Law: EE oooo = QQ aaaaaa εε oooo VV oooo = EE oooo. TT oooo = QQ aaaaaa. TT oooo εε oooo = QQ aaaaaa QQ aaaaaa = VV gg VV ffff MOS capacitor in accumulation behaves like regular capacitor with (QQ = CC. VV) but with a shift in V by VV ffff negative sign because voltage is measured at gate while charge is measured on body More generally: VV oooo = QQ bbbbbb QQ aaaaaa is accumulated charge per unit area (C/cm 2 ) TT oooo is oxide thickness (cm) is oxide capacitance per unit area (F/cm 2 ) where QQ bbbbbb is total charge in body (including QQ aaaaaa ) 8

9 Surface Depletion What happens if we take VV gg > VV ffff? Band diagram on gate side pulled downward EE cc on body side bends down towards oxide surface More positive voltage on gate repels majority holes from surface Because EE FF is now far from EE cc and EE vv at surface, electron and hole densities are both small. There is now a depletion region at the surface with residual negative charge due to uncompensated acceptor ions N+ poly SiO 2 P-body 9

10 Depletion Width VV oooo = QQ bbbbbb = QQ dddddd = qq. NN aa. WW dddddd Using Poisson s eqn. as we did with reverse biased PN junction: WW dddddd = 2εε ss. ss qq. NN aa which gives: VV oooo = 2qq. NN aa. εε ss. ss and ss = qq. NN 2 aa. WW dddddd 2εε ss 10

11 Charge Depletion As VV gg increases, hole concentration at surface decreases as electron concentration at surface increases qq pp ss = NN aa. ee ss kkkk +qq ss kkkk nn ss = nn ii 2. ee NN aa In depletion, ss is no longer negligible can solve following quadratics to yield ss or WW dddddd as a function of VV gg VV gg = VV ffff + ss + VV oooo = VV ffff + ss + 2qq. NN aa. εε ss. ss VV gg = VV ffff + qq. NN 2 aa. WW dddddd 2εε ss + qq. NN aa. WW dddddd 11

12 Surface Inversion What happens if we make VV gg increasingly more positive? pp ss continues to decrease N+ poly SiO 2 P-body nn ss continues to increase At some point, surface changes from P-type to N-type this is called inversion Threshold of inversion is defined as that condition in which surface electron concentration becomes equal to bulk hole concentration nn ss = NN aa EE cc EE FF ssssssssssssss = EE FF EE vv bbbbbbbb i.e., AA = BB which implies CC = DD in figure 12

13 Threshold Condition Surface potential at threshold ssss = CC + DD qq = 2CC qq N+ poly SiO 2 P-body = 2 BB where qq. BB EE gg 2 EE FF EE vv bbbbbbbb BB is sometimes called bulk potential Assuming NN cc NN vv, qq. BB = kkkk. llll NN vv nn ii kkkk. llll NN vv NN aa so, BB = kkkk qq. llll NN aa nn ii ssss = 2 BB = 2. kkkk qq. ln NN aa nn ii 13

14 Threshold Voltage Substituting: VV gg = VV ffff + ss + VV oooo VV oooo = 2qq. NN aa. εε ss. ss and ss = ssss = 2 BB VV tt = VV gg at threshold = VV ffff + 2 BB + 2. qq. NN aa. εε ss. BB For N-type body: VV tt = VV ffff 2 BB 2. BB = kkkk qq llll NN dd nn ii qq. NN dd. εε ss. BB and (nnnnnnnn ttttttt BB iiii aaaaaaaaaaaa pppppppppppppppp) ssss = 2 BB 14

15 Threshold Voltage vs. Body Doping VV tt = VV ffff ± 2 BB ± 2. qq. NN bbbbbbbb. εε ss. BB + for P-body for N-body 15

16 Strong Inversion If we increase VV gg beyond VV tt... There is now an inversion layer filled with inversion electrons Surface electron concentration increases dramatically with small increase in ss qq nn ss = NN aa. ee ss 2 BB kkkk N+ poly SiO 2 P-body Again, to a first order, ss does not increase significantly beyond 2 BB Which implies depletion width has reached its maximum value WW dddddddd = 2. εε ss. BB qq. NN aa 16

17 Strong Inversion Charge QQ iiiiii is inversion charge density (C/cm 2 ) = VV ffff + 2 BB QQ dddddd_mmmmmm QQ iiiiii i.e., = VV tt QQ iiiiii QQ iiiiii = VV gg VV tt P-Si body MOS capacitor in strong inversion behaves as a capacitor with a voltage offset of VV tt Where do all these electrons come from? 17

18 MOS Transistor in Strong Inversion In MOS capacitor, inversion electrons generated thermally can take many seconds in modern high quality silicon processes In MOS transistor, electrons rapidly supplied by N + source V g > V t V g > V t N+ gate SiO 2 N + N + P body N+ gate SiO 2 N N + N + P body 18

19 Example: MOS Capacitor Consider an ideal MOS capacitor fabricated on a P-type silicon substrate with a doping of cccc 3 with an oxide thickness of 10nnnn and an N + poly gate. Determine: a) Bulk potential BB b) Flat-band voltage VV ffff of this capacitor c) Oxide capacitance per unit area d) Threshold voltage VV tt e) Maximum depletion width WW dddddddd f) What would be the threshold if the poly gate were changed to heavy P + doping? 19

20 Gate Doping and Threshold Voltage P-body transistor normally operates in an IC with signal voltages that range from zero (ground) to some positive supply (V DD ) VV tt is normally set to a small positive voltage (e.g., 0.4V) so that the transistor does not have an inversion layer at VV gg = 0VV A transistor that does not conduct at VV gggg = 0 is known as an enhancement mode transistor P + gate is not normally used with P-body device as it would raise threshold voltage too high (> 1V) N-body device is paired with P+ gate to give small negative VV tt N+ gate P+ gate SiO 2 SiO 2 N + N + P + P + V DD P body N body V DD 20

is inverted and ss = 2 BB ss 2 BB in inversion region WW dddddd increases as the

21 MOS Substrate Charge - Review ss is zero at VV ffff and near zero in accumulation region As VV gg increases above VV ffff, ss increases until surface is inverted and ss = 2 BB ss 2 BB in inversion region WW dddddd increases as the square root of the surface potential At VV gg = VV tt, WW dddddd reaches its maximum value 21

22 Substrate Charge Components QQ dddddd = qq. NN aa. WW dddddd QQ iiiiii = VV gg VV tt QQ aaaaaa = VV gg VV ffff 22

23 Total Substrate Charge QQ bbbbbb = QQ aaaaaa + QQ dddddd + QQ iiiiii QQ bbbbbb CC ddqq gg ddvv gg = ddqq bbbbbb ddvv gg 23

24 MOS C-V Characteristics CC ddqq gg ddvv gg = ddqq ssssss ddvv gg In depletion regime, C consists of two capacitors and CC dddddd in series: 1 CC dddddd = εε ss CC = CC and dddddd WW dddddd Substituting for WW dddddd : 1 CC = VV gg VV ffff qq. NN aa. εε ss 24

25 MOS Capacitor C-V vs MOS Transistor C-V At high frequencies, MOS capacitor cannot (thermally) generate electrons fast enough to produce an inversion layer consistent with applied voltage VV gg so for VV gg > VV tt, C remains at maximum depletion value In modern processes, high frequencies (in this context) may mean more than a few hertz! MOS Transistor has a good supply of electrons from nearby N + source region LF MOS capacitor C-V MOS transistor C-V at any frequency HF MOS capacitor C-V 25

26 Example: Capacitance Values A 10 μμμμ 10 μμμμ MOS capacitor is built with a N + poly gate on a P-type substrate with NN aa = cccc 3 and a gate oxide thickness of 50 nnnn. What are the high and low frequency capacitances of the MOS capacitor when biased in strong inversion? 26

27 Second Order Effects So far, have ignored possibility of electric charge in oxide fixed charge due to silicon ions at Si-SiO 2 interface mobile charge due to impurities in oxide sodium is a serious potential contaminant Oxide charge shifts flat-band voltage VV ffff EE FF EE cc qq QQ oooo This, in turn, shifts threshold voltage very serious in low voltage processes So far, have assumed accumulation and inversion layers to be zero width Quantum solution of Poisson s eqn. at SiO 2 interface yields finite layer thickness ~ 5-15 A Effectively locates charge below interface by TT iiiiii Reduces C in accumulation and inversion domains 27 Reduces transistor performance with thin gate oxides (<10nm)

28 Polysilicon Gate Depletion So far, we have ignored any band bending in N + poly gate poly is heavily doped but there will be small surface potential pppppppp when body is biased into inversion Creates a thin depletion layer in poly at SiO 2 interface Gauss s Law gives: WW dddddddddd = εε oooo. EE oooo qq. NN pppppppp WW dddddddddd may be 1-2 nm Solving Poisson's Equation: EE cc, EE FF EE vv N + poly gate qq. pppppppp SiO 2 P body EE cc EE FF EE vv pppppppp = qq. NN pppppppp. WW dddddddddd 2 2. εε ss WW dddddddddd Summing potentials across interface: VV gg = VV ffff + ssss + VV oooo pppppppp 28

29 Effects of Polysilicon Gate Depletion Gate Depletion decreases gate capacitance: CC = CC pppppppp 1 = TT oooo εε oooo + WW dddddddddd εε ss 1 N + poly gate EE cc EE FF EE vv = εε oooo TT oooo + WW dddddddddd 3 qq. pppppppp EE cc, EE FF SiO 2 P body Also, effectively reduces gate voltage: EE vv WW dddddddddd QQ iiiiii = VV gg pppppppp VV tt 29

30 Effective Oxide Capacitance Effective oxide thickness: TT oooooo = TT oooo + WW dddddddddd 3 + TT iiiiii 3 Effective oxide capacitance: oo = εε oooo TT oooooo QQ iiiiii = oo VV gg VV tt Poly depletion can be eliminated with metal gate 30

31 Example: Poly Gate Depletion Assume that VV oooo, the voltage across a 2nm thin oxide is 1V. The N + poly-gate doping is NN pppppppp = cccc 3 and substrate NN aa = cccc 3. Assuming that channel is inverted, estimate: a) WW dddddddddd b) pppppppp c) VV gg 31

32 CCD Imager In CMOS imager, photodiode is used as photo-detector and CMOS circuitry is used to convert charge to voltage and amplify and transmit that voltage to output circuits In CCD imager, MOS capacitor is used both as a photodetector and a charge transfer device to move photocharge from pixel to output circuits Suppose a voltage VV gg > VV tt is suddenly applied to gate of a MOS capacitor Thermal generation is slow for a period of time there are no inversion electrons. bands bend beyond 2 BB depletion region extends beyond WW dddddddd Known as deep depletion 32

33 CCD Photodetector hν V g > V t P body SiO 2 If light shines on MOS capacitor in deep depletion, photons pass through thin poly gate and generate electron-hole pairs in depletion region Photo-generated holes drift into substrate and are removed through substrate contact Photo-generated electrons drift towards gate and are collected at oxide surface Number of electrons collected proportional to light intensity 33

CCD Charge Transport Once electrons are collected under a MOS gate, they can be passed along a row of adjacent gates with suitably timed multiphase clocks Every third gate

34 CCD Charge Transport Once electrons are collected under a MOS gate, they can be passed along a row of adjacent gates with suitably timed multiphase clocks Every third gate functions as a photo-detector At end of exposure time, charges are passed along row toward output circuits Overlapping poly gates ensure high charge transfer efficiency 34

35 2-D CCD Imager 2-D array of charge packets are read row by row 35

Choice of V t and Gate Doping Type

Choice of V t and Gate Doping Type To make circuit design easier, it is routine to set V t at a small positive value, e.g., 0.4 V, so that, at V g = 0, the transistor does not have an inversion layer and