Lecture 310 Open-Loop Comparators (3/28/10) Page 310-1

Transcription

1 Lecture 310 Open-Loop Comparators (3/28/10) Page LECTURE 310 OPEN-LOOP COMPARATORS LECTURE ORGANIZATION Outline Characterization of comparators Dominant pole, open-loop comparators Two-pole, open-loop comparators Summary CMOS Analog Circuit Design, 2 nd Edition Reference Pages Lecture 310 Open-Loop Comparators (3/28/10) Page CHARACTERIZATION OF COMPARATORS What is a Comparator? The comparator is a circuit that compares one analog signal with another analog signal or a reference voltage and outputs a binary signal based on the comparison. The comparator is basically a 1-bit analog-to-digital converter: Analog Input Reference Voltage 1-Bit Quantizer 1-Bit ADC 1-Bit Encoder 1-Bit Digital Output Analog Input 1 Analog Input 2 Comparator 1-Bit Quantizer 1-Bit Encoder Comparator symbol: v P v N - v O Fig

2 Lecture 310 Open-Loop Comparators (3/28/10) Page Noninverting and Inverting Comparators The comparator output is binary with the two-level outputs defined as, V OH = the high output of the comparator V OL = the low level output of the comparator Voltage transfer function of a Noninverting and Inverting Comparator: v o V OH V OH v o V OL Noninverting Comparator v P -v N V OL v P -v N Inverting Comparator Fig A Lecture 310 Open-Loop Comparators (3/28/10) Page Infinite Gain Comparator Voltage transfer function curve: v o V OH v P -v N V OL Fig Model: v P v N v P -v N f 0 (v P -v N ) v O - - Comparator V OH for (v P -v N ) > 0 f 0 (v P -v N ) = V OL for (v P -v N ) < 0 Fig Gain = Av = lim VOH-VOL V0 V where V is the input voltage change

3 Lecture 310 Open-Loop Comparators (3/28/10) Page Finite Gain Comparator Voltage transfer curve: v o V OH V IL V IH v P -v N V OL Fig where for a noninverting comparator, V IH = smallest input voltage at which the output voltage is V OH V IL = largest input voltage at which the output voltage is V OL Model: v P v N f 1 (v P -v N ) = v P -v N f 1 (v P -v N ) v O - - Comparator V OH for (v P -v N ) > V IH A v (v P- v N ) for V IL < (v P -v N )<V IH V OL for (v P -v N ) < V IL Fig The voltage gain is A v = V OHV OL V IH V IL Lecture 310 Open-Loop Comparators (3/28/10) Page Input Offset Voltage of a Comparator Voltage transfer curve: v o V OS V OH V IL V IH v P -v N V OL Fig V OS = the input voltage necessary to make the output equal V OHV OL 2 when v P = v N. Model: v P v P ' ±V OS v P'-v N' f 1 (v P '-v N ') v O - - v N v N ' Comparator Fig Other aspects of the model: ICMR = input common mode voltage range (all transistors remain in saturation) R in = input differential resistance R icm = common mode input resistance

4 Lecture 310 Open-Loop Comparators (3/28/10) Page Comparator Noise Noise of a comparator is modeled as if the comparator were biased in the transition region. v o Rms Noise V OH v P -v N V OL Transition Uncertainty Fig Noise leads to an uncertainty in the transition region causing jitter or phase noise. Lecture 310 Open-Loop Comparators (3/28/10) Page Input Common Mode Range Because the input is analog and normally differential, the input common mode range of the comparator is also important. Input common mode range (ICMR): ICMR = the voltage range over which the input common-mode signal can vary without influence the differential performance As we have seen before, the ICMR is defined by the common-mode voltage range over which all MOSFETs remain in the saturation region.

5 Lecture 310 Open-Loop Comparators (3/28/10) Page Propagation Delay Time Rising propagation delay time: v o V OH v o = V OHV OL 2 t V OL v i = v P -v N V IH V IL t pr v i = V IHV IL 2 t pf t Propagation delay time = RisingpropagationdelaytimeFallingpropagationdelaytime 2 = t prt pf 2 Lecture 310 Open-Loop Comparators (3/28/10) Page Linear Frequency Response Dominant Single-Pole Model: A v (s) = A v(0) s = A v(0) s c 1 c 1 where A v (0) = dc voltage gain of the comparator c = 1 c = -3dB frequency of the comparator or the magnitude of the pole Step Response: v o (t) = A v (0) [1 - e-t/c]v in where V in = the magnitude of the step input. Maximum slope of the step response: dv o (t) dt = A v(0) c e -t/ cv in The maximum slope occurs at t = 0 giving, dv o (t) dt t=0 = A v(0) c V in

6 Lecture 310 Open-Loop Comparators (3/28/10) Page Propagation Time Delay The rising propagation time delay for a single-pole comparator is: V OH -V OL 1 2 = A v (0) [1 - e-t p /c]v in t p = c ln 1- V OH-V OL 2A v (0)V in Define the minimum input voltage to the comparator as, V in (min) = V OH-V OL 1 A v (0) t p = c ln 1- V in(min) 2V in Define k as the ratio, V in, to the minimum input voltage, V in (min), V in k = V in (min) t p = c ln 2k 2k-1 Thus, if k = 1, t p = 0.693c. Illustration: v out V in > V in (min) V Obviously, the more overdrive OH v applied to the input, the smaller in v out V OH V OL the propagation delay time. - 2 V V OL in = V in (min) 0 t 0 t p t p (max) Fig Lecture 310 Open-Loop Comparators (3/28/10) Page Dynamic Characteristics - Slew Rate of a Comparator If the rate of rise or fall of a comparator becomes large, the dynamics may be limited by the slew rate. Slew rate comes from the relationship, i = C dv dt where i is the current through a capacitor and v is the voltage across it. If the current becomes limited, then the voltage rate becomes limited. Therefore for a comparator that is slew rate limited we have, t p = T = V SR = V OH-V OL 2 SR where SR = slew rate of the comparator. If SR < maximum slope, then the comparator is slewing.

7 Lecture 310 Open-Loop Comparators (3/28/10) Page Example Propagation Delay Time of a Comparator Find the propagation delay time of an open loop comparator that has a dominant pole at 10 3 radians/sec, a dc gain of 10 4, a slew rate of 1V/μs, and a binary output voltage swing of 1V. Assume the applied input voltage is 10mV. Solution The input resolution for this comparator is 1V/10 4 or 0.1mV. Therefore, the 10mV input is 100 times larger than v in (min) giving a k of 100. Therefore, we get t p = ln = 10-3 ln = 5.01μs For slew rate considerations, we get Maximum slope = mV = 10 5 V/sec. = 0.1V/μs. Therefore, the propagation delay time for this case is limited by the linear response and is 5.01μs. Lecture 310 Open-Loop Comparators (3/28/10) Page DOMINANT POLE, OPEN-LOOP COMPARATORS Dominant Pole Comparators Any of the self-compensated op amps provide a straight-forward implementation of an open loop comparator without any modification. The previous characterization gives the relationships for: 1.) The static characteristics Gain Input offset Noise 2.) The dynamic characteristics Linear frequency response Slew rate response

8 Lecture 310 Open-Loop Comparators (3/28/10) Page Single-Stage Dominant Pole Comparator M3 V DD M4 V PBias2 MC3 MC4 v o v p MC1 M1 - C L MC2 M2 v V n Bias M5 V NBias1 - Gain g 2 m r 2 ds Slew rate = I 5 /C L Dominant pole = -1/(R out C L ) = -1/(g m r 2 ds C L ) Lecture 310 Open-Loop Comparators (3/28/10) Page Folded-Cascode Comparator V DD V PB1 M4 M5 V PB2 v P vn M1 M2 M8 M6 M7 V NB2 M9 v OUT C L V NB1 M3 I3 M10 M11 Gain g 2 m r 2 ds Slew rate = I 3 /C L Dominant pole = -1/(R out C L ) -1/(g m r 2 ds C L ) Slightly improved ICMR

9 Lecture 310 Open-Loop Comparators (3/28/10) Page Enhanced-Gain, Folded-Cascode Comparator V DD M10 V PB1 M3 v P -A M8 v N M1 M2 M6 -A -A M11 M9 v OUT M7 C L V NB1 M4 M5 Gain g m1 R out R out [Ar ds7 g m7 (r ds1 r ds5 )] (Ar ds9 g m9 r ds11 ) Slew rate = I 3 /C L Dominant pole = -1/(R out C L ) Lecture 310 Open-Loop Comparators (3/28/10) Page TWO-POLE, OPEN-LOOP COMPARATORS Two-Stage Comparator The two-stage op amp without compensation is an excellent implementation of a high-gain, open-loop comparator. V DD M3 M4 M6 v n v p M1 M2 V NB1 - M5 M7 v out C L Much faster linear response the two poles of the comparator are typically much larger than the dominant pole of the self-compensated type of comparator. Be careful not to close the loop because the amplifier is uncompensated. Slew rate: SR- = I 7 C II and SR = I 6-I7 CII

10 Lecture 310 Open-Loop Comparators (3/28/10) Page Performance of the Two-Stage, Open-Loop Comparator We know the performance should be similar to the uncompensated two-stage op amp. Emphasis on comparator performance: Maximum output voltage V OH = V DD - (V DD -V G6 (min)- V TP ) 8I (V DD -V G6 (min)- V TP ) 2 Minimum output voltage V OL = V SS Small-signal voltage gain Av(0) = g m1 g m6 g ds2 g ds4 g ds6 g ds7 Poles Input: Output: p 1 = -(g ds2g ds4 ) C I p 2 = -(g ds6g ds7 ) C II Frequency response Av(0) Av(s) = s p1-1 s p2-1 Lecture 310 Open-Loop Comparators (3/28/10) Page Example Performance of a Two-Stage Comparator Evaluate V OH, V OL, A v (0), V in (min), p 1, p 2, for the two-stage comparator shown. The large signal model parameters are K N = 110μA/V 2, K P = 50μA/V 2, V TN = V TP = 0.7V, N = 0.04V -1 and P = 0.05V -1. Assume that the minimum value of V G6 = 0V and that C I = 0.2pF and C II = 5pF. Solution Using the above relations, we find that V OH = ( ) x10-6 = 2.2V 50x ( )2 V OL is -2.5V. The gain can be found as A v (0) = Therefore, the input resolution is V in (min) = (V OH -V OL /A v (0) = 4.7V/7,696 = 0.611mV Next, we find the poles of the comparator, p 1 and p 2. p 1 = -(g ds2 g ds4 )/C I = 15x10-6 ( )/0.2x10-12 = -6.75x10 6 (1.074MHz) and p 2 = -(g ds6 g ds7 )/C II ) =(95x10-6 )( )/5x10-12 = -1.71x10 6 (0.272MHz) 30µA 4.5µm 1µm - v in M8 15µm 1µm M1 M3 3µm 1µm M5 V DD = 2.5V M4 15µm 1µm 3µm 1µm 30µA 4.5µm 1µm M2 V SS = -2.5V C I = 0.2pF M6 95µA M7 94µm 1µm 14µm 1µm v out C II = 5p

11 Lecture 310 Open-Loop Comparators (3/28/10) Page Linear Step Response of the Two-Stage Comparator The step response of a circuit with two real poles (p 1 p 2 ) is, v out (t) = A v (0)V in 1 p 2e tp 1 Normalizing gives, p 1 -p - p 1e tp 2 2 p 1 -p 2 v out (t n ) = v out(t) A v (0)V in = 1 - m m-1 e-t n 1 m-1 e-mt n where m = p 2 p 1 1 and t n = -tp 1 If p 1 = p 2 (m =1), then Normalized Output Voltage m = 4 m = 2 v out (t n ) = 1 - e tp 1 tp 1 e tp 1 = 1 - e -t n - t n e -t n m = 1 m = 0.5 m = p 2 p 1 m = Normalized Time (t n = -tp1 ) Fig Lecture 310 Open-Loop Comparators (3/28/10) Page Linear Step Response of the Two-Stage Comparator - Continued The above results are valid as long as the slope of the linear response does not exceed the slew rate. Slope at t = 0 is zero Maximum slope occurs at (m 1) t n (max) = ln(m) m-1 and is dv out (t n (max)) dt n = m m-1 exp -ln(m) m-1 -exp -m ln(m) m-1 For the two-stage comparator using NMOS input transistors, the slew rate is SR- = I 7 C II SR = I 6-I7 CII = 0.5 6(VDD-VG6(min)- VTP )2-I7 CII

12 Lecture 310 Open-Loop Comparators (3/28/10) Page Example Step Response of Ex Find the maximum slope of Ex and the time it occurs if the magnitude of the input step is v in (min). If the dc bias current in M7 is 100μA, at what value of load capacitance, C L would the transient response become slew limited? If the magnitude of the input step is 100v in (min), what is the new value of C L at which slewing would occur? Solution The poles of the comparator were given in Ex as p 1 = -6.75x106 rads/sec. and p 2 = -1.71x10 6 rads/sec. This gives a value of m = From the previous expressions, the maximum slope occurs at t n (max) = 1.84 secs. Dividing by p 1 gives t(max) = 0.272μs. The slope of the transient response at this time is found as dv out (t n (max)) dt n = [exp(-1.84) - exp( )] = V/sec Multiplying the above by p 1 gives dv out (t(max))/dt = 1.072V/μs. If the slew rate is less than 1.072V/μs, the transient response will experience slewing. Therefore, if C L 100μA/1.072V/μs or 93.3pF, the comparator will slew. If the input is 100v in (min), then we must unnormalize the output slope as follows. dv out (t(max)) v in dt = dv out (t(max)) v in (min) dt = V/μs = 107.2V/μs Therefore, the comparator will slew with a load capacitance greater than 0.933pF. Lecture 310 Open-Loop Comparators (3/28/10) Page Propagation Delay Time (Non-Slew) To find t p, we want to set 0.5(V OH -V OL ) equal to v out (t n ). However, v out (t n ) given as v out (t n ) = A v (0)V in 1- m m-1 e-t n 1 m-1 e-mt n can t be easily solved so approximate the step response as a power series to get v out (t n ) A v (0)V in 1- m m-1 1-t n t n 2 2 Therefore, set v out (t n ) = 0.5(V OH -V OL ) V OH -V OL 2 mt pn 2 A v (0)V in 2 or V OH -V OL V in (min) 1 t pn ma v (0)V in = mv in = mk This approximation is particularly good for large values of k. 1 m-1 1-mt n m2 t 2 n 2 mt n 2 A v (0)V in 2

13 Lecture 310 Open-Loop Comparators (3/28/10) Page Example Propagation Delay Time of a Two-Pole Comparator (Non-Slew) Find the propagation time delay of Ex if V in = 10mV, 100mV and 1V. Solution From Ex we know that Vin(min) = 0.611mV and m = For Vin = 10mV, k = which gives tpn The propagation time delay is equal to 0.491/6.75x106 or 72.9nS. This corresponds well with the figure shown where the normalized propagation time delay is the time at which the amplitude is 1/2k or which corresponds to tpn of approximately 0.5. Similarly, for Vin = 100mV and 1V we get a propagation time delay of 23ns and 7.3ns, respectively. Normalized Output Voltage m = 4 m = 2 m = 1 m = 0.5 m = p 2 p 1 m = = k Normalized Time (t n = tp1 = t/τ 1 ) tp = x10 6 = 77ns Fig A Lecture 310 Open-Loop Comparators (3/28/10) Page Initial Operating States for the Two-Stage, Open-Loop Comparator What are the initial operating states for the two-stage, open-loop comparator? The following table summarizes the results for the two-stage, open-loop comparator shown. Conditions Initial State of vo1 Initial State of vout v G1 >V G2, i 1 <I SS and i 2 >0 V DD -V SD4 (sat) < v o1 < V DD V SS v G1 >>V G2, i 1 =I SS and i 2 =0 V DD V SS vg1<vg2, i1>0 and i2<iss vo1=vg2-vgs2,act(iss/2), VSS if M5 act. VOH see equation below tabl vg1<<vg2, i1>0 and i2<iss VSS VOH see equation below tabl vg2>vg1, i1>0 and i2<iss VS2(ISS/2)<vo1<VS2(ISS/2)VDS2(sat) VOH see equation below tabl vg2>>vg1, i1>0 and i2<iss VG1-VGS1(ISS/2), VSS if M5 active VOH see equation below tabl vg2<vg1, i1<iss and i2>0 VDD-VSD4(sat) < vo1 < VDD VSS vg2<<vg1, i1=iss and i2=0 VDD VSS V OH = V DD (V DD -V G6 (min)- V TP ) x i3 8I (V DD -VG6(min)- V TP )2 M3 M4 v G1 M1 M2 v v out G2 C II I SS M7 VBias M5 - V SS Fig V DD i 4 v o1 i 1 i 2 C I M6

14 Lecture 310 Open-Loop Comparators (3/28/10) Page Trip Point of an Inverter In order to determine the propagation delay time, it is necessary to know when the second stage of the two-stage comparator begins to turn on. Second stage: Trip point: Assume that M6 and M7 are saturated. (We know that the steepest slope occurs for this condition.) Equate i 6 to i 7 and solve for v in which becomes the trip point. K N (W 7 /L 7 ) v in = V TRP = V DD - V TP - K P (W 6 /L 6 ) (V Bias- V SS -V TN ) Example: If W 7 /L 7 = W 6 /L 6, V DD = 2.5V, V SS = -2.5V, and V Bias = 0V the trip point for the circuit above is V TRP = /50 ( ) = V V Bias v in - V DD V SS M6 i 6 i 7 M7 v out Fig Lecture 310 Open-Loop Comparators (3/28/10) Page Propagation Delay Time of a Slewing, Two-Stage, Open-Loop Comparator Previously we calculated the propagation delay time for a nonslewing comparator. If the comparator slews, then the propagation delay time is found from dv i i i = C i dt = C v i i i t i where C i is the capacitance to ground at the output of the i-th stage The propagation delay time of the i-th stage is, V i t i = t i = C i I i The propagation delay time is found by summing the delays of each stage. t p = t 1 t 2 t 3

15 Lecture 310 Open-Loop Comparators (3/28/10) Page Example Propagation Time Delay of a Two-Stage, Open-Loop Comparator For the two-stage comparator shown V DD = 2.5V assume that C I = 0.2pF and C II = 5pF. M3 M4 M6 4.5μm 4.5μm 38μm Also, assume that v G1 = 0V and that v G2 1μm 1μm 1μm v has the waveform shown. If the input o1 voltage is large enough to cause slew to 30μA M1 M2 C I = v dominate, find the propagation time delay G1 3μm 3μm 0.2pF 1μm 1μm of the rising and falling output of the v comparator and give the propagation time G2 234μA delay of the comparator. 30μA 2.5V 0V -2.5V v G t(μs) Fig μm 1μm Solution 1.) Total delay = sum of the first and second stage delays, t 1 and t 2 2.) First, consider the change of v G2 from -2.5V to 2.5V at 0.2μs. The last row of table on Slide gives v o1 = 2.5V and v out = -2.5V 3.) t f1, requires C I, V o1, and I 5. C I = 0.2pF, I 5 = 30μA and V 1 can be calculated by finding the trip point of the output stage. M8 M5 4.5μm 1μm V SS = -2.5V M7 35μm 1μm v out C II = 5pF Fig A Lecture 310 Open-Loop Comparators (3/28/10) Page Example Continued 4.) The trip point of the output stage by setting the current of M6 when saturated equal to 234μA (V SG6 - V TP )2 = 234μA V SG6 = = 1.196V Therefore, the trip point of the second stage is V TRP2 = = 1.304V Therefore, V 1 = 2.5V V = V SG6 = 1.196V. Thus the falling propagation time delay of the first stage is t fo1 = 0.2pF 1.196V 30μA = 8 ns 5.) The rising propagation time delay of the second stage requires C II, V out, and I 6. C II is given as 5pF, V out = 2.5V (assuming the trip point of the circuit connected to the output of the comparator is 0V), and I 6 can be found as follows: V G6 (guess) 0.5[V G6 (I 6 =234μA) V G6 (min)] V G6 (min) = V G1 - V GS1 (I SS /2) V DS2 -V GS1 (I SS /2) = V G6 (guess) 0.5(1.304V-1.00V) = 0.152V = -1.00V Therefore V SG6 = 2.348V and I 6 = 6 2 (V SG6 - V TP ) 2 = ( )2 = 2,580μA

16 Lecture 310 Open-Loop Comparators (3/28/10) Page Example Continued 6.) The rising propagation time delay for the output can expressed as t rout = 5pF 2.5V 2580μA-234μA = 5.3 ns Thus the total propagation time delay of the rising output of the comparator is approximately 13.3 ns and most of this delay is attributable to the first stage. 7.) Next consider the change of v G2 from 2.5V to -2.5V at 0.4μs. We shall assume that v G2 has been at 2.5V long enough for the conditions of the table on Slide to be valid. Therefore, v o1 V SS = -2.5V and v out V DD. The propagation time delays for the first and second stages are calculated as t ro1 = 0.2pF 3V 1.304V-(-1.00V) 30μA v = 15.4 ns out 2V V t fout = 5pF 2.5V TRP6 = 1.304V 234μA = 53.42ns 1V 8.) The total propagation time delay of the 0V falling output is ns. Taking the v o1 average of the rising and falling propagation -1V time delays gives a propagation time delay -2V Falling prop. for this two-stage, open-loop comparator of Rising prop. delay time about 41.06ns. delay time -3V 200ns 300ns 400ns 500ns 600ns Time Fig Lecture 310 Open-Loop Comparators (3/28/10) Page SUMMARY The two-stage, open-loop comparator has two poles which should as large as possible The transient response of a two-stage, open-loop comparator will be limited by either the bandwidth or the slew rate It is important to know the initial states of a two-stage, open-loop comparator when finding the propagation delay time If the comparator is gainbandwidth limited then the poles should be as large as possible for minimum propagation delay time If the comparator is slew rate limited, then the current sinking and sourcing ability should be as large as possible