Lecture 23. CMOS Logic Gates and Digital VLSI I


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1 ecture 3 CMOS ogic Gates and Digital SI I In this lecture you will learn: Digital ogic The CMOS Inverter Charge and Discharge Dynamics Power Dissipation Digital evels and Noise NFET Inverter Cutoff Saturation IN TN 0 0 TN inear X
2 Digital Signal evels alid logic levels: OH egion of gain > 1 O I IH I = Maximum valid logical OW input IH = Minimum valid logical HIGH input O = Maximum valid logical OW output OH = Minimum valid logical HIGH output I, IH and O, OH are determined by the unity gain points on the transfer curve (Otherwise amplification can corrupt the logic levels as they propagate in a chain) Gain is necessary to realize logic gates!!! Digital Signal evels and Noise OH Slope > 1 OH Slope > 1 IH IH I O I IH I O Noise amplified at the output (actual signal can go outside the I valid input level for the next stage) IH Input with noise Noise is reduced at the output when the input is within the valid range Noise can be amplified at the output when the input is outside the valid range
3 Noise Margins nd when noise is present OH IH I OH IH I Noise margin HIGH (NM H ) O I IH O Noise margin OW (NM ) I IH One must have: noise O I noise OH IH Noise margins: NM I O NM H OH IH Noise and device variations sets the minimum one can use The Ideal Inverter Transfer Curve OH IH I Noise margin OW O Noise margin HIGH I IH perfectly symmetric curve with a nearvertical transition is an ideal transfer curve because: Noise margins can be made very large ogical HIGH voltage can be made very small (because the noise margins are so large) resulting smaller power dissipation 3
4 NFET Inverter: Noise Margins Problem: The input/output characteristics are not symmetric Saturation IN TN Cutoff inear 0 0 TN Noise margins are good but not excellent The oad Capacitance is the capacitance of the subsequent CMOS stage(s) as well as of the interconnects 4
5 NFET Inverter: Charging Dynamics Problem: When the output is OW, charging of the output to HIGH is slow because charging current is not uniform I I t C 1 e d dt t NFET Inverter: Charging and Discharging Dynamics H H H H X
6 NFET Inverter: Static Power Dissipation Problem: H H When the input is HIGH, and the output is OW, current keeps flowing through the FET and the resistor forever!! This is an example of static power dissipation extremely bad! CMOS Inverter: Noise Margins M C M I S M II S M S IN TN III 0 0 TN I M S M C If TN and + are close to each other, the transition region can be made narrow and sharp The noise margins can be very wide!! 6
7 CMOS Inverter: Charging and Discharging Dynamics H M H H M H X CMOS Inverter: No Static Power Dissipation H M H When the input goes HIGH or OW, power is only dissipated during the when the output makes the transition after this period, there is no power dissipation There is no static power dissipation (ideally!), only dynamic power dissipation!! H M H 7
8 ise Times, Fall Times and Propagation Delays tr ise b/w 10% to 90% of the total upward swing tf Fall b/w 90% to 10% of the total downward swing tph Propagation delay for H b/w 50% points tph tph tph Propagation delay for H b/w 50% points t f t r H ssume the input changes abruptly CMOS Inverter: Charging Dynamics M H I When the output is OW, initial charging of the output to HIGH is done with a uniform current supplied by the PFET in saturation: I C k p k p IN d dt C C d dt d dt k p t t C Condition for the PFET to be in saturation: DS GS IN IN When becomes larger than  then the PFET goes into the linear region. 8
9 CMOS Inverter: Charging Dynamics t 1 0t 1 For s 0 < t < t 1 when the PFET (M) is in saturation: p t k C k p C t C kp CMOS Inverter: Charging Dynamics When becomes larger than  then the PFET goes into the linear region, and from then onwards: d I C dt kp IN kp d C dt d C dt One can obtain faster charging compared to a resistor in place of a PFET! 9
10 CMOS Inverter: Charging Dynamics d k p C dt d k t p k p dt t C t C 1 t t 1 t t1 C 1 e e t t1 t t1 k p 1 e CMOS Inverter: Charging Dynamics One can obtain faster charging compared to a resistor: H M H ~t r tr C ln kp 0.1 t if C Cgs In reality, the load capacitance is not just p due to the next FET gate  it also includes the interconnect capacitances FET transit 10
11 CMOS Inverter: Discharging Dynamics One can obtain faster discharging compared to a resistor: H ssume the input changes abruptly M H TN S t f C 1 TN 0.1 ln kn TN TN TN0.1 In reality, the load capacitance is not just t if C Cgs n due to the next FET gate  it also includes the interconnect capacitances FET transit CMOS Inverter: Charging and Discharging Dynamics How to charge and discharge faster? H M H Decrease Increase charging current Increase supply voltage t what price? ssuming is not dominated by interconnect capacitance (not generally true), the only way to increase k n and k p of FETs and at the same decrease C gs is to decrease the FET length : t r p n tf M M S 11
12 Intel FET Gate length Trends Gate ength Mark Bohr, Intel (014) Gate ength Smaller transistor provides: Higher performance ower power ower cost per FET Year CMOS Inverter: Dynamic Power Dissipation H M H I Q: How much energy is dissipated (in the PFET and the wires) in charging the capacitor to HIGH from OW? : Irrespective of how it is charged, the net energy dissipation in charging a capacitor equals the energy stored in the capacitor after charging! 1 ED C 1
13 H CMOS Inverter: Dynamic Power Dissipation M H Q: How much energy is dissipated (in the NFET and the wires) in discharging the capacitor from HIGH to OW? : Irrespective of how it is discharged, the net energy dissipation in discharging a capacitor equals the energy stored in the capacitor before discharging! 1 ED C Total energy dissipation in one charge and discharge cycle: ED C Thermodynamics, Entropy, Information, and Computation Question: How much energy does it require to compute or process one bit of information? The question was answered by olf W. andauer ( ) (IBM) ny thermodynamically irreversible operation that manipulates information increases entropy, and an associated amount of energy is unavoidably dissipated as heat. The minimum amount of energy needed to process or compute one bit of information equals: KT log KT log 17.9 me at room temperature For the smallest CMOS inverter intel has: E D C 6.5 e ox 17 C Cgs W 10 Farads 3 tox 1 This is almost ~3500 s larger than the fundamental thermodynamic limit!!! This is almost ~5000 s smaller than where CMOS was in the 80 s There is plenty of room for improvement!!! 13
14 Dynamic Power Dissipation in CMOS Chips M M Total energy dissipation in one charge and discharge cycle per FET: ED Cgs Ignoring interconnect capacitance Total energy dissipation in one charge and discharge cycle if N FET FETs in the chip are active: E D N FET C gs Total power dissipation (energy dissipation per second) if N FET FETs are active: P N D f FET CK C gs Number of cycles per second ~ f CK Dynamic Power Dissipation in CMOS Chips E nm Chipset Fraction of active FETs at any instant on the average (~0.4%) Clock speed = 3.16 GHz Gate length: 45 nm =.045 m Number of FETs in the chip = 410 X 10 6 Power supply voltage ~ PD NFET fckcgs N.004 x 410e6 1.64e6 f t FET CK ox 3.1e9 10 (equivalent low thickness) W m.045 m C gs ox W femto Farads 3 t ox Our power dissipation estimate: PD NFET fckcgs 4 Watts!! ctual published number: P T 65 Watts!! P D P S 14
15 Intel FET Gate length Trends Gate ength Mark Bohr, Intel (014) ~ Gate ength Smaller transistor provides: Higher performance ower power < 1 ower cost per FET Year CMOS Trends Number of 1000s of FETs per cm Clock speed (MHz) Power Dissipated (W/cm ) 100 W/cm 15
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