EE115C Winter 2017 Digital Electronic Circuits. Lecture 2: MOS Transistor: IV Model

Size: px

Start display at page:

Download "EE115C Winter 2017 Digital Electronic Circuits. Lecture 2: MOS Transistor: IV Model"

Alannah Walton
5 years ago
Views:

1 EE115C Winter 2017 Digital Electronic Circuits Lecture 2: MOS Transistor: IV Model

2 Levels of Modeling Analytical CAD analytical Switch-level sim Transistor-level sim complexity Different complexity, accuracy, speed of convergence EE115C Winter

3 MOS Transistor Modeling D S Our goal is to model delay and energy not current But have to start with current EE115C Winter

4 MOSFET, Notations D G S t ox x d L eff L d x d B Hand-analysis I-V formulas: L = L eff EE115C Winter

5 Important Concepts to Understand Threshold voltage (V T ) Velocity saturation Channel length modulation (channel pinch-off) EE115C Winter

6 Threshold Voltage, V T V SB = 0 V T0 is approx 0.2V for our process V T = V T0 + γ ( 2Φ F + V SB 2Φ F ) D G B V T S V SB NMOS: V SB > 0 (RBB) V SB < 0 (FBB) PMOS: V SB > 0 (FBB) V SB < 0 (RBB) EE115C Winter

7 Outline MOS Transistor Basic Operation Modes of Operation Deep sub-micron MOS EE115C Winter

8 The Drain Current in Linear Regime Combining velocity and charge: Integrating over the channel: Transconductance: Gain factor: Small V DS ignore quadratic term linear V DS dependence L = effective L = L d 2x d EE115C Winter

9 Velocity Saturation Carrier velocity saturates when critical field is reached v v sat 10 5 m/s με ε c ε EE115C Winter

10 Simple Model EE115C Winter

11 A More General Model Approximate velocity: A more general model: for ξ ξ c for ξ ξ c we use n = 1 And integrate current again: In deep submicron, there are four regions of operation: (1) cutoff, (2) resistive, (3) saturation and (4) velocity saturation EE115C Winter

12 Including Velocity Saturation in the I D Formula EE115C Winter

13 Calculating Velocity Saturation, V DSAT EE115C Winter

14 Vsat Occurs at LOWER V DS than Sat V DS = k V GT V DS = V GT I D Vsat k Sat k = V GT ε c L k = k(v GT ) V DS EE115C Winter

15 Vsat: Less Current for Same V GS I D Sat (Long-L) V GS = V DD Vsat (Short-L) V DSAT V GT V DS EE115C Winter

16 Channel Length Modulation (CLM) Channel pinch-off EE115C Winter

17 Modeling Channel Length Modulation (CLM) Many empirical models Goal: get a simple model that is convenient for hand analysis Here is a possible modeling approach: EE115C Winter

18 MOS in Saturation with CLM Another model: DV instead of L p EE115C Winter

19 CLM Holds in Vsat V DS > V DSAT S V DS D L eff L p V DSAT ΔV DS EE115C Winter

20 Saturation vs. Velocity Saturation V-Sat occurs for lower V DS than Sat EE115C Winter

21 Simulation: Long vs. Short Channel (90nm) I D VSat (V GS ) linear, I D Sat (V GS ) quadratic Stronger CLM in short-l than long-l I D Vsat < I D Sat only for large V GS 2.4µm/0.5µm 0.48µm/0.1µm EE115C Winter

22 Simplification: V DSAT = Constant Const V DSAT Simplifies hand calculations I D BUT V DS EE115C Winter

23 Regions of Operation I D Const V DSAT Lin VSat Simplification introduces Sat region for low V GS V GT < V DSAT, the device appears to be in Sat Sat V DS V GT = V DSAT EE115C Winter

I D (ma) Unified Model vs. SPICE Simulation 0.25 0.2 0.

24 I D (ma) Unified Model vs. SPICE Simulation V DS = V DSAT Lin VSat simulation model Transition lin/v-sat: largest modeling error Sat V GT = V DSAT V DS / V REF V DS = V GT EE115C Winter

25 MOS Regions of Operation Nano-scale MOS devices operate in velocity saturation Saturation still possible for low V GS values (up to V DSAT ) EE115C Winter

26 MOS I-V Model: Active Region V GT = V GS V T G S D I D Active region (V GT 0) Lin, Sat, V-Sat 2 V min W I D = k (1 + λ V DS ) L (V GT V min ) 2 V min = min(v DS, V GT, V DSAT ) B Lin Sat V-Sat Neglect CLM in linear region EE115C Winter

27 Model Parameters: Active Region V T0 γ V DSAT k λ : Threshold voltage : Body effect : Velocity saturation : Transconductance (k = µ C ox ) : Channel-length modulation (CLM) CLM term (1 + λv DS ) also included for linear region Empirical, no physical justification EE115C Winter

28 Typical Values for 90nm ε ox ε 0 = F/m (ε ox = 3.9) t ox = 2.3 nm C ox = ε ox / t ox = 15.2 ff/um 2 For W/L = 430nm/120nm C g = 0.65 ff Leff = 70nm ε c = 4V/um Vdsat = ε c L = 0.3V EE115C Winter

29 Unified Model: Observations CLM term (1 + lv DS ) also included for linear region Empirical, not grounded in physical considerations Five parameters: V T0, g, V DSAT, k, l Can determine from physics Or choose values that best match simulation/measured data (match the best in regions that matter the most) Use different model for L >> L min (in EE115C we assume L = L min unless otherwise specified) Let s see how do we extract these parameters from the I-V curves EE115C Winter

30 140 The Meaning 120 of Model Parameters: V T0 I D (ma) I D (ma) MOS in saturation V GS =0.5V V GS =0.4V V DS (V) B A BB 0.5BB 0.7BB 1BB EE115C Winter

31 The Meaning of Model Parameters: g EE115C Winter

32 The Meaning of Model Parameters: l EE115C Winter

33 The Meaning of Model Parameters: k EE115C Winter

34 Sub-threshold Current This is another topic of crucial importance in digital design (and not considered in EE115A models) We need to consider sub-threshold current, because digital designs have many millions of transistors and when these are inactive, we may get some surprise power consumption EE115C Winter

35 I D (A) Sub-threshold I D versus V GS is Exponential 6 5 x 10-4 Long Channel 4 3 quadratic 2 Sub-threshold Short Channel 1 exp quadratic linear V GS (V) EE115C Winter

36 Modeling the Sub-threshold Behavior G S D Parasitic BJT n + E B C ox C n + V BE I C = I 0 e Φ t C d V BE = V GS 1 + C d C ox n = 1 + C d C ox V GS I D = I 0 enφ t (1 e V DS Φ t ) Φ t = kt q EE115C Winter

37 Sub-threshold I D vs. V GS Physical model V GS I D = I 0 enφ t (1 e V DS Φ t ) I 0 = μ W L Φ t 2 e V T nφ t DIBL Empirical model I D = I 0 W 10 V GS V T +γ D V DS S W 0 S = nφ t ln(10) [mv/dec] EE115C Winter

38 The Sub-threshold Slope Parameter S = nφ t ln(10) [mv/dec] Change in V GS that gives 10x change in I DS n = 1 60 mv/dec (ideal) n = mv/dec (typical) S: increases with temperature (Φ t ) n: intrinsic to device topology / structure EE115C Winter

39 Drain Induced Barrier Lowering (DIBL) Effective V T Long-L Short-L decreasing L V DS Field lines from the drain affect charge in the channel Typically derived for small V DS, holds for large V DS Even if we neglect CLM, I DS will increase b/c of V T drop Device turned off by V GS (below V T ) may turn on by V DS EE115C Winter

40 MOS I-V Model: Subthreshold V GT = V GS V T G Subthreshold region (V GT 0) I D = I W V GS V T + γ D V DS 0 S W 0 10 S I D D Model parameters B I 0 S γ D : Nominal leakage current : Subthreshold slope : DIBL factor EE115C Winter

41 90nm Simulation: Sub-threshold I D vs. V GS I D ~10 V GS V T +γ D V DS S PMOS NMOS 10x 90mV V DS : 0 to 0.4V S = nφ t ln(10) 90mV/dec EE115C Winter

42 90nm Simulation: Sub-threshold I D vs. V DS I D ~10 V GS V T +γ D V DS S PMOS NMOS V GS : 0 to 0.3V 480nm/100nm 240nm/100nm EE115C Winter

43 MOS I-V Model: Summary V GT = V GS V T G Subthreshold region (V GT 0) I D = I W V GS V T + γ D V DS 0 S W 0 10 S B I D D Active region (V GT 0) Lin, Sat, V-Sat 2 V min W I D = k (1 + λ V DS ) L (V GT V min ) 2 V min = min(v DS, V GT, V DSAT ) Lin Sat V-Sat EE115C Winter

44 .MODEL Parameters MOS1 (Basic Parameters).MODEL Modname NMOS/PMOS <VT0=VT0 > EE115C Winter

45 In Reality: GPDK090 Model (gpdk090_mos.scs) section TT_s1v parameters + s1v_rs_ne = e+000 s1v_vsat_ne = e+005 s1v_pldd_surf = e s1v_uc1_ne = e-010 s1v_u0_ne = e-002 s1v_nch_ne = e s1v_rsc_ne = e-014 s1v_cgbo_ne = e-011 s1v_prt_ne = e s1v_rdc_ne = e-014 s1v_vth0_ne = e-001 s1v_k2_ne = e s1v_cgdo_ne = e-010 s1v_ckappa_ne = e+000 s1v_wint_ne = e s1v_k1_ne = e-001 s1v_cgsl_ne = e-010 s1v_nldd_surf = e s1v_js_ne = e-006 s1v_hdif_ne = e-007 s1v_rdsw_ne = e s1v_jsw_ne = e-010 s1v_tox_ne = e-009 s1v_cj_ne = e s1v_cjsw_ne = e-011 s1v_ldif_ne = e-008 s1v_xj_ne = e s1v_rd_ne = e+000 s1v_pb_ne = e-001 s1v_cf_ne = e s1v_lint_ne = e-008 s1v_cjswg_ne = e-011 s1v_rsh_ne = e s1v_u0_pe = e-002 s1v_nch_pe = e+017 s1v_rsc_pe = e s1v_cgbo_pe = e-011 s1v_rdc_pe = e-014 s1v_vth0_pe = e s1v_k2_pe = e+000 s1v_cgdo_pe = e-010 s1v_ckappa_pe = e s1v_wint_pe = e-009 s1v_k1_pe = e-001 s1v_cgsl_pe = e s1v_js_pe = e-006 s1v_hdif_pe = e-007 s1v_rdsw_pe = e s1v_jsw_pe = e-010 s1v_tox_pe = e-009 s1v_cj_pe = e s1v_cjsw_pe = e-011 s1v_ldif_pe = e-008 s1v_xj_pe = e s1v_rd_pe = e+000 s1v_pb_pe = e+000 s1v_cf_pe = e s1v_lint_pe = e-008 s1v_cjswg_pe = e-011 s1v_rsh_pe = e s1v_rs_pe = e+000 s1v_vsat_pe = e+005 include "gpdk090_mos.scs" section = s1v_mos endsection TT_s1v This model continues on the next slide EE115C Winter

46 GPDK090 Model (section s1v_mos) section s1v_mos model gpdk090_nmos1v bsim3v3 type = n + lmin = 0.0 lmax = 1.0 wmin = wmax = 1.0 tnom = 25.0 version = tox = s1v_tox_ne toxm = s1v_tox_ne xj = s1v_xj_ne + nch = s1v_nch_ne lln = lwn = wln = wwn = lint = s1v_lint_ne + ll = 0.00 lw = 0.00 lwl = wint = s1v_wint_ne wl = 0.00 ww = wwl = 0.00 mobmod = 1 binunit = 2 + xl = 0 xw = 0 dwg = dwb = 0.00 acm = 12 ldif = s1v_ldif_ne + hdif = s1v_hdif_ne rsh = s1v_rsh_ne rd = s1v_rd_ne + rs = s1v_rs_ne rsc = s1v_rsc_ne rdc = s1v_rdc_ne + vth0 = s1v_vth0_ne k1 = s1v_k1_ne k2 = s1v_k2_ne + k3 = dvt0 = dvt1 = dvt2 = E-02 dvt0w = 0.00 dvt1w = dvt2w = 0.00 nlx = E-07 w0 = E-09 + k3b = ngate = 4.0E20 vsat = s1v_vsat_ne + ua = E-10 ub = E-18 uc = E-10 + rdsw = s1v_rdsw_ne prwb = 0.00 prwg = wr = u0 = s1v_u0_ne a0 = keta = E-02 a1 = 0.00 a2 = ags = b0 = 0.00 b1 = 0.00 And many more parameters... (compare to our 5-parameter model) EE115C Winter

47 Spectre Netlist (NMOS, PMOS) section s1v_mac subckt s1v_ckt_nch (n11 n2 n33 n4) parameters l=0.1u w=10u multi=1 factor=1 nrd=s1v_hdif_ne/factor/w nrs=s1v_hdif_ne/factor/w + Tox_ratio = 3.0e-9 / (s1v_tox_ne*s1v_tox_ne*s1v_tox_ne) MAIN (n1 n2 n3 n4) gpdk090_nmos1v w=w l=l nrd=nrd nrs=nrs multi=multi GDF1 (n2 n1) bsource i = w*0.6*s1v_xj_ne* *tox_ratio*v(n2,n1)*v(n2,n3)*exp( e11*s1v_tox_ne* GDF2 (n2 n3) bsource i = w*0.6*s1v_xj_ne* *tox_ratio*v(n2,n3)*sqrt( (v(n2,n3) *log(4.0e20 20 / s1v_nldd_surf)) + 1.0e-4 )*exp( e11*s1v_tox_ne*( *sqrt( (v(n2,n3) *log(4.0e20.0e20 / s1v_nldd_surf)) *log(4.0e20 / s1v_nldd_surf))*(v(n2,n3) s1v_nldd_surf)) + 1.0e-4 ))) rdn (n1 n11) resistor r= 6.8 *nrd/multi rsn (n3 n33) resistor r= 6.8 *nrs/multi ends s1v_ckt_nch subckt s1v_ckt_pch (p11 p2 p33 p4) parameters l=0.1u w=10u multi=1 factor=1 nrd=s1v_hdif_pe/factor/w nrs=s1v_hdif_pe/factor/w + Tox_ratio = 3.0e-9/(s1v_tox_pe*s1v_tox_pe*s1v_tox_pe) MAIN (p1 p2 p3 p4) gpdk090_pmos1v w=w l=l nrd=nrd nrs=nrs multi=multi GDF1 (p2 p1) bsource i = w*0.6*s1v_xj_pe* *tox_ratio*v(p2, p1)*sqrt( (v(p2, p1) *log(9.32E19/s1v_pldd_surf))*(v(p2, p1)-0.026*log(9.32e1 9/s1v_pldd_surf)) + 1.0e-4 )*exp( e11*s1v_tox_pe*( *sqrt( (v(p2, p1) *log(9.32E19/s1v_pldd_surf))*(v(p2, p1)-0.026*log(9.32e19 s1v_pldd_surf)) + 1.0e-4 ))*( *sqrt( (v(p2, p1) *log(9.32E19/s1v_pldd_surf))*(v(p2, p1)-0.026*log(9.32e19/s1v_pldd_surf)) + 1.0e-4 ))) GDF2 (p2 p3) bsource i = w*0.6*s1v_xj_pe* *tox_ratio* sqrt( (v(p2, p3) *log(9.32E19/ )) + 1.0e-4 ))) rdp (p1 p11) resistor r = 7.1 * nrd / multi rsp (p3 p33) resistor r = 7.1 * nrs / multi ends s1v_ckt_pch endsection s1v_mac EE115C Winter

(S&S ) PMOS: holes flow from Source to Drain. from Source to Drain. W.-Y. Choi. Electronic Circuits 2 (09/1)

(S&S ) PMOS: holes flow from Source to Drain. from Source to Drain. W.-Y. Choi. Electronic Circuits 2 (09/1) (S&S 4.1 4.3) NMOS: electrons flow from Source to Drain PMOS: holes flow from Source to Drain In cut-off ( v < V ), i = 0 GS t D NMOS I-V Characteristics In triode, ( v > V but v v v ) GS t DS GS T W 1