ECEN474/704: (Analog) VLSI Circuit Design Spring 2018
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1 ECEN474/704: (Analog) VLSI Circuit Design Spring 2018 Lecture 4: MOS ransistor Modeling Sam Palermo Analog & Mixed-Signal Center exas A&M University
2 Agenda MOS ransistor Modeling MOS Spice Models MOS High-Order Effects Lab 1 begins Jan 31 Current Reading Razavi Chapters 2 & 17 2
3 Why Do We Need MOS Spice Models? Analog circuits are sensitive to detailed transistor behavior Bias conditions set operation mode, gain, bandwidth, Can t simply use logical modeling methods, as in digital design flows Spice simulations allow us to predict the performance of complex analog circuits with models that capture high-order device operation Much easier and cheaper than actually fabricating the circuit and performing physical measurements 3
4 MOS Level 1 Model Closely follows derived Square-Law Model I I V DS DS W ncox GS n DS DS L 2L 1 D 1 W 2 ncox GS n 2 L 2LD V V 0.5V V V V V V 1 V 0 2 F VSB 2 F DS DS (riode) (Saturation) Note, extra 1+V DS term in triode equation is to have continuity between triode and saturation regions Reasonably accurate I/V characteristics for devices with L 4m, but models output resistance poorly Neglects subthreshold conduction and many high-order effects in shorter-channel length devices 4
5 MOS Level 1 Model Parameters [Razavi] 5
6 MOS Level 2 Model Improves upon the Level 1 model by modeling V variation along the channel (V DS ) Output conductance increases as V DS increases Mobility degradation due to vertical field and velocity saturation Subthreshold Behavior V dependencies on transistor W & L Contains 5-10 more parameters than level 1 model Reasonably accurate I/V characteristics for devices with L 0.7m, but still poorly models output resistance and transition point between saturation and triode 6
7 MOS Level 3 Model Similar in complexity to the level 2 model, but computationally more efficient Adds Drain-Induced Barrier Lowering effect V DS can lower effective V Different model for mobility degradation 7
8 Velocity Saturation Square-law model assumes carrier drift velocity is proportional to lateral E-field [Gray] v d E However, near critical electric field E c, carrier velocity in silicon saturates due to scattering 5 v scl 10 m Causes reduction in ID relative to square-law model I V V D GS s (fully velocity saturated) v d E E E 1 E c E c v scl v 2 scl for E for E E E c c 8
9 Mobility Degradation Carrier mobility is degraded by lateral E-field induced velocity saturation AND vertical electric field strength Vertical field attracts carriers closer to silicon surface where surface imperfections impede movement U CRI U EXP si U CRI Cox VGS V URAVDS Gate - Channel Critical Field 0 RA Fitting Parameter (0-0.5) U EXP Level 2 Model Exponent (~ 0.15) U v max Level 3 Model eff 1 v 0 1 V Mobility Modulation Parameter ( V eff eff V max GS DS L V Max Carrier Velocity -1 ) 9
10 V Dependency on W Gate-controlled depletion region extends in part outside the gate width W V monotonically increases with decreasing channel width [Pierret] V V V wide qn AW C ox V W 2W L=4u L=0.6u 10
11 V Dependency on L Source and drain assist in forming the depletion region under the gate With simple model, V monotonically decreases with decreasing channel length [Pierret] W=1.5u V V long V V qn AW C ox r j L 1 2W r j 1 W=50u 11
12 V Dependency on L: Reverse Short Channel Effect Modern device structures use a halo implant of heavy doping that surrounds the source and drain junctions his locally increases the threshold in these regions, causing an increase in the overall threshold as L is decreased At very small Ls, the effect on the previous slide may dominate 12
![AMU-474-08 [Sedra/Smith] J.](/docs-images/85/91736204/images/13-0.jpg "Silva-Martinez SPICE LEVEL3 (NON-LINEAR OUPU RESISANCE) Recall in the simple transistor model L V DS In the L3 model, a KAPPA parameter is introduced for the computation of the channel length")
13 AMU [Sedra/Smith] J. Silva-Martinez SPICE LEVEL3 (NON-LINEAR OUPU RESISANCE) Recall in the simple transistor model L V DS In the L3 model, a KAPPA parameter is introduced for the computation of the channel length modulation: L COMPUAION OF L IS MORE COMPLEX BU MORE PRECISE: E P X 2 2 D 2 KX 2 D V DS V Notice that L is funtion of: X D (technology parameter) V GS -V (Saturation voltage) Design parameter. Output resistance is function of L, I D and V DSA!! R~ L/I D dsat E P X 2 2 D -13-
14 AMU Design Example: Constant current J. Silva-Martinez 20 A m1 vd1 vd1 m2 vd2 vd2 m3 vd3 vd3 m4 vd4 vd4 m5 vd5 vd5 0 0 l=0.8u w=10u ad=20p ps=30u pd=30u 0 0 l=1.6u w=20u ad=40p ps=40u pd=40u 0 0 l=2.4u w=30u ad=60p ps=50u pd=50u 0 0 l=3.2u w=40u ad=60p ps=50u pd=50u 0 0 l=4u w=50u ad=60p ps=50u pd=50u While W/L is constant, V increases as transistor dimensions increase Check simulation operating point information to aid in the design procedure element 0:m1 0:m2 0:m3 0:m4 0:m5 id u u u u u vgs m m m vds m m m vth m m m m m vdsat m m m m m beta m m u u u gam eff m m m m m gm u u u u u gds u u u n n gmb u u u u u cdtot f f f f f cgtot f f f f f cstot f f f f f cbtot f f f f f cgs f f f f f cgd f f f f f -14-
15 AMU Design Example: Constant voltages J. Silva-Martinez 50 A Array of transistors; only 4 transistors are shown. Ideally, all transistors should have the same current! i1 vdd vd1 dc 50u m1 vd1 vd1 0 0 nmos l=0.8u w=10u ad=20p ps=30u pd=30u m2 vdd vd1 0 0 nmos l=0.8u w=10u ad=20p ps=30u pd=30u m3 vdd vd1 0 0 nmos l=1.6u w=20u ad=40p ps=40u pd=40u m4 vdd vd1 0 0 nmos l=2.4u w=30u ad=60p ps=50u pd=50u m5 vdd vd1 0 0 nmos l=3.2u w=40u ad=60p ps=50u pd=50u m6 vdd vd1 0 0 nmos l=4u w=50u ad=60p ps=50u pd=50u element 0:m1 0:m2 0:m3 0:m4 0:m5 0:m6 id u u u u u u vgs vth m m m m m m vdsat m m m m m m beta m m m u u u gam eff m m m m m m gm u u u u u u gds u u u u n n gmb u u u u u u cdtot f f f f f f cgtot f f f f f f cstot f f f f f f cbtot f f f f f f cgs f f f f f f cgd f f f f f f For best current mirror performance, use same W and L and scale the finger number -15-
16 AMU J. Silva-Martinez Avalanche: drain current I D and a substrate current I B he substrate current may contribute to latch-up he device noise increases he output impedance decreases Carriers can be trapped on the oxide and the V h changes (hot electron effect) -16-
17 Drain Induced Barrier Lowering [Razavi] [Stockinger] Drain potential controls channel charge also Higher V DS reduces barrier to the flow of charge, resulting in a net reduction in the threshold voltage 17
18 BSIM Model Berkeley Short-Channel IGFE Model (BSIM) Industry standard model for modern devices BSIM3v3 is model for this course ypically parameters Advanced software and expertise needed to perform extraction 18
19 Example 0.6m echnology Model (NMOS) *N8BN SPICE BSIM3 VERSION 3.1 (HSPICE Level 49) PARAMEERS * level 11 for Cadence Spectre * DAE: Jan 25/99 * LO: n8bn WAF: 03 * emperature_parameters=default.model ami06n NMOS ( LEVEL=11 & VERSION=3.1 & NOM=27 & OX=1.41E-8 & XJ=1.5E-7 & NCH=1.7E17 & VH0= & K1= & K2= & K3= & K3B=-14 & W0= E-7 & NLX=1E-10 & DV0W=0 & DV1W=5.3E6 & DV2W= & DV0= & DV1= & DV2= & U0= & UA= E-10 & UB= E-18 & UC= E-11 & VSA= E5 & A0= & AGS= & B0= E-6 & B1= E-6 & KEA= & A1=0 & A2=1 & RDSW= E3 & PRWG=-1E-3 & PRWB= E-5 & WR=1 & WIN= E-7 & LIN= E-8 & XL=0 & XW=0 & DWG= E-8 & DWB= E-8 & VOFF= & NFACOR= & CI=0 & CDSC= E-4 & CDSCD=0 & CDSCB=0 & EA0= E-4 & EAB= E-3 & DSUB= E-4 & PCLM= & PDIBLC1= & PDIBLC2= E-3 & PDIBLCB=-1E-3 & DROU= & PSCBE1= E9 & PSCBE2= E-8 & PVAG= & DELA=0.01 & MOBMOD=1 & PR=0 & UE=-1.5 & K1=-0.11 & K1L=0 & K2=0.022 & UA1=4.31E-9 & UB1=-7.61E-18 & UC1=-5.6E-11 & A=3.3E4 & WL=0 & WLN=1 & WW=0 & WWN=1 & WWL=0 & LL=0 & LLN=1 & LW=0 & LWN=1 & LWL=0 & CAPMOD=2 & XPAR=0.4 & CGDO=1.99E-10 & CGSO=1.99E-10 & CGBO=0 & CJ= E-4 & PB= & MJ= & CJSW= E-10 & PBSW= & MJSW= & PVH0= & PRDSW= & PK2= & WKEA= & LKEA= ) 19
20 emperature Dependence ransistor mobility and threshold voltage are dependent on temperature Mobility -3/2 due to increased scattering hreshold voltage decreases with temperature due to reduced bandgap energy E g 2 I D vs emperature W=2.4u, L=0.6u V vs emperature W=2.4u, L=0.6u -23% -3% 20
21 Process Corners Substantial process variations can exist from wafer to wafer and lot to lot Device characteristics are guaranteed to lie in a performance envelope o guarantee circuit yield, designers simulate over the corners of this envelope Example: Slow Corner hicker oxide (high V, low C ox ), low, high R SF FF SS FS [Razavi] 21
22 Inverter Delay Variation with Process & emperature 0.13m CMOS [Woo ISSCC 2009] CMOS inverter delay varies close to 40% over process and temperature Also need to consider variations in supply voltage (PV) 22
23 Next ime Layout echniques 23
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