MOS Device Modeling. C.K. Ken Yang UCLA Courtesy of Agilent eesoft EE 215B

Transcription

1 MOS Device Modeling C.K. Ken Yang UCLA Courtesy of Agilent eesoft 1

2 Overview Reading Rabaey 3.3 W&H Overview This class will look at the iv and CV characteristics of an MOS device in more detail to try to explain some of the limitations of the simple RC models that we observed in the previous lecture, and to give us some insight about how the simple RC models will change when we change power supply voltages or technology. We will extend the quadratic model to handle effects in a modern technology. In these lectures we will define a magic threshold voltage where the transistor starts to conduct, and describe briefly how this threshold depends on operating parameters. Later in the class we will revisit the issue of threshold voltage. 2

3 Review: Equation w/ Saturation * If we clamp the equation we get: W V ds i = µc V V V V L 2 V c V g, V d min V d V g V th * ds ox g s th ds ( ) V = min V,V V V * ds ds g s th i ds Vdd, V c Vdd, V d, i ds 2.5, V c 2.5, V d, 0 i ds 1.5, V c 1.5, V d, There is no current variation with output voltage V d 3

4 i ds as Function of V ds Several mechanisms Channel Length Modulation (CLM) Drain Induced Barrier Lowering (DIBL) Substrate Current Body Effect (SCBE) The dominant effect for digital circuits is CLM As the drain voltage rises above V g -V th, there is a high-field region (E max ) that forms to drop this excess voltage at the drain end of the channel. While the E-field is high, it is not infinite (E max ~ v sat /u eff ), so it takes a finite distance to drop this voltage. The net result is that the channel length is a function of the drain voltage when the transistor is saturated. The channel is effectively shortened. The effect is also known as finite output impedance, r o. 4

5 Aside: Incremental Resistance Often measure the small-signal resistance What is the effective resistance at this operating point Usually measured in conductance, rather than resistance Two important conductance values for MOS drain current g m = change in drain current when you change V gs di ds /dv gs g ds = change in drain current with a change in V ds di ds /dv ds In the saturation region, 1/g ds = r o. Both are a function of DC operating point of V gs and V ds. 5

6 Modeling CLM Simple model: ( ) L = L ζ V V eff elec d c W 1 i µc V V W 1 2 ζ Vd Vdsat i dsat µcox ( Vgs Vth ) 1+ Lelec 2 Lelec i ζ ds idsat Observations Vds Lelec CLM is a function of the length of the channel (L elec ) r o is worst for higher i dsat (V gs ) ζl min is approximately ζ is not a linear function of V ds (sublinear) ζ is a function of E max (a function of u eff ) ( V ) ( ) dsat ox gs th ζ V 2 d dsat Lelec 1 Lelec ( ) 2 6

7 CLM Model Results Results in higher currents. 90nm gpdk results in almost 20% more current than the current at V dsat. Good for digital applications (higher I on ) 7

8 Aside: Output Impedance Factors Plot is biased at V gs ~2V th 8

9 Aside: Drain-Induced Barrier Lowering For short channel lengths, V d can result in 2-D E fields in the silicon Causes the conduction barrier to be lowered at the source side Effectively reduces the threshold voltage Depends on the ratio of the channel length to the depth of the source and drain junctions. Shallow junctions reduces DIBL. 9

10 Aside: Modeling DIBL A simple formula is: Where ξ=0.02 to 0.1 w/o w/ ( ) V = V ξ V th th0 ds µc W i V V + ξv Observations ( ) ox dsat_dibl gs th0 ds 2Leff i ds V ds µc W ( Vgs Vth0 ξvds )( ξ) ox + L eff 2 Smaller effect at high V gs Very strong effect in subthreshold. 10

11 Aside: Substrate Current Body Effect High electric field at the Drain causes electrons to be highly energetic, hot Impact (w/ silicon) ionization causes hole/electron pairs. Substrate-drain current Need V ds >1.5V 11

12 Modified Effective Resistance I D V GS = V DD V GS V T S R on D R mid R 0 ζ=λl min λl min λl min VDD 1- VDD ( VDD 2) 1- ( VDD 2) 1 L elec L elec R eff + 2 IDSATN I DSATN 3 V 5 λl DD min R eff 1- VDD 4I DSATN 6 Lelec V DD /2 V DD V DS 12

13 Effective Current I D I max V GS = V DD I mid delay=cδv/i ζ=λl min avg 1 I I + I I V = V ;V = 3 V 2 4 W 1 2 I = µc ( V V ) ( ) ( ) eff max mid ds gs dd ds dd eff * ox gs th Leff 2 * Leff = L elec 1 ( 3 ) λl V 4 V L min dd dsat elec V DD /2 V DD V DS 13

14 Bulk Charge Effect V th changes with V c There is an easy fix for this problem. Assume that V th (V c ) is a linear function First order approximation V th = V tho + δv c Can be easily handled Q i i ds n ds = C dy = = Wµ C ox ( Vg Vc Vth δ Vc ) = Cox ( Vg Vc (1+ δ ) Vth) Wµ Cox ( Vg Vc (1+ δ ) Vth) dvc ox V g V s V th (1+ δ V ) 2 ds V ds 14

15 Data Comparison With Model 0.35um nmos The model is looking better but still the wrong shape. It matches well at low V gs, and even at moderate V gs and low V ds, but does not match at all at high V gs The model has too much current Cannot be fixed by scaling the current in the model (making mobility smaller Model Comparison Vg=1 model Vg=1 spice Vg=2 model Vg=2 spice Vg=3.3 model Vg=3.3 spice 15

16 0.35um pmos Comparison Not as bad as nmos device. The shape seems rougly right. Still have trouble matching the current Clearly the mobility is not constant! pmos Model Comparison Vg=1 model Vg=1 spice Vg=2 model Vg=2 EE spice 215B Vg=3.3 model Vg=3.3 spice 16

17 Modern Transistor Unfortunately this modified quadratic model is pretty old Transistors I-V does not look like that any more To get higher performance E-fields have gone up Both vertical gate field (V gs /t ox ) And lateral field (V ds /L) Under high fields, mobility is not constant High gate (vertical) E-field reduce the effective mobility Carriers have a max velocity, ν sat = 10 7 cm/s This causes i ds = (V gs - V th ) α, where α is about

18 High-Field Effects 18

19 Overview Reading Rabaey 3.3 Overview Today we will first look at the effect that high-fields have on a transistor. High fields have two principle effect -- to make the threshold voltage a function of the device dimensions, and to reduce the current through the device by limiting the carrier velocity. The book has a large discussion of the short-channel threshold effects. While it is important to realize that the threshold depends on device geometry, remembering the exact formulas is not needed. Some of today's devices have reverse short channel effects. The part to focus on is the effect of velocity saturation, and the modeling of the charge storage in a transistor 19

20 Real Transistors Current is less then projected by first order model Main error is in the approximation for mobility Assumed that it was a constant Really it is affected by both vertical and horizontal fields For the linear region Vertical field effect is most important For the saturation current Horizontal field and velocity saturation dominate There are adjustments to the models that we can use 20

21 Mobility Degradation (left): 30+% mobility reduction due to carriers pulled to collide with the surface. (right) Linear region plot of the current 21

22 nmos Vertical Field Primarily reduces the conductance in the linear region µ e V gs V gs V th t. ox V µm For a 0.35-µm transistors, T ox = 7.3 nm, V gs +V th = cm 2 V. s For 0.35um transistors Tox*.54 V/nm is around 4 as well. 600 cm2 V. s µ e V gs V gs 3.3 This is an empirical formula that was derived from data taken by the Berkeley device group headed up by Dr. Hu. The paper reference is IEEE Trans on Elect. Dev, Nav 97, Predicting CMOS Speed with Gate Oxide and Voltage Scaling and Interconnect Loading Effects, Kai Chen et. al. 22

23 pmos Vertical Field Reduces mobility but the fitting parameters is a little different, 185 µ h V gs V gs 1.5. V th 1 t. ox V µm. cm 2. 1 V. s cm2 V. s µ h V gs V gs BSIM4 uses an even more complex model for both devices

24 Velocity Saturation Vel 1 V GS + + V DS 0.8 Normalized Vel E field (x 10E4) N y = 0 Q (y), V(y) n y y = L N We have been assuming as the carriers density goes down, the electric field goes up, and the carriers move faster Carriers (e-) cannot move faster than 8x10 6 cm/sec = ν sat Current saturate when C ox (V gs -V th -V ds ) ν sat = i ds Unlike before, carriers are hitting v sat before V ds >V gs -V th 24

25 Velocity Saturated Transistors There are many ways to calculate the i-v curves They all give similar results I will use the one that gives the simplest results But it is a little tricky Journal Solid State Circuits, Aug 88, Toh, Ko, Meyer pg Approximate mobility Piecewise linear Use effective mobility reduced by vertical field Critical field depends on V gs e ν = E Ec c µe E 1+ E sat sat e c ν = ν E E E = 2ν µ c 25

26 Critical Field Since the mobility depends on the gate field, the E c also depends on V gs. Often choose E c at V gs =V dd for simplicity and worst case degradation E ch V gs E ce V gs V gs 26

27 Approximation Velocity Model for Holes and Electrons ν r ( E, 3) ν e ( E, 3) ν h ( E, 3) ν e ( E, 1) ν r ( E, 1) E Solid lines are the real electron velocity for two different gate voltages (3V, and 1V), the dotted lines are the model, and the green dotted line is the model for pmos. Velocity saturation is less of an issue for pmos devices. 27

28 Modified i-v Equations (1) i ds i i C WC ( V V V ) ( V V V ) rearranging terms and noting that E is - E ds ds = WQν = Wµ e c = µ ee = W C E 1+ E ox ox ( V V V ) g g ox c c g th c th ; th but i + Wµ ds µ ee E 1+ E e E c E c dvc = dy dvc dy 28

29 of current in saturation. Modified i-v Equations (2) W μ ecox Vds ids = Vg Vs Vth Vds L V 2 ds 1 + EcL Saturation occurs when the current forces the carriers at the channel to move at ν i i ds V Wν Wν C ( V V V ) Equating these two equations lets one solve for Vdsat, and the dsat = = It takes lots of math, but gives : dsat sat sat = sat ox gs ( Vgs Vth ) EcL ( Vgs Vth ) + EcL 2 ( Vg Vth ) Cox ( V V ) + E L gs th th ds c the end 29

30 Modified i-v Equations (3) Incorporating CLM Use the L eff instead of L But the equations gets a little tricky because L eff =f(v dsat ) To estimate drive current (V gs =V dd ) Estimate V dsat using L=L elec (the electrical channel length) Calculate effective current using L eff* V dsat ( ) ( ) ( ) Vgs Vth EcLelec Vgs Vth = = Vgs V V th + EcL elec gs V 1+ EL c elec ( 3 ) λlmin Vdd Vdsat * 4 Leff = L elec 1 Lelec W µc i = V V ( ) e ox dsat * gs th 2Leff Vgs Vth 1+ EL c * eff th 2 30

31 i-v Discussion V dsat is not fixed, except since mobility decreases with increase V gs, V ds increases to compensate I dsat is initially quadratic, but then becomes linear. I ds equation has a good feel to it: Correct in both limits Complete velocity saturation Current linear on voltage No velocity saturation Becomes quadratic model Key parameter is the relation of E c L to V In a L = 0.4µ technology E c = 6V/µ; ; E c L = 2.4V V gs -V th = 3ish; Idsat Vdsat

32 Model Comparison Vg=1 model Vg=1 spice Vg=2 model Vg=2 spice Vg=3.3 model Vg=3.3 spice Not perfect, but not terrible either Vg=1 model Vg=1 spice Vg=2 model Vg=2 spice Vg=3.3 model Vg=3.3 spice 32

33 Aside: Alpha-Power Model Simplified equation for current scaling Chen in Transactions in Electron Devices Nov 97 presented a simple model of i dsat for scaling. His model was based on alpha-power law. Clearly current is not quadratic on (V gs -V th ), so try to match it to some power. I dsat V dsat = k = c k W(V v (V Today s devices, the power is roughly 1.25 If we focus on the current equation (within a couple of generations of 0.25um) i ds α L -0.5 T ox -0.8 (V gs -V th ) 1.25 gs gs V ) t t V ) α α/2 33

34 Impact of Temperature Changing the temperature changes the device currents Increasing T makes V th smaller in magnitude. k VT =0.5-3mV/K Mobility V(T) = V(T Mobility also proportional to (T/T o ) -3/2 kµ is between -1.2 and -2 T is in Kelvin 30% slower significant change from o C ν sat does not change that much ref μ(t) = μ(t ) -k vt T T ( T T ) kμ ref )( ) ref ref I DS lower T V GS 34

35 Impact of Series Junction Resistance Less deep junction improves DIBL. but Source and drain resistances are becoming comparable to channel resistance. 25% at 65nm technology. 35

36 Geometry Effects: Short/Narrow Channel L eff =L-ΔL Reduced L (design) results in larger ΔL Increases current Opposite is true for narrow width 36

37 i-v Summary The basic quadratic model is no longer sufficient Short channel lengths and higher electric fields creates a myriad of effects and problems Many result in reduced I on Mobility degradation, velocity saturation, junction resistance And increased I off (as we will see later) Causes the Elmore delay model to not be as effective Must treat P/NMOS networks as an effective resistance/current. Many possible models Physically based model Alpha-power simple fitted model BSIM3 is a blend and accounts for all effects (including T). Many fitting parameters, and similar general form 37

38 Capacitance 38

39 Review: Charge Storage Basics Three basic capacitance to worry about: Wiring, is usually the largest Discuss more later, but is a nice linear capacitor Often couples things you don t want coupled Junction Non-linear cap, simple geometry Gate Non-linear capacitance to model channel 39

40 Review: MOS Model G S W L D C jsb C 1 C 2 C 3 C 4 x j C jdb L D C 1 - C 4 - gate capacitances Cj -- are junction capacitances 40

41 Review: Gate Overlap Parasitics Gate Overlap (C 1, C 3 ) Two terms C ox W L D = true overlap C gso, C gdo = fringe cap off the side of the gate In modern devices L D is very small (spacers) But you still have the fringe field 0.2fF/µ for each edge 41

42 Review: Junction Cap Three geometry-dependent pieces Bottom Area capacitor, proportional to W eff *DiffExt Sidewalls Edge capacitor, proportional to (W eff +2*DiffExt) GateEdge Edge capacitor for the junction edge under the transistor Included in the SPICE model, DiffExt 42

43 Review: Junction Capacitance Plot shows the cap is not linear Each junction has three components Area, outside edge and gate edge Edge are important In SPICE model Area C = C j (V bs +2φ) mj *AS Perm C = C jsw (V bs +2φ) mjsw *PS Gate Edge = C jgate (V bs +2φ) mjsw *W C j /C j pmos pmos side nmos nmos side V OUT_inverter 43

44 Review: Channel Charge C GD D C DB Traditional derivation shows that the channel charge changes with the region of operation. G C GB C 2 B C GB C C, C GS GD GB C GS C 1 + C 2 CGS S C SB C C 2 C 1 C GD C 1 (= C ) 3 V FB 0 V T V DS + V T V GS OFF (ACCUMULATION) OFF (DEPLETION) SATURATION LINEAR 44

45 Review: MOS Capacitance Table The capacitance for channel charge is often summarized in a table APPROXIMATE CAPACITANCES OFF LINEAR SATURATION C GS C 1 C C 2 C 1 + C 2 C GD C GB C C C 2 C 3 < C2 0 0 > 1/( ) 1/ + 1/ C4 C 2 2 C SB C jsb C jsb + 1 C 4 2 C jsb + 2 C 4 3 C DB C jdb C jdb + 1 C 4 2 C jdb 45

46 Accounting For Channel Charge For quadratic model, get 2/3 of C ox when transistor is in sat For velocity sat device, it will be more than 2/3 V dsat is lower It is easier just to use C ox This is a small cap, and error will be small Also, in a digital gate, the transistor ends in in linear region so you need eventually to suppy C ox V charge Actually the charge is C ox (Vdd V th ) 46

47 Short/Long Channel Charge Capacitance asymptotically approach 0 (off), ½ (linear), and 2/3 (saturation) as we sweep V DS for various V GS. Only true for long channel. C OV is significant enough to be 1/5 of total C. Long Channel Length Short Channel Length 47

48 Dealing with Nonlinear Capacitance Linear capacitor Q=CV Nonlinear capacitor C(V) Regions of operation Small signal approximation Large signal approximation Hand calculation uses a C eq Equivalent linear capacitor Average ΔQ for a ΔV=Vdd/2 Q CV C = This explains why the effective linear cap rising and falling transitions are different. The voltage range for the capacitor for delay are different (Vdd to Vdd/2 or Vdd/2 to Gnd) so the average value of capacitance in these regions is slightly different. Q Q V = f(v) 48

49 Effective Capacitance We used a simulator to find effective capacitances Simulate inverter with real non-linear capacitance Simulate inverter with linear cap Find linear cap that matches the delays These methods work well, but need to remember that capacitance values are For the voltage range you used. For different transitions. Different coupling 49

50 Simple Capacitance Insights The capacitance of a MOS device is not linear Can use this fact to your advantage (And explains some anomalies) Junction capacitance Decreases with increasing voltage Depletion depth increases If you have a large number of nmos source/drains on a line It is good if the line is at Vdd (lowest incremental cap) Better if you only swing line a small amount Adding substrate voltage reduces cap more Rising and falling delays will not match!! pmos pmos side nmos nmos side

51 Impact of Nonlinear Gate Capacitance The nonlinearity of the gate capacitance will effect our delay as well. Until the transistor turn on the gate capacitance is smaller If pmos are 2x nmos, then cap when input is near Gnd will generally be larger than cap when input is need Vdd, since near Gnd nmos are off, while near Vdd the pmos are off. This will effect rising and falling delay In particular be careful if you try to find the right ratio of nmos to pmos devices by matching delays. The result will depend on whether you use a linear cap, or an inverter as a load A significant fraction of the capacitance is overlap capacitance Does not depend on voltage a linear capacitance Causes delay to depend on loading on the successor gate. Causes all kinds of interesting effects in amplifiers 51

52 Miller Capacitance (Small Signal) Courtesy of MG Johnson 52

53 Miller Effect in Logic Gates Courtesy of MG Johnson 53

54 Simple Large Signal Approximation for Miller Effect. Consider the full swing of the input. The effective ΔV=2V dd so ΔQ = 2V dd C eq Equivalent capacitance is 2C eq Model this by doubling the input and output overlap capacitance. Does not account for the waveform shape Extra charge may not impact delay will impact power 54

55 Impact on Signal Waveform Courtesy of MG Johnson 55

56 Possible Transition Scenarios Many possible transitions are possible. May need to create a table of different cases. First 3 cases are most common. Courtesy of W&H 56

57 C-V Summary Devices are small enough that we primarily are concerned with the capacitance between terminals RF models include distributed capacitance (BSIM4) Models are generally linear Nonlinear junction caps (sqrt relations) Can take advantage of this effect in design Device capacitance across regions of operations (dominated by linear parasitics) Complexity is the coupling between the many nodes Can lead to errors in delay/power estimates Causes denser coupling matrices and hence computational complexity. 57