# Common Drain Stage (Source Follower) Claudio Talarico, Gonzaga University

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1 Common Drain Stage (Source Follower) Claudio Talarico, Gonzaga University

2 Common Drain Stage v gs v i - v o V DD v bs - v o R S Vv IN i v i G C gd C+C gd gb B&D v s vv OUT o + V S I B R L C L v gs - C gs S r o v gs -b v o v o V B R L C sb +C L EE 303 Common Drain Stage 2

3 CD Bias Point V DD Assume V B V OUT, so I D I B R S V IN V OUT V IN V GS V S V OUT I B R L V GS V T + I D 0.5C OX W / L ( ) V T V T 0 +γ PHI +V OUT PHI V B V DS V DD V OUT V DD V IN +V GS For M to be in saturation V DS > V OV V GS +V T! V DD V IN +V GS > V GS +V T! V IN < V DD +V T This is almost always the case in practical realizations EE 303 Common Drain Stage 3

4 I/O DC characteristic () Example: V IN 2.5V; I 400µA; V DD 5V; W/L00µm/µm DC Transfer Function um Technology Vout V DD -V th 3.43 V Vth M triode 6 Source: Razavi M operation V out [V] VdsVdd Vout VovVin Vout Vth V in [V] 3 2 M sat. A V V IN 2.5V) 0.82 Math artifact due to ideal current source (a current source can take any voltage value across it!!) V in [V] M triode V out (min) 0 V out (max) V DD -V th EE 303 Common Drain Stage 4

5 I/O DC characteristic (2) I Example: V IN 2.5V; I 400µA; V DD 5V; V B 0.9V; W/L00µm/µm; DC Transfer Function um Technology element 0:m 0:m2 model 0:simple_n 0:simple_n region Saturati Saturati id u u ibs f 0. ibd f f vgs m vds vbs vth m m vdsat m m vod m m beta m 5.656m gam eff m m gm m m gds u u gmb u u cdtot f f cgtot f f cstot f f cbtot 66.38f f cgs f f cgd 5.337f f * measurement av m V out [V] M 2 off M sat M 2 triode M sat V in [V] M 2 sat M sat Reduced output (and input) swing - V out (max) V DD V OV - V out (min) V OV2 VoutVds2 Vov2 Vds Vov M 2 sat M triode EE 303 Common Drain Stage 5

6 CD Voltage Transfer v o ' % sc & Ltot \$ + sc " gs + viscgs gm i o RLtot # ( v v ) 0 v i C gd +C gb + v gs - C gs v gs v o v v o i g m + sc g gs m + sc + sc gs Ltot + R Ltot LHP zero C Ltot C L + C sb C Ltot R Ltot R Ltot R L g mb r o v o v i + R Ltot s a v0 z + sc gs ( ) + s C + C gs Ltot + R Ltot often R Ltot /b s p EE 303 Common Drain Stage 6

7 Low Frequency Gain V DD a v0 g m Ltot L o gm + gmb RLtot R Interesting cases Ideal current source; PMOS with source tied to body; no load resistor; R L, r o, b 0 V o R r V i Y in C L a v0 V i V DD I B V o R L Ideal current source; NMOS; no load resistor; R L, r o, b 0 C L a v0 g m gm + g mb (typically 0.8) Ideal current source, PMOS with source tied to body; load resistor r o, b 0, R L finite gm av0 g + m EE 303 Common Drain Stage R 7 L

8 Low frequency input and output resistances R in R out v in v s R S / /b v out v in r o R L a v0 / (g m +/r o +/R L ) R in R out r o (/g m ) EE 303 Common Drain Stage 8

9 High Frequency Gain a v0 g' m +/ r o +/ R L a v ( s) v v o i a v0 s z s p z g C m gs p g C m gs + R + C Ltot Ltot Three scenarios: z < p z > p z p a v (s) a v (s) a v (s) The presence of a LHP zero leads to the possibility that the pole and zero will provide some degree of cancellation, leading to a broadband response a v0 a v0 a v0 f f (infinite bandwidth?!?) f EE 303 Common Drain Stage 9

10 CD Input Impedance Hint: ic gs (v i -v o ) By inspection: Y in sc gd + sc gs Consistent with insight from Miller Theorem ( a v (s)) v i Y in Gain term a v (s) is real and close to unity C gs v gs up to fairly high frequencies C gd +C gb + v gs - C Ltot R Ltot v o Hence, up to moderate frequencies, we see a capacitor looking into the input A fairly small one, C gd, plus a fraction of C gs EE 303 Common Drain Stage 0

11 CD input impedance for PMOS stage (with Body-source tie) V DD I B b generator inactive Low frequency gain very close to unity r o >> C gs v OUT V out C L a v0 + r o vv IN in C C gd Cin C gd C gd C bsub Very small input capacitance Y in sc gd + sc gs ( a v (s)) Y in sc gd for a v (V out V in ) no current flows through C gs (perfect bootstrap) The well-body capacitance C bsub can be large and may significantly affect the 3-db bandwidth EE 303 Common Drain Stage

12 CD Output Impedance () Let's first look at an analytically simple case Input driven by ideal voltage source C gd +C gb + v gs - C gs v gs v o Z out g m + g mb s ( C + C ) gs sb AC shorted C sb /b Z out Z L Y L sc L +/R L Low output impedance Resistive up to very high frequencies EE 303 Common Drain Stage 2

13 CD Output Impedance (2) Now include finite source resistance v g R i C gs (v g -v o ) Z x Z out C gd +C gb v o Neglect C gd i x C sb /b Z L i x ( v o v g )( + sc gs ) v o v g \$ Z x v o i x + sr ic gs + sc gs " + sc gs v o # " \$ \$ + sr i C gs \$ \$ # % ' + sc gs & % ' ' ' ' & ( ) Neglecting C gd v g v o R i sc gs + R i EE 303 Common Drain Stage 3

14 CD Output Impedance (3) Two interesting cases Z x ( + sr i C gs ) " + sc % gs \$ ' # & NOTE: Typically /gm is small, so this can happen!! R i < / R i > / Z x (s) Z x (s) / / f f Inductive behavior! EE 303 Common Drain Stage 4

15 Equivalent Circuit for R i > / Z x ( + sr i C gs ) " + sc % gs \$ ' # & for s 0 Z x / for s Z x R i for s 0 Z x R R 2 for s Z x R 2 R L R 2 Z x C sb /b Z out R R 2 L R g 2 R i R m 2 i C R i g gs m Z x (R + sl)r 2 R + R 2 + sl R + L R 2 R R + R 2 L + R + R 2 This circuit is prone to ringing! L forms an LC tank with any capacitance at the output If the circuit drives a large capacitance the response to step-like signals will result in ringing EE 303 Common Drain Stage 5

16 Inclusion of Parasitic Input Capacitance* What happens to the output impedance if we don t neglect C i C gd? * Hint: replace R i with R i Z i R i + sc i R i ( ( )) Z x + sr i C gs + C i! + sc \$ gs # & + sr i C i " % ( ) R i ( C gs + C i ) < < C gs R i C i R i ( C gs + C i ) < < R i C i C gs Z x (s) Z x (s) / / f f EE4 EE 303 Common Drain Stage 6

17 Applications of the Common Drain Stage Level Shifter Voltage Buffer Load Device EE 303 Common Drain Stage 7

18 Application : Level Shifter V i V GS +V o V o V i V GS V i (V t +V OV ) V DD V i V GS V t +V ov const. V o I B Output quiescent point is roughly V t +V ov lower than input quiescent point Adjusting the W/L ratio allows to tune Vov ( the desired shifting level) EE 303 Common Drain Stage 8

19 Why is lowering the DC level useful? When building cascades of CS and CG amplifiers, as we move along the DC level moves up A CD stage is a way to buffer the signal, and moving down the DC level EE 303 Common Drain Stage 9

20 Application 2: Buffer V DD V BB I B R D (large) M v x R out vv out Vv in M X M 2 I B2 R L (small) V B2 Low frequency voltage gain of the above circuit is ~ R big Would be ~ (R small R big ) ~ R small without CD buffer stage Disadvantage Reduced swing V out (max) V DD V OV V out (min) V OV 2 EE 303 Common Drain Stage 20

21 Buffer Design Considerations I B V DD V B B R D (large) M v x V x Vv in M X VB M2 I B2 R out vv out out R L (small) Without the buffer the minimum allowable value of V x for M x to remain in saturation is: V X > V GSX V thx With the buffer for M 2 to remain in sat. it must be: V X > V GS +V GS2 -V th2 V B2 Assuming the overdrive of M x and M 2 are comparable this means that the allowable swing at X is reduced by V GS which is a significant amount (V GS V OV +V th ) EE 303 Common Drain Stage 2

22 Application 3: Load Device Looks familiar? CS stage with diode connected load V i V DD M2 M /(2 +b2 ) V o Advantages compared to resistor load "Ratiometric" Gain depends on ratio of similar parameters Reduced process and temperature variations First order cancellation of nonlinearities Disadvantage Reduced swing V out (max) V DD V th2 a v0 g m2 gm + g mb2 V out (min) V IN V th V OV EE 303 Common Drain Stage 22

23 CD stage Issues Several sources of nonlinearity V t is a function of V o (NMOS, without S to B connection) I D and thus V ov changes with V o Gets worse with small R L ( ) V t V t 0 +γ PHI +V o PHI I D 2 µc OX W ( L V V GS t ) 2 If we worry about distortion we need to keep ΔV in /2V OV small (à we need large V OV, and this affect adversely signal swing). If R L is small, things are even worse because to obtain the desired ΔV out we need more ΔV in (and so even more V OV ) ΔV out ΔV in g' m +/ R L Small R L means less gain Reduced input and output voltage swing Consider e.g. V DD V, V t 0.3V, V OV 0.2V (V GS V t +V ov 0.5V) CD buffer stage consumes 50% of supply headroom! In low V DD applications that require large output swing, using a CD buffer is often not possible CD buffers are more frequently used when the required swing is small E.g. pre-amplifiers or LNAs that turn µv into mv at the output EE 303 Common Drain Stage 23

24 Summary Elementary Transistor Stages Common source VCCS, makes a good voltage amplifier when terminated with a high impedance Common gate Typically low input impedance, high output impedance Can be used to improve the intrinsic voltage gain of a common source stage "Cascode" stage Common drain Typically high input impedance, low output impedance Great for shifting the DC operating point of signals Useful as a voltage buffer when swing and nonlinearity are not an issue EE 303 Common Drain Stage 24

25 CD Voltage Transfer Revisited () The driving circuit has a finite resistance R s Z in CD Core example: if R S is the output resistance of a CS stage it can be relatively large Z out R S v in v out v s Cgd C gs /g m C sb R L C L v in r o /g m R tot C tot This model resembles the model of the CS stage - The main difference is in the polarity of the controlled source - This difference has profound impact on the Miller amplification of the capacitance coupling input and output EE 303 Common Drain Stage 25

26 CD Voltage Transfer Revisited (2) v out v s a v0 + s C gs + b s + b 2 s 2 a v0 R tot b R s C gs ( a v0 )+ R S C gd + R tot C gs + R tot C tot b 2 R S R tot (C gs C gd + C gs C tot + C gd C tot ) The zero in the transfer function is on the LHP and it occurs at approximately ω T Unfortunately the high frequency analysis can become quite involved. A dominant real pole does not always exist, in fact poles can be complex. In the case the poles are complex a designer should be careful that the circuit does not exhibit too much overshoot and ringing. EE 303 Common Drain Stage 26

27 CD Voltage Transfer Revisited (3) v out v s a v0 + s C gs + s C gs + b s + b 2 s a g 2 v0 m + s ω 0 Q + s2 2 ω 0 Interesting cases: - A dominant pole condition exist - Poles are complex ω 3dB b τ j b ( ) A dominant pole condition exist for: Q 2 << /4 b 2 b 2 <</ 4 EE 303 Common Drain Stage 27

28 Poles Location Roots of the denominator of the transfer function: + s ω 0 Q + s2 ω Complex Conjugate poles (overshooting in step response) for Q > 0.5 s,2 ω 0 2Q ( ± j 4Q2 ) - For Q (φ45 ), the -3dB frequency is ω 0 (Maximally Flat Magnitude or Butterworth Response) Poles location with Q> 0.5 jω φ σ - For Q > the frequency response has peaking Real poles (no overshoot in the step response) for Q 0.5 s,2 ω 0 ± 4Q2 2Q ( ) Source: Carusone EE 303 Common Drain Stage 28

29 Frequency Response 0 H(s) 5 H(s) + s ω 0 Q + s2 ω 0 2 Magnitude [db] Q0.5 Q/sqrt(2) Q Q / 0 EE 303 Common Drain Stage 29

30 Step Response Underdamped Q > 0.5 Source: Carusone Q0.5 Overdamped Q > 0.5 time Ringing for Q > 0.5 The case Q0.5 is called maximally damped response (fastest settling without any overshoot) EE 303 Common Drain Stage 30

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