MOSFET Internal Capacitance Dr. Lynn Fuller Webpage:

Transcription

1 ROCHESTER INSTITUTE OF TECHNOLOGY MICROELECTRONIC ENGINEERING Dr. Lynn Fuller Webpage: 82 Lomb Memorial Drive Rochester, NY Department webpage: MOSFET_Internal_Capaitance.pptx Page 1

2 OUTLINE Introduction Definitions s Inverter Rise and Fall times and Gate Delay Sizing Gates for Equal Rise and Fall Times Fan In and Fan Out Considerations Astable Multivibrator Two Phase Non-Overlapping Clocks Buffers Tristate I/O Pads with ESD protection Power Dissipation Energy and Delay References Homework Page 2

3 INTRODUCTION High speed electronics depends on technology, design, and architecture among other things. Technology includes Strained Silicon, Silicon on Insulator, and Metal Gate. The transistors themselves can be made of different materials such as Silicon, Germanium, or Gallium Arsenide, or can be FINFETS instead of planner MOSFETS. Design includes transistor size, gate design, interconnect methodology and more. There are many design goals other than high speed such as low power, compact size, high yield (redundancy) and more. Everything is complicated by the 100 s of millions of transistors in todays complicated microchips. The mobility of carriers in n-type silicon is always higher than the mobility in p-type silicon. In CMOS the pull up transistor drive current (pmos) in an inverter will be less than the pull down transistor drive current (nmos) for transistors of equal length and width. By increasing the width of a transistor the drive current can be increased to better match rise time and fall time. Page 3

4 DEFINITIONS Rise Time time for Vout of a gate to go from 10% to 90% Fall Time time for Vout of a gate to go from 90% to 10% Propagation Delay or Gate Delay (td) average time it takes for the output of a gate to get to the 50% point during switching to Vout high or Vout low. i.e. td = ½ (td LTH + td HTL ) Low to High Delay (td LTH ) time for output to go from low to the 50% point. High to Low Delay (td HTL ) time for output to go from high to the 50% point. Transition Frequency frequency at which the gain (gm for MOSFETs or Beta for BJTs) drops to equal 0dB called unity gain frequency or gain-bandwidth product. For BJT s frequency at which Beta, b, drops to equal 0dB. Page 4

5 RISE TIME, FALL TIME AND PROPAGATION DELAY The system speed is determined by many factors but the basic parameter that determines the speed of the system is the individual gate propagation delay, td. The propagation delay is often used as a figure of merit to compare different technologies. For example in 1997 IBM reported their measured ring oscillator propagation delay of 9.5ps the fastest reported to date for CMOS at room temperature. These times are so fast they are hard to measure so td is typically extracted from the measured period of a ring oscillator. A ring oscillator is an odd number of inverters (N) in series with the output connected back to the input, which will oscillate with period T. thus oscillator period, T, is: T = td 2N If a 1001 stage ring oscillator has a period of 0.1µs what is the gate delay, td? Answer: Rochester Institute 50ps of Technology(0.1us waveform can be easily measured with general purpose oscilloscope) Page 5

6 RISE TIME, FALL TIME AND PROPAGATION DELAY T = td 2N If a 1001 stage ring oscillator has a period of 0.1µs what is the gate propagation delay, td? Answer: 50ps (note: 0.1µs waveform can be easily measured with any general purpose oscilloscope) For npn transistors fabricated in a modern processes have f T of ~500MHz compared with nmosfets fabricated at 100nm size which have transition frequency, f T of ~ 100 GHz. Page 6

7 MOSFET INTERNAL CAPACITANCES The internal capacitors for a MOSFET are associated with the gateto-channel, Gate overlap with the Drain, Source and substrate, and the source and drain junction capacitance to the substrate. The values of these capacitors depend on the length, L, width, W, overlap in the length and width directions, and area and perimeter of the drain and source. Further, these capacitors change with voltage (with junction space charge width) and with the circuit topology including voltage gain Miller capacitance. The models are complex however this complexity is imbedded in the more advanced SPICE models used for simulation. We will attempt to get values for these capacitances, making simplifying approximations and assumptions. In addition we need to include the capacitance associated with the interconnect Rochester wiring. Institute of Technology Today s complex chips have 1000 s of meters of wiring. Page 7

8 SPICE LEVEL-1 MOSFET MODEL G S CGSO COX CGDO D p+ p+ RS ID RD CBD CBS CGBO B ID is a dependent current source. These C and R values are calculated separately in SPICE and multiplied by Ad, As, Pd, Ps, Nd, Ns, L, W etc. for a given Microelectronic MOSFET. Engineering CGBO is small compared to the other capacitors Page 8

9 TRANSISTOR LAYOUT SHOWING CAPACITANCE Gate Overlap with Substrate CGBO W Drain Gate CGD = CGS = WxCGSO Gate Overlap with Drain L Gate Fox Overlap Source Source Junction Capacitance Area=AS Perimeter=PS CBS =CJ AS + CJSW PS Note: overlap distances are the same for all transistors Page 9

10 MOSFET SHOWING INTERNAL CAPACITANCE Drain GSO L Gate C G-D C D-Sub W Substrate GFoxO C Gin C G-S Cs -Sub Source Page 10

11 SPICE LEVEL-1 PARAMETERS FOR MOSFET L Cox = r o/x OX =3.9 o/x OX GSO where r = 3.9 for Oxide o = 8.85E-14 F/cm X OX = gate oxide thickness W GFoxO CGSO is the gate-to-source overlap capacitance (per meter channel width) CGSO = Cox (using overlap, GSO, in L direction) F/m CGDO is the gate-to-drain overlap capacitance (per meter channel width) CGDO = Cox (using overlap, GDO, in L direction) F/m CGBO is the gate-to-bulk overlap capacitance, GFoxO (per meter of channel length) CGBO = Cox field_oxide (using overlap, GFoxO, in W direction) F/m where Cox field_oxide = 3.9 o/x FieldOX Page 11

12 SPICE LEVEL-1 PARAMETERS FOR MOSFET CBD zero bias bulk to drain junction capacitance CBD = CJ AD + CJSW PD CBS zero bias bulk to source junction capacitance CBS = CJ AS + CJSW PS CJ is the zero bias bulk junction bottom capacitance per m2 of junction area. CJ = r o / W where W is width of space charge layer. CJ = r o / [2 ( r o/q) ( o-va) (1/Na + 1/Nd] -m F/m2 where r = 11.7 F/cm for Silicon o = PB = (KT/q) ln (NSUB/ni) m = junction grading coefficient = 0.5 MJ is the junction grading coefficient = 0.5 CJSW is the zero bias bulk junction sidewall capacitance per meter of junction perimeter. CJSW = CJ XJ MJSW is the junction grading coefficient = 0.5 W GSO L GFoxO Page 12

13 SPICE LEVEL-1 PARAMETERS FOR MOSFET (cont.) For ~1um Technology L= 1um and W=4um Xox=150Å Xj=1um VDD=5 V AD=25um2 Field Fox=6500Å VTO =1 V PD=20um Nsub=3E16cm-3 Gate Fox Overlap (GFoxO)=2um N+D/S = 1E19 cm-3 Gate to Drain Overlap (LD)=0.1um Cox = eoer/xox=8.85e-14(f/cm)x3.9/150e-8cm = 2.30E-7 F/cm2 CGin=Cox LxW=2.30E-7(F/cm2)x1umx4um = 9.2 ff Cfield = eoer/fox = 8.85e-14(F/cm)x3.9/6500E-8cm=5.31E-9F/cm2 CG-Sub=Cfield xlxgfoxo=2x5.31e-9x2umx1um=0.21ff CGDO=Cox x LD= 2.30E-7 x 0.1um=4.6e-12F/cm CGD=CGDOxW=4.6E-12 x 4um=1.8fF Cj =eoer/wsc=5.41e-8f/cm2 CJ=Cj x AD=5.41E-8(F/cm2)x25um2=13.5fF Cjsw =eoer Xj/Wsc=5.41E-12 F/cm CJ2=Cjsw x PD = 5.41E-12 x 20um=10.8fF CBD Page 13

14 MOSFET SHOWING CAPACITANCE 1.8fF C G-D Drain 24.3fF C D-Sub Gate 9.2fF Substrate C Gin C G-S 1.8fF Source Cs -Sub 24.3fF CG Rochester = Institute C Gin of + Technology C G-S + C G-D (1-Av) = 9.2fF + 1.8fF + 1.8fF x (1- -5) = ~22fF Page 14

15 SPICE LEVEL-1 MOSFET MODEL G S 1.8fF CGSO COX 9.2fF CGDO 1.8fF D p+ p+ RS ID RD CBS 24.3fF 0.21fF 24.3fF CBD CGBO B The capacitors in this model are a function of the voltages on the D, G, S and B terminals. CGDO is across a voltage gain in many circuits so that capacitor will appear to be larger do to Miller effect. CG Rochester = Institute C Gin of + Technology C G-S + C G-D (1-Av) = 9.2fF + 1.8fF + 1.8fF x (1- -5) = ~22fF Page 15

16 GATE TO DRAIN OVERLAP, JUNCTION CAPACITANCE Since the Drain and Source Junction Capacitance is large we want to keep the area of the Drain and Source as small as we can. The doping concentration on both sides of the junction determine the space charge layer width and ultimately the junction capacitance. We can minimize that by careful well design. Today s wells are shallow and are not uniformly doped. Retrograde wells provide higher doping near but slightly below the surface to reduce punch through. The deeper parts of the drain and source contact area are to provide robust contacts. If these intersect the wells where the wells are lighter doped the junction capacitance will be lower. The Gate to Drain overlap capacitance is multiplied by the Miller effect so it is one of the larger capacitances. To reduce this overlap the Poly is oxidized after being etched (Poly ReOx) before the Drain and Source is ion implanted. This reduces the overlap because the ion implant of the D/S is placed further away from the gate edge. Page 16

17 GATE TO DRAIN OVERLAP, JUNCTION CAPACITANCE GATE SOURCE DRAIN p+ p+ WELL The Gate to Drain overlap capacitance is reduced if the Poly is oxidized before the Drain and Source is ion implanted. Page 17

18 CMOS INVERTER SHOWING CAPACITANCE During switching one transistor is off while the other is in saturation. The self capacitance is the capacitance connected to the output. One C D-sub and the overlap capacitance from gate to drain for each transistor. The capacitance from gate to drain is a Miller capacitance and is Cm =C D-sub VIN In this example: Cself = 2x(24.3fF + 1.8fF) Cself=2x25.2fF=50.4fF CG is everything connected to Vin Including miller effect CG=25.6fF 9.2fF C Gin 9.2fF C Gin 1.8fF C G-S C G-D 1.8fF 1.8fF C G-D C G-S 1.8fF VDD C D-Sub 24.3fF VOUT 24.3fF C D-Sub Page 18

19 INTERNAL CAPACITANCE CALCULATION All the internal capacitances can be calculated from the equation, C= o r Area/d, where d is the oxide thickness or width of the space charge layer. This spreadsheet does the calculations for the capacitors shown on the previous page. The total internal capacitance for the inverter with this technology is ~1.15pF ~1.15pF Page 19

20 RING OSCILLATOR, td, THEORY Seven stage ring oscillator, N=7 with two output buffers td = T / 2 N td = gate delay N = number of stages T = period of oscillation Vout Buffer Vout T = period of oscillation Page 20

21 MEASURED RING OSCILLATOR OUTPUT RIT 2µm CMOS Ring Oscillator 73 Stage Ring at 5V td = 104.8ns / 2(73) = ns Rob Saxer 2005 Page 21

22 MOSFETS IN THE INVERTER OF 73 RING OSCILLATOR nmosfet pmosfet 73 Stage Ring Oscillator Page 22

23 FIND DIMENSIONS OF THE TRANSISTORS NMOS PMOS L 2u 2u W 12u 30u AD 12ux12u=144p 12ux30u=360p AS 12ux12u=144p 12ux30u=360p PD 2x(12u+12u)=48u 2x(12u+30u)=84u PS 2x(12u+12u)=48u 2x(12u+30u)=84u NRS NRD Stage Use Ctrl Click on all NMOS on OrCad Schematic Use Rochester Ctrl Institute Click of Technology on all PMOS on OrCad Schematic Then Enter Dimensions Page 23

24 SPICE MODELS FOR MOSFETS * LTSPICE uses Level=8 *For RIT Sub-CMOS 150 process with L=2u.MODEL RITSUBN8 NMOS (LEVEL=8 +VERSION=3.1 CAPMOD=2 MOBMOD=1 +TOX=1.5E-8 XJ=1.84E-7 NCH=1.45E17 NSUB=5.33E16 XT=8.66E-8 +VTH0=1.0 U0= 600 WINT=2.0E-7 LINT=1E-7 +NGATE=5E20 RSH=1082 JS=3.23E-8 JSW=3.23E-8 CJ=6.8E-4 MJ=0.5 PB=0.95 +CJSW=1.26E-10 MJSW=0.5 PBSW=0.95 PCLM=5 +CGSO=3.4E-10 CGDO=3.4E-10 CGBO=5.75E-10) * * LTSPICE uses Level=8 *For RIT Sub-CMOS 150 process with L=2u.MODEL RITSUBP8 PMOS (LEVEL=8 +VERSION=3.1 CAPMOD=2 MOBMOD=1 +TOX=1.5E-8 XJ=2.26E-7 NCH=7.12E16 NSUB=3.16E16 XT=8.66E-8 +VTH0=-1.0 U0= WINT=2.0E-7 LINT=2.26E-7 +NGATE=5E20 RSH=1347 JS=3.51E-8 JSW=3.51E-8 CJ=5.28E-4 MJ=0.5 PB=0.94 +CJSW=1.19E-10 MJSW=0.5 PBSW=0.94 +CGSO=4.5E-10 CGDO=4.5E-10 CGBO=5.75E-10) Page 24

25 SIMULATED OUTPUT AT 5 VOLTS Three Stage Ring Oscillator with Transistor Parameters for 73 Stage Ring Oscillator and Supply of 5 volts Measured Microelectronic td = Engineering V td = T / 2N = 5.5nsec / 2 / 3 td = 0.92 nsec Page 25

26 CONCLUSION Since the measured and the simulated gate delays, td are close to correct, then the SPICE model must be close to correct. The inverter gate delay depends on the values of the internal capacitors and resistances of the transistor. Specifically: RS, RD, RSH CGSO, CGDO, CGBO CJ, CJSW These are combined with the transistors L, W Length and Width AS,AD Area of the Source/Drain PS,PD Perimeter of the Source/Drain NRS,NRD Number of squares Contact to Channel Page 26

27 GATE DELAY FROM SPICE Equal L and W Gate Rochester delay Institute is the of Technology time to get to 50% of the final value. td LTH = 441ps td HTL = 328ps Page 27

28 GATE DELAY Equal L and W Include parameters Gate Rochester delay Institute is of the Technology time to get to 50% of the final value. td LTH = 825ps td HTL = 599ps Page 28

29 INVERTER MODEL FOR LTH AND HTL TRANSISTION ReqP PMOS +V Ipmos -125uA +100uA NMOS ReqN Inmos Cin ReqN = ~ Vave/Iave = 2.5/125uA = 20K ohms ReqP = ~ Vave/Iave = 2.5/100uA = 25K ohms Gate delay is the time to get to 50% of the final value. Page 29

30 INVERTER RISE TIME AND FALL TIME ReqN = ~ Vave/Iave = 2.5/125uA = 20K ohms ReqP = ~ Vave/Iave = 2.5/100uA = 25K ohms RN = 1/(q µ n Dose) x Lnmos/Wnmos RP = 1/(q µ p Dose) x Lpmos/Wpmos Rise/Fall time is defined as the time for Vout to go from10% to 90%. For rise time equal to fall time the RC time constants are equal RN Cin = RP Cin Lnmos/(Wnmos µn) = Lpmos/(Wpmos µp) µp / µn = (Lpmos/Wpmos) / (Lnmos/Wnmos) Often Lpmos = Lnmos Finally µp / µn = (Wnmos/Wpmos) Wpmos = Wnmos (µn/µp) Page 30

31 Mobility (cm 2 / V sec) MOBILITY ^13 10^14 holes 10^15 10^16 Total Impurity Concentration (cm -3 ) electrons 10^17 10^18 See Dr. Fuller s Mobility Calculator 10^19 From Muller and Kamins, 3 rd Ed., pg 33 10^20 Electron Arsenic and hole mobilities in silicon Boron at 300 K as functions Phosphorus of the total dopant concentration (N). The values plotted are the results of the curve fitting measurements from several sources. The mobility curves can be generated using the equation below with the parameters shown: µ(n) = µ mi + (µ max-µ min ) {1 + (N/N ref ) } Parameter Arsenic Phosphorous Boron µ min µ max N ref 9.68X10^ X10^ X10^ Page 31

32 RISE TIME EQUALS FALL TIME Wpmos = 1.5 x Wnmos Gate Rochester delay Institute is of the Technology time to get to 50% of the final value. td LTH = 526ps td HTL = 663ps Page 32

33 RISE TIME EQUALS FALL TIME Wpmos = 1.25 x Wnmos Gate Rochester delay Institute is of the Technology time to get to 50% of the final value. td LTH = 604ps td HTL = 652ps Page 33

34 LOGIC GATE RISE TIME AND FALL TIME The inverter rise time is determined by the channel resistance and the capacitance to be charged or discharged. +V ReqP = 25K L/W For L=2um and W=3um PMOS Ipmos RC=25K/1.5 x 41fF = 683ps NMOS Inmos Cself Cwire CG ReqN= 20K L/W 22fF zeroff 19fF Page 34

35 LOGIC GATE RISE TIME AND FALL TIME The inverter rise time is determined by PMOS and NMOS current charging or discharging output capacitance. Q = CV +V I = Q/t = CV/t I = 125uA t = CV/I PMOS Ipmos C total= 41fF t = 41fF 2.5/125uA = 820ps For L=2um W= 2.5um NMOS For L=2um W= 2um Inmos I = 125uA 22fF Cself Cwire zeroff 19fF CG Page 35

36 CAPACITANCE FOR EXAMPLE ON PREVIOUS PAGE Page 36

37 MORE DETAIL OF CURRENTS IN AN INVERTER Page 37

38 WIRE RESISTANCE AND CAPACITANCE, LOW K, CU The wiring is typically aluminum or copper. The resistivity of aluminum is 26.5 nohm-cm and copper is 17.1 nohm-cm thus the wire will be lower resistance if copper. Page 38

39 MULTILAYER METAL, W PLUGS, CMP 8 Layers Metal Page 39

40 LOW-K FOR INTERCONNECT Page 40

41 CMOS INVERTER DESIGN The design guideline is that the inverter should have the same current drive when Vout is switching low to high as high to low. Because the mobility of electrons is ~1.5 times higher than mobility for holes we make the PMOS 1.5 times wider. Typically L s are the same. (W/L) pullup = ~ 1.5 (W/L) pulldown based on mobility only Vin Vout Pull up 1.5µW/L +V I low to high I D = µw Cox (Vg-Vt) 2 2L Vin Vout Pull down µw/l CMOS C Load Page 41

42 CMOS NOR AND NAND The design guideline for other logic gates is to provide the same current drive as the inverter. For the NOR gate we can go from high to low by starting with both inputs at zero and then making either input high or both high. The worst case condition is making only one input high. For that condition we want the same current drive as the inverter. Thus the width of the NMOS should be W. If both the inputs were switching high at the same time the current would be twice as much (that s okay) For a low to high transition the current goes through two PMOS in series. The equivalent L for the series combination is 2L. If the width for each transistor was 3W the combined value is 3W/2L which is 1.5W/L as desired for equal drive current as the inverter. VA VB NOR NAND VA VB Vout 3W W VA +V 3W NOR W VB W VA 2W +V 2W VA VB 1.5W NAND VB Vout Page 42

43 SIZING AND TIMING FOR THREE-INPUT NAND To achieve equal rise time and fall time (and make these times approximately equal to the simple inverter rise time and fall time). The transistors length and width can be calculated. In the simple inverter the nmos W/L is the smallest values for that technology. The pmos is 1.5 times wider to give equal drive current. For a more complex gate there will be transistors in series and parallel and those combinations need to be considered when trying to achieve rise and fall times equivalent to the simple inverter. For example: M1, M2 and M3 have a combined length of 3L So the combined width should be 3W to give drive current equivalent to the nmos in the simple inverter. M1,M2,M3 nmos = 3W/L The worst case condition for low to high transition is only one input going low. So the width of the PMOS should be 1.5W. (when two or more inputs are going low at the same time there will be more current (that is okay) 1.5W/L VA M2 M3 +V Page W/L 1.5W/L M1 3W/L 3W/L 3W/L VOUT VB VC

44 FAN IN AND FAN OUT CONSIDERATIONS Fan in refers to the number of inputs to a gate. It is common to have up to 8 inputs. In CMOS this implies that there are 8 transistors in parallel and 8 transistors in series. The 8 in parallel is not necessarily a problem but the 8 in series is because of the body effect on the threshold voltage of some of the transistors if they are all in the same well (at Vss or Vdd for p-well or n-well respectively) The solution to this problem is to use a Pseudo CMOS logic gate where the series transistors are replaced by a single transistor with the gate wired to VDD or Ground for NMOS or PMOS respectively. This transistor is always on. Fan-In = 6 Page 44

45 FAN IN AND FAN OUT CONSIDERATIONS What is the correct sizing for the transistors in this gate? Fan-In = 6 1.5W W Page 45

46 FAN OUT GATE CAPACITANCE Fan out refers to the number of gates connected to the output of a gate. Each gate adds more capacitance to be charged or discharged during switching which has implications on rise time, fall time and gate delay. The size (W and L) of the MOSFETS in the gate, G1, can be set to keep the gate delay small. C G = C Gin + C G-S + C G-D (1-Av) = 23fF + 2.3fF + 2.3fF x (1- -5) = ~25fF Fan-Out = 6 C fan-out = Fan-Out x (C G ) = 6 x 25fF = 150fF G1 C G C G C G C G C G C G Page 46

47 TWO PHASE NON OVERLAPPING CLOCK Synchronous circuits that use the two phase non overlapping clock can separate input quantities from output quantities used to calculate the results in feedback systems such as the finite state machine. 1 2 Page 47

48 SWITCHED CAPACITOR VOLTAGE DOUBLER 2 2 C1 1 Vdd C1 C Load R Load 2 Application for two phase non overlapping clock Page 48

49 TWO-PHASE CLOCK GENERATORS A CLOCK B C R CLOCK t 1 CLOCKBAR S t 2 t 3 Q 1 2 R S Q 0 0 Qn INDETERMINATE CLOCK BAR 1 t 1 t 2 t 1 2 t 3 t 3 = Page 49

50 TRANSISTOR LEVEL SCHEMATIC OF 2 PHASE CLOCK +V Layout 1 Clock 2 +V Page 50

51 TWO PHASE NON OVERLAPPING CLOCK Clock 1 2 Page 51

52 CMOS TWO PHASE NON-OVERLAPPING CLOCK Page 52

53 CMOS TWO PHASE NON-OVERLAPPING CLOCK Page 53

54 SIMULATION NON-OVERLAPPING CLOCK + BUFFERS R CLOCK t 1 CLOCKBAR S t 2 t 3 1 BUFFERS 2 Page 54

55 SIMULATION NON-OVERLAPPING CLOCK + BUFFERS R CLOCK t 1 CLOCKBAR S t 2 t 3 1 BUFFERS 2 0.1pF Loads Page 55

56 SIMULATION NON-OVERLAPPING CLOCK + BUFFERS R CLOCK t 1 CLOCKBAR S t 2 t 3 1 BUFFERS 2 5pF Loads 10pF Loads Page 56

57 SIMULATION NON-OVERLAPPING CLOCK + BUFFERS R CLOCK t 1 CLOCKBAR S t 2 t 3 1 BUFFERS 2 4xL 16xL Page 57

58 SIMULATION NON-OVERLAPPING CLOCK + BUFFERS R CLOCK t 1 CLOCKBAR S t 2 t 3 1 BUFFERS 2 10pF Loads Page 58

59 CMOS TRISTATE INPUT OUTPUT PAD The Input/Output/Tristate Pad is the interface between the chip and the rest of the system. The pad is typically connected via a printed circuit board (PCB) to other chips, other PCB s, and other devices. If an oscilloscope probe is connected to a chip it represents a large capacitive load (~10pF) in parallel with a 1MEG or 10MEG resistor. If the chip is connected in parallel with other chips (as is done in memory) via a data bus it represents a large capacitive load to the chip. In the case of a data bus the pad could be for an input or an output signal or high impedance (thus Tri State) Also, these pads are subject to possible electrostatic discharge (ESD) as connections are made to the pads. Page 59

60 TRISTATE I/O PAD WITH ESD PROTECTION - SCHEMATIC Data D Enable EN Vdd l/w=5/30 l/w=5/40 Tristate Logic l/w=5/20 M1 M2 M3 M8 l/w=5/20 Vdd l/w=5/40 M5 M6 l/w=5/20 M4 l/w=5/20 Vdd M7 l/w=5/40 M9 l/w=5/40 M10 l/w=5/20 M11 l/w=5/ M12 l/w=5/1000 Vdd I/O l/w=5/46 M13 M14 l/w=5/28 Pad IN Vin ESD Protection M4 Page 60

61 TRISTATE I/O PAD WITH ESD PROTECTION - SCHEMATIC If the enable EN is low M5 will be on making M11 off. If the enable EN is low M10 will be on making M12 off. Data can be low or high and if EN is low both M11 and M12 are off. This is the high impedance state. If EN is high M6 will be on and if Data is high then M4 will be on making M11 on providing a high output to the I/O pad. If EN is high M9 will be on and if Data is low then M7 will also be on making M12 on providing a low output to the I/O pad. Transistors M13 and M14 will normally be off unless the pad voltage is at large negative or positive voltages. For large negative voltages current can flow from ground through M14 and the resistor. For large positive voltages (more than Vdd) current can flow through the resistor and M13 to Vdd. The voltage IN will always be between Vdd +0.7 and -0.7 volts. Page 61

62 TRISTATE I/O PAD WITH ESD PROTECTION - LAYOUT Resistor Page 62

63 ELECTROSTATIC DISCHARGE Electrostatic Discharge (ESD) Dielectric Breakdown Strength of SiO2 is approximately 8 E6 V/cm, thus a 250 Å gate oxide will not sustain voltages in excess of 20 V Triboelectricity (electricity produced by rubbing two materials together) can generate high voltages. A person walking across a room can generate 20,000 Volts and if discharged into an IC can cause immediate failure or damage that will reduce operating life. Even with proper handling several hundred volts can be applied to the IC. Therefore, protection circuitry is needed to provide a safe path for discharge of this electricity. Page 63

64 ESD DAMAGE Page 64

65 ELECTROSTATIC DISCHARGE - PROTECTION CIRCUITRY VDD PAD R -10 I 0.7 V FIRST TRANSISTOR GATE Page 65

66 ELECTROSTATIC DISCHARGE - MODEL Human Model: 0 to 5000 Volts R = 1500 ohms L = 7.5 µh C = 100 pf R VDD Machine Model One: 0 to 100 Volts R = 100 ohms R VDD Machine Model Two L = 1.0 µh C = 200 pf R = 10 ohms Charged Device Model L = 50 nh C = 10 pf R = 1 ohms Page 66

67 SPICE FOR ESD CIRCUIT Page 67

68 REFERNCES 1. Hodges Jackson and Saleh, Analysis and Design of Digital Integrated Circuits, Chapter Sedra and Smith, Microelectronic Circuits, Sixth Edition, Chapter Dr. Fuller s Lecture Notes, Page 68

69 HOMEWORK HIGH SPEED LOGIC 1. Investigate a 100nm ring oscillator. Does the number of stages change the period of oscillation, explain. Does the number of stages change the inverter gate delay, td, explain. Does the size of the transistors affect the period of oscillation, explain. Does the supply voltage, VDD, affect the period of oscillation, explain. Does the temperature affect the period of oscillation, explain. 2. Use SPICE to illustrate some of the questions in problem The simple hand calculation for inverter gate delay, td, uses Resistors to represent the PMOS and NMOS transistors and capacitors to represent the gate self capacitance and input capacitance. Assume the wiring capacitance is zero. How are the resistors and capacitors different for 1um technology compared to 100nm technology. Provide approximate values for the resistors and capacitors for both technologies. Page 69

70 SPICE MODELS FOR CD4007 MOSFETS *SPICE MODELS FOR RIT DEVICES - DR. LYNN FULLER *LOCATION DR.FULLER'S WEBPAGE - * *Used in Electronics II for CD4007 inverter chip *Note: Properties L=10u W=170u Ad=8500p As=8500p Pd=440u Ps=440u NRD=0.1 NRS=0.1.MODEL RIT4007N7 NMOS (LEVEL=7 +VERSION=3.1 CAPMOD=2 MOBMOD=1 +TOX=4E-8 XJ=2.9E-7 NCH=4E15 NSUB=5.33E15 XT=8.66E-8 +VTH0=1.4 U0= 1300 WINT=2.0E-7 LINT=1E-7 +NGATE=5E20 RSH=300 JS=3.23E-8 JSW=3.23E-8 CJ=6.8E-8 MJ=0.5 PB=0.95 +CJSW=1.26E-10 MJSW=0.5 PBSW=0.95 PCLM=5 +CGSO=3.4E-10 CGDO=3.4E-10 CGBO=5.75E-10) * *Used in Electronics II for CD4007 inverter chip *Note: Properties L=10u W=360u Ad=18000p As=18000p Pd=820u Ps=820u NRS=O.54 NRD=0.54.MODEL RIT4007P7 PMOS (LEVEL=7 +VERSION=3.1 CAPMOD=2 MOBMOD=1 +TOX=5E-8 XJ=2.26E-7 NCH=1E15 NSUB=8E14 XT=8.66E-8 +VTH0=-1.65 U0= 400 WINT=1.0E-6 LINT=1E-6 +NGATE=5E20 RSH=1347 JS=3.51E-8 JSW=3.51E-8 CJ=5.28E-8 MJ=0.5 PB=0.94 +CJSW=1.19E-10 MJSW=0.5 PBSW=0.94 pclm=5 +CGSO=4.5E-10 CGDO=4.5E-10 CGBO=5.75E-10) Page 70

71 SPICE MODELS FOR MOSFETS * From Sub-Micron CMOS Manufacturing Classes in MicroE ~ 1um Technology.MODEL RITSUBN7 NMOS (LEVEL=7 +VERSION=3.1 CAPMOD=2 MOBMOD=1 +TOX=1.5E-8 XJ=1.84E-7 NCH=1.45E17 NSUB=5.33E16 XT=8.66E-8 +VTH0=1.0 U0= 600 WINT=2.0E-7 LINT=1E-7 +NGATE=5E20 RSH=1082 JS=3.23E-8 JSW=3.23E-8 CJ=6.8E-4 MJ=0.5 PB=0.95 +CJSW=1.26E-10 MJSW=0.5 PBSW=0.95 PCLM=5 +CGSO=3.4E-10 CGDO=3.4E-10 CGBO=5.75E-10) * *From Sub-Micron CMOS Manufacturing Classes in MicroE ~ 1um Technology.MODEL RITSUBP7 PMOS (LEVEL=7 +VERSION=3.1 CAPMOD=2 MOBMOD=1 +TOX=1.5E-8 XJ=2.26E-7 NCH=7.12E16 NSUB=3.16E16 XT=8.66E-8 +VTH0=-1.0 U0= WINT=2.0E-7 LINT=2.26E-7 +NGATE=5E20 RSH=1347 JS=3.51E-8 JSW=3.51E-8 CJ=5.28E-4 MJ=0.5 PB=0.94 +CJSW=1.19E-10 MJSW=0.5 PBSW=0.94 +CGSO=4.5E-10 CGDO=4.5E-10 CGBO=5.75E-10) Page 71

72 SPICE MODELS FOR MOSFETS * LTSPICE uses Level=8 * From Electronics II EEEE482 FOR ~100nm Technology.model EECMOSN NMOS (LEVEL=8 +VERSION=3.1 CAPMOD=2 MOBMOD=1 +TOX=5E-9 XJ=1.84E-7 NCH=1E17 NSUB=5E16 XT=5E-8 +VTH0=0.4 U0= 200 WINT=1E-8 LINT=1E-8 +NGATE=5E20 RSH=1000 JS=3.23E-8 JSW=3.23E-8 CJ=6.8E-4 MJ=0.5 PB=0.95 +CJSW=1.26E-10 MJSW=0.5 PBSW=0.95 PCLM=5 +CGSO=3.4E-10 CGDO=3.4E-10 CGBO=5.75E-10) * * LTSPICE uses Level=8 * From Electronics II EEEE482 FOR ~100nm Technology.model EECMOSP PMOS (LEVEL=8 +TOX=5E-9 XJ=0.05E-6 NCH=1E17 NSUB=5E16 XT=5E-8 +VTH0=-0.4 U0= 100 WINT=1E-8 LINT=1E-8 +NGATE=5E20 RSH=1000 JS=3.51E-8 JSW=3.51E-8 CJ=5.28E-4 MJ=0.5 PB=0.94 +CJSW=1.19E-10 MJSW=0.5 PBSW=0.94 PCLM=5 +CGSO=4.5E-10 CGDO=4.5E-10 CGBO=5.75E-10) * Page 72

73 SOLUTION The layout for an NMOS transistor and its SPICE model is shown on the next page. Calculate the internal capacitance Cgate and Cdrain. Cgate = o r Area / TOX where Area = L x W = 2um x 12um = 8.85e-12 (3.9) (2e-6) 12e-6/1.5e-8 = 55.2fF Cdrain = Cj Ad + Cjsw Pd where Cj=6.8e-4 and Cjsw=1.26E-10 Ad=144p Pd=48u Cdrain = 6.8e-4x144e e-10x48e-6 = 97.9fF fF = 104fF Combine these capacitors into one equivalent capacitance (Cinverter) at the output node of a CMOS inverter in a ring oscillator. Assume the PMOS capacitor values are equal to the NMOS internal capacitor values. Cinverter = 2 Cgate + 2 Cdrain = 2x55.2fF +2x104fF = 318fF If the transistors provide a constant current of 3mA when charging or discharging Cint calculate the gate delay lowto-high TDLH and high-to-low TDHL and the inverter gate delay. Q=CV=I t where V= VDD/2= 2.5, C=Cinverter, I=3mA TDLH = TDHL = Cinverter xv / I = 318fF x 2.5 / = 0.265ns td = TDLH + TDHL = 0.53ns

74 * From Sub-Micron CMOS Manufacturing Classes in MicroE ~ 1um Technology.MODEL RITSUBN7 NMOS (LEVEL=7 +VERSION=3.1 CAPMOD=2 MOBMOD=1 +TOX=1.5E-8 XJ=1.84E-7 NCH=1.45E17 NSUB=5.33E16 XT=8.66E-8 +VTH0=1.0 U0= 600 WINT=2.0E-7 LINT=1E-7 +NGATE=5E20 RSH=1082 JS=3.23E-8 JSW=3.23E-8 CJ=6.8E-4 MJ=0.5 PB=0.95 +CJSW=1.26E-10 MJSW=0.5 PBSW=0.95 PCLM=5 +CGSO=3.4E-10 CGDO=3.4E-10 CGBO=5.75E-10) *