EE410 vs. Advanced CMOS Structures

Size: px
Start display at page:

Download "EE410 vs. Advanced CMOS Structures"

Transcription

1 EE410 vs. Advanced CMOS Structures Prof. Krishna S Department of Electrical Engineering S 1 EE410 CMOS Structure P + poly-si N + poly-si Al/Si alloy LPCVD PSG P + P + N + N + PMOS N-substrate NMOS P-well LOCOS Field oxide General Features of the EE410 Process 7 mask levels 0.45µm minimum dimensions 540nm field oxide LOCOS isolation 10nm gate oxide p+ poly-si gate for PMOS transistors and n+ poly-si for NMOS transistors single mask n + and p + source/drain definition (no LDD) single level of aluminum/silicon metallization phosphosilicate glass (PSG) passivation non-silicided contacts (high metal contact resistance to poly and active regions) 2 2 1

2 Dual Well CMOS Technology Global Interconnect Semi-global Interconnect N-well P+ P+ N+ N+ LDD P-well LOCOS Isolation PMOS NMOS 3 Feature Size Trend & Moore s Law 1 Generation 0.1 micron L GATE Reduction in transistor area has resulted in higher packing density and hence more complex chips 4 2

3 Scaling of MOS Gate Dielectric K I D g m thickness (Ref: S. Asai, Microelectronics Engg., Sept. 1996) Gate SiO 2 thickness is approaching < 10 Å to improve device performance How far can we push MOS gate dielectric thickness? How will we grow such a thin layer uniformly? How long will such a thin dielectric live under electrical stress? How can we improve the endurance of the dielectric? 5 MOS Technology in 2010 Gate oxide thickness ~ 1 nm Channel Length ~ 20 nm Junction depth ~ 1-2 nm Size of an atom ~ 5Å In integrated system 10 billion components 10 interconnect layers Technological Issues Gate dielectrics/electrode Shallow junctions Isolation Contacts Interconnections 6 3

4 Problems in Scaling of Gate Oxide Below 20 Å problems with SiO 2 Gate leakage => circuit instability, power dissipation Degradation and breakdown Dopant penetration through gate oxide Defects 7 MOSFET Scaling Limit: Leakage Total Leakage Trend Gate Leakage S/D Leakage Source: Marcyk, Intel Lo et al.,ieee EDL, May Total Power Trends Ability to control I off will limit gate-length scaling Thermionic emission over barrier QM tunneling through barrier Band-to-band tunneling from body to drain To suppress D/S leakage, need to use: Higher body doping to reduce DIBL lower mobility, higher junction capacitance, increased junction leakage Thinner gate dielectric to improve gate control higher gate leakage Ultra-shallow S/D junctions to reduce DIBL higher R series 8 4

5 High-k Dielectric Technology Evolution Physical thickness can be increased for MOS gate dielectric operation by using a higher K dielectric K I D g m thickness Long term Today 20 Å SiO 2 K 4 Si Near future 40 Å Si 3 N 4 K Å high K K 20 Higher thickness -> reduced gate leakage 9 Silicide R csd Parasitic S/D Resistance Sidewall R dp R ext N ext (x) y = 0 R ov Gate N ov (y) R R ch sd Lchtox ( V V ) th R sh gs 1 N X sd Scaled with L g (L ch, t ox ) j Difficult to scale (N sd const, X j ) R sd /R ch I DS [( ) I DS R SD ] α SAT = Κ V GS V T Problem in junction scaling: With scaling parasitic S/D resistance R SD increases compared to channel resistance Contact resistance R csd is one of the dominant components for future technology Problem more serious for PMOS Source: Jason Woo, UCLA 10 5

6 Solutions to Shallow Junction Resistance Problem Extension implants Elevated source/ drain Silicidation 11 Device Isolation pitch as a function of minimum dimension M M 1.0 1G 0.5 P. Fazan, Micron, IEDM-93 With decreasing feature size the requirement on allowed isolation area becomes stringent Minimum dimension [µm] 12 6

7 Scaling of Device Isolation Semi-recessed LOCOS Nitride Pad oxide Nitride Field oxide LOCOS based isolation technologies have serious problems in loss of area due to birdʼs beak. Shallow trench isolation P-substrate N-well Deep trench isolation Trench isolation can minimize area loss 13 Physical Limits in Scaling Si MOSFET Source/Drain Contact resistance Band-to-band tunneling Doping level, abruptness Source Gate stack Tunneling current Gate depletion, resistance Gate Drain High E-Field Mobility degradation Reliability te Substrate Channel Surface scattering - the universal mobility tyranny Subthreshold slope limited to 60mV/decade (kt/q) V G - V T decrease DIBL leakage Net result: Bulk-Si CMOS device performance increase commensurate with size scaling is unlikely beyond the 65 nm generation 14 7

8 3 New Structures and Materials for Nanoscale MOSFETs Si G S C D Si SiO 2 Source High µ channel Top Gate Bottom Gate BULK SOI Double gate Drain High-K 1. Electrostatics - Double Gate - Retain gate control over channel - Minimize OFF-state drain-source leakage 2. Transport - High Mobility Channel - High mobility/injection velocity - High drive current for low intrinsic delay 3. Parasitics - Schottky S/D - Reduced extrinsic resistance 4. Gate leakage - High-K dielectrics - Reduced power consumption 5. Gate depletion - Metal gate 15 Non Planar MOSFETs Vertical FET D Double Gate FinFET Channel Tri Gate FET Gate 1 Gate 2 Source SiO 2 Tsi:45nm Lch=250nm Drain Gate1 Gate2 Source Gate Source Drain Stanford UC Berkeley 16 Intel 8

9 Mobility Enhancements in Strained-Si MOSFETs Gate electrode n + p o l y LTO gate oxide spacer Strained Si n + Relaxed Si 1-x Ge n + x Si 1-x Ge x Graded layer Si Substrate Mobility Enhancement Factor Calculated for strained Si 1.0 MOS inversion layer M S. Takagi, et al., J. Appl. Phys. 80, Substrate Ge fraction, x V DS = 10 mv 300 K NMOS Measured, J. Welser, et al., IEDM Gibbons Group, Stanford 17 Intel PMOS Seemingly Useful Devices Limited Current Drive Cryogenic operation Limited Fan-Out Critical dimension control Challenging fabrication and process integration B + = ~ 2 nm Spintronics Need high spin injection and long spin coherence time Limited thermal stability New architectures needed 18 Carbon Nanotubes Controlled growth 9

10 Limits of Interconnect 22nm Node 32nm Node 2.5X Combined Grain Boundary Scattering Surface Scattering Cu (bulk) Old A New (scaled) l 19 bit rate B A/l 2 Scaled wire with lower A and longer l has higher R,C and L and thus reduced bandwidth, higher delay and higher power dissipation Current Interconnect Technologies Copper 6 Copper 5 Copper 4 Copper 3 Copper 2 Copper 1 Current Al technology (Courtesy of Motorola) Current Cu/low-K technology (Courtesy of IBM) Tungsten Local Interconnect Reduced resistivity and dielectric constant results in improvement in performance

11 Carbon Nanotubes 1-D conductors: 3-D conductors: E Quantum Wires: Very limited phase space for scattering. Mean free paths as large as 1.6µm. Lower resistivity E Conventional metal wires : Backscattering through a series of small angle scatterings. Mean free paths ~ 30nm. Higher resistivity Potential Candidates for GSI Interconnects. 21 Can Optical Interconnects help? On-Chip Optical Interconnects 40Tb/s Optical I/O1024 x OC Tb/s On-ChipBisection BW For Clock Distribution P Chip-to-chip Optical Interconnects modulator chip grating grating receiver chip Signal wires Reduce delay Increase bandwidth incoming short Clock distribution laser pulse Reduce jitter and skew I/O with very high bandwidth Reduce power 22 fiber 11

12 Summary: Technology Progression Bulk CMOS Cu interconnect Low-k ILD FD SOI CMOS Wafer bonding Crystallization Double-Gate CMOS 3D, heterogeneous integration Optical interconnect Nanotechnology Metal gate High k gate dielectric Strained Si Ge channel Detectors, lasers, QWM, waveguides Si (tensile) Si 0.8Ge 0.2 Si 1-xGe x Self-assembly Nanotube Si Interconnects and contacts for nanodevices Molecular devices 100 nm Feature Size 23 2 nm 12

Enhanced Mobility CMOS

Enhanced Mobility CMOS Enhanced Mobility CMOS Judy L. Hoyt I. Åberg, C. Ni Chléirigh, O. Olubuyide, J. Jung, S. Yu, E.A. Fitzgerald, and D.A. Antoniadis Microsystems Technology Laboratory MIT, Cambridge, MA 02139 Acknowledge

More information

Scaling Issues in Planar FET: Dual Gate FET and FinFETs

Scaling Issues in Planar FET: Dual Gate FET and FinFETs Scaling Issues in Planar FET: Dual Gate FET and FinFETs Lecture 12 Dr. Amr Bayoumi Fall 2014 Advanced Devices (EC760) Arab Academy for Science and Technology - Cairo 1 Outline Scaling Issues for Planar

More information

A final review session will be offered on Thursday, May 10 from 10AM to 12noon in 521 Cory (the Hogan Room).

A final review session will be offered on Thursday, May 10 from 10AM to 12noon in 521 Cory (the Hogan Room). A final review session will be offered on Thursday, May 10 from 10AM to 12noon in 521 Cory (the Hogan Room). The Final Exam will take place from 12:30PM to 3:30PM on Saturday May 12 in 60 Evans.» All of

More information

High Mobility Materials and Novel Device Structures for High Performance Nanoscale MOSFETs

High Mobility Materials and Novel Device Structures for High Performance Nanoscale MOSFETs High Mobility Materials and Novel Device Structures for High Performance Nanoscale MOSFETs Prof. (Dr.) Tejas Krishnamohan Department of Electrical Engineering Stanford University, CA & Intel Corporation

More information

EECS130 Integrated Circuit Devices

EECS130 Integrated Circuit Devices EECS130 Integrated Circuit Devices Professor Ali Javey 10/30/2007 MOSFETs Lecture 4 Reading: Chapter 17, 19 Announcements The next HW set is due on Thursday. Midterm 2 is next week!!!! Threshold and Subthreshold

More information

MOSFET: Introduction

MOSFET: Introduction E&CE 437 Integrated VLSI Systems MOS Transistor 1 of 30 MOSFET: Introduction Metal oxide semiconductor field effect transistor (MOSFET) or MOS is widely used for implementing digital designs Its major

More information

CMPEN 411 VLSI Digital Circuits. Lecture 03: MOS Transistor

CMPEN 411 VLSI Digital Circuits. Lecture 03: MOS Transistor CMPEN 411 VLSI Digital Circuits Lecture 03: MOS Transistor Kyusun Choi [Adapted from Rabaey s Digital Integrated Circuits, Second Edition, 2003 J. Rabaey, A. Chandrakasan, B. Nikolic] CMPEN 411 L03 S.1

More information

L ECE 4211 UConn F. Jain Scaling Laws for NanoFETs Chapter 10 Logic Gate Scaling

L ECE 4211 UConn F. Jain Scaling Laws for NanoFETs Chapter 10 Logic Gate Scaling L13 04202017 ECE 4211 UConn F. Jain Scaling Laws for NanoFETs Chapter 10 Logic Gate Scaling Scaling laws: Generalized scaling (GS) p. 610 Design steps p.613 Nanotransistor issues (page 626) Degradation

More information

CHAPTER 5 EFFECT OF GATE ELECTRODE WORK FUNCTION VARIATION ON DC AND AC PARAMETERS IN CONVENTIONAL AND JUNCTIONLESS FINFETS

CHAPTER 5 EFFECT OF GATE ELECTRODE WORK FUNCTION VARIATION ON DC AND AC PARAMETERS IN CONVENTIONAL AND JUNCTIONLESS FINFETS 98 CHAPTER 5 EFFECT OF GATE ELECTRODE WORK FUNCTION VARIATION ON DC AND AC PARAMETERS IN CONVENTIONAL AND JUNCTIONLESS FINFETS In this chapter, the effect of gate electrode work function variation on DC

More information

ELEN0037 Microelectronic IC Design. Prof. Dr. Michael Kraft

ELEN0037 Microelectronic IC Design. Prof. Dr. Michael Kraft ELEN0037 Microelectronic IC Design Prof. Dr. Michael Kraft Lecture 2: Technological Aspects Technology Passive components Active components CMOS Process Basic Layout Scaling CMOS Technology Integrated

More information

Chapter 5 MOSFET Theory for Submicron Technology

Chapter 5 MOSFET Theory for Submicron Technology Chapter 5 MOSFET Theory for Submicron Technology Short channel effects Other small geometry effects Parasitic components Velocity saturation/overshoot Hot carrier effects ** Majority of these notes are

More information

Thin Film Transistors (TFT)

Thin Film Transistors (TFT) Thin Film Transistors (TFT) a-si TFT - α-si:h (Hydrogenated amorphous Si) deposited with a PECVD system (low temp. process) replaces the single crystal Si substrate. - Inverted staggered structure with

More information

MOS Transistor I-V Characteristics and Parasitics

MOS Transistor I-V Characteristics and Parasitics ECEN454 Digital Integrated Circuit Design MOS Transistor I-V Characteristics and Parasitics ECEN 454 Facts about Transistors So far, we have treated transistors as ideal switches An ON transistor passes

More information

The Devices. Digital Integrated Circuits A Design Perspective. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic. July 30, 2002

The Devices. Digital Integrated Circuits A Design Perspective. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic. July 30, 2002 Digital Integrated Circuits A Design Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic The Devices July 30, 2002 Goal of this chapter Present intuitive understanding of device operation Introduction

More information

Tri-Gate Fully-Depleted CMOS Transistors: Fabrication, Design and Layout

Tri-Gate Fully-Depleted CMOS Transistors: Fabrication, Design and Layout Tri-Gate Fully-Depleted CMOS Transistors: Fabrication, Design and Layout B.Doyle, J.Kavalieros, T. Linton, R.Rios B.Boyanov, S.Datta, M. Doczy, S.Hareland, B. Jin, R.Chau Logic Technology Development Intel

More information

MOSFET SCALING ECE 663

MOSFET SCALING ECE 663 MOSFET SCALING Scaling of switches Moore s Law economics Moore s Law - #DRAM Bits per chip doubles every 18 months ~5% bigger chips/wafers ~5% design improvements ~50 % Lithography ability to print smaller

More information

Objective and Outline. Acknowledgement. Objective: Power Components. Outline: 1) Acknowledgements. Section 4: Power Components

Objective and Outline. Acknowledgement. Objective: Power Components. Outline: 1) Acknowledgements. Section 4: Power Components Objective: Power Components Outline: 1) Acknowledgements 2) Objective and Outline 1 Acknowledgement This lecture note has been obtained from similar courses all over the world. I wish to thank all the

More information

MOS Transistor Properties Review

MOS Transistor Properties Review MOS Transistor Properties Review 1 VLSI Chip Manufacturing Process Photolithography: transfer of mask patterns to the chip Diffusion or ion implantation: selective doping of Si substrate Oxidation: SiO

More information

Stretching the Barriers An analysis of MOSFET Scaling. Presenters (in order) Zeinab Mousavi Stephanie Teich-McGoldrick Aseem Jain Jaspreet Wadhwa

Stretching the Barriers An analysis of MOSFET Scaling. Presenters (in order) Zeinab Mousavi Stephanie Teich-McGoldrick Aseem Jain Jaspreet Wadhwa Stretching the Barriers An analysis of MOSFET Scaling Presenters (in order) Zeinab Mousavi Stephanie Teich-McGoldrick Aseem Jain Jaspreet Wadhwa Why Small? Higher Current Lower Gate Capacitance Higher

More information

The Devices: MOS Transistors

The Devices: MOS Transistors The Devices: MOS Transistors References: Semiconductor Device Fundamentals, R. F. Pierret, Addison-Wesley Digital Integrated Circuits: A Design Perspective, J. Rabaey et.al. Prentice Hall NMOS Transistor

More information

Technische Universität Graz. Institute of Solid State Physics. 11. MOSFETs

Technische Universität Graz. Institute of Solid State Physics. 11. MOSFETs Technische Universität Graz Institute of Solid State Physics 11. MOSFETs Dec. 12, 2018 Gradual channel approximation accumulation depletion inversion http://lampx.tugraz.at/~hadley/psd/l10/gradualchannelapprox.php

More information

ESE 570: Digital Integrated Circuits and VLSI Fundamentals

ESE 570: Digital Integrated Circuits and VLSI Fundamentals ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 4: January 23, 2018 MOS Transistor Theory, MOS Model Penn ESE 570 Spring 2018 Khanna Lecture Outline! CMOS Process Enhancements! Semiconductor

More information

Chapter 3 Basics Semiconductor Devices and Processing

Chapter 3 Basics Semiconductor Devices and Processing Chapter 3 Basics Semiconductor Devices and Processing Hong Xiao, Ph. D. www2.austin.cc.tx.us/hongxiao/book.htm Hong Xiao, Ph. D. www2.austin.cc.tx.us/hongxiao/book.htm 1 Objectives Identify at least two

More information

MOS Transistor Theory

MOS Transistor Theory CHAPTER 3 MOS Transistor Theory Outline 2 1. Introduction 2. Ideal I-V Characteristics 3. Nonideal I-V Effects 4. C-V Characteristics 5. DC Transfer Characteristics 6. Switch-level RC Delay Models MOS

More information

III-V CMOS: What have we learned from HEMTs? J. A. del Alamo, D.-H. Kim 1, T.-W. Kim, D. Jin, and D. A. Antoniadis

III-V CMOS: What have we learned from HEMTs? J. A. del Alamo, D.-H. Kim 1, T.-W. Kim, D. Jin, and D. A. Antoniadis III-V CMOS: What have we learned from HEMTs? J. A. del Alamo, D.-H. Kim 1, T.-W. Kim, D. Jin, and D. A. Antoniadis Microsystems Technology Laboratories, MIT 1 presently with Teledyne Scientific 23rd International

More information

ENEE 359a Digital VLSI Design

ENEE 359a Digital VLSI Design SLIDE 1 ENEE 359a Digital VLSI Design & Logical Effort Prof. blj@ece.umd.edu Credit where credit is due: Slides contain original artwork ( Jacob 2004) as well as material taken liberally from Irwin & Vijay

More information

The Future of CMOS. David Pulfrey. CHRONOLOGY of the FET. Lecture Lilienfeld s patent (BG FET) 1965 Commercialization (Fairchild)

The Future of CMOS. David Pulfrey. CHRONOLOGY of the FET. Lecture Lilienfeld s patent (BG FET) 1965 Commercialization (Fairchild) The Future of CMOS David Pulfrey 1 CHRONOLOGY of the FET 1933 Lilienfeld s patent (BG FET) 1965 Commercialization (Fairchild) 1991 The most abundant object made by mankind (C.T. Sah) 2003 The 10 nm FET

More information

S=0.7 [0.5x per 2 nodes] ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems. Today. Scaling ITRS Roadmap

S=0.7 [0.5x per 2 nodes] ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems. Today. Scaling ITRS Roadmap ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 15: October 4, 2013 Scaling Today VLSI Scaling Trends/Disciplines Effects Alternatives (cheating) 1 2 Scaling ITRS Roadmap

More information

Digital Integrated Circuits A Design Perspective. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic. The Devices. July 30, Devices.

Digital Integrated Circuits A Design Perspective. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic. The Devices. July 30, Devices. Digital Integrated Circuits A Design Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic The July 30, 2002 1 Goal of this chapter Present intuitive understanding of device operation Introduction

More information

Lecture #27. The Short Channel Effect (SCE)

Lecture #27. The Short Channel Effect (SCE) Lecture #27 ANNOUNCEMENTS Design Project: Your BJT design should meet the performance specifications to within 10% at both 300K and 360K. ( β dc > 45, f T > 18 GHz, V A > 9 V and V punchthrough > 9 V )

More information

EE115C Winter 2017 Digital Electronic Circuits. Lecture 3: MOS RC Model, CMOS Manufacturing

EE115C Winter 2017 Digital Electronic Circuits. Lecture 3: MOS RC Model, CMOS Manufacturing EE115C Winter 2017 Digital Electronic Circuits Lecture 3: MOS RC Model, CMOS Manufacturing Agenda MOS Transistor: RC Model (pp. 104-113) S R on D CMOS Manufacturing Process (pp. 36-46) S S C GS G G C GD

More information

Introduction and Background

Introduction and Background Analog CMOS Integrated Circuit Design Introduction and Background Dr. Jawdat Abu-Taha Department of Electrical and Computer Engineering Islamic University of Gaza jtaha@iugaza.edu.ps 1 Marking Assignments

More information

CMOS Scaling. Two motivations to scale down. Faster transistors, both digital and analog. To pack more functionality per area. Lower the cost!

CMOS Scaling. Two motivations to scale down. Faster transistors, both digital and analog. To pack more functionality per area. Lower the cost! Two motivations to scale down CMOS Scaling Faster transistors, both digital and analog To pack more functionality per area. Lower the cost! (which makes (some) physical sense) Scale all dimensions and

More information

Nanometer Transistors and Their Models. Jan M. Rabaey

Nanometer Transistors and Their Models. Jan M. Rabaey Nanometer Transistors and Their Models Jan M. Rabaey Chapter Outline Nanometer transistor behavior and models Sub-threshold currents and leakage Variability Device and technology innovations Nanometer

More information

A Multi-Gate CMOS Compact Model BSIMMG

A Multi-Gate CMOS Compact Model BSIMMG A Multi-Gate CMOS Compact Model BSIMMG Darsen Lu, Sriramkumar Venugopalan, Tanvir Morshed, Yogesh Singh Chauhan, Chung-Hsun Lin, Mohan Dunga, Ali Niknejad and Chenming Hu University of California, Berkeley

More information

Recent Development of FinFET Technology for CMOS Logic and Memory

Recent Development of FinFET Technology for CMOS Logic and Memory Recent Development of FinFET Technology for CMOS Logic and Memory Chung-Hsun Lin EECS Department University of California at Berkeley Why FinFET Outline FinFET process Unique features of FinFET Mobility,

More information

Ultimately Scaled CMOS: DG FinFETs?

Ultimately Scaled CMOS: DG FinFETs? Ultimately Scaled CMOS: DG FinFETs? Jerry G. Fossum SOI Group Department of Electrical and Computer Engineering University of Florida Gainesville, FL 32611-6130 J. G. Fossum / 1 Outline Introduction -

More information

Multiple Gate CMOS and Beyond

Multiple Gate CMOS and Beyond Multiple CMOS and Beyond Dept. of EECS, KAIST Yang-Kyu Choi Outline 1. Ultimate Scaling of MOSFETs - 3nm Nanowire FET - 8nm Non-Volatile Memory Device 2. Multiple Functions of MOSFETs 3. Summary 2 CMOS

More information

Nanoscale CMOS Design Issues

Nanoscale CMOS Design Issues Nanoscale CMOS Design Issues Jaydeep P. Kulkarni Assistant Professor, ECE Department The University of Texas at Austin jaydeep@austin.utexas.edu Fall, 2017, VLSI-1 Class Transistor I-V Review Agenda Non-ideal

More information

Lecture 5: CMOS Transistor Theory

Lecture 5: CMOS Transistor Theory Lecture 5: CMOS Transistor Theory Slides courtesy of Deming Chen Slides based on the initial set from David Harris CMOS VLSI Design Outline q q q q q q q Introduction MOS Capacitor nmos I-V Characteristics

More information

Section 12: Intro to Devices

Section 12: Intro to Devices Section 12: Intro to Devices Extensive reading materials on reserve, including Robert F. Pierret, Semiconductor Device Fundamentals EE143 Ali Javey Bond Model of Electrons and Holes Si Si Si Si Si Si Si

More information

The Devices. Digital Integrated Circuits A Design Perspective. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic. July 30, 2002

The Devices. Digital Integrated Circuits A Design Perspective. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic. July 30, 2002 igital Integrated Circuits A esign Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic The evices July 30, 2002 Goal of this chapter Present intuitive understanding of device operation Introduction

More information

ECE520 VLSI Design. Lecture 8: Interconnect Manufacturing and Modeling. Payman Zarkesh-Ha

ECE520 VLSI Design. Lecture 8: Interconnect Manufacturing and Modeling. Payman Zarkesh-Ha ECE520 VLSI Design Lecture 8: Interconnect Manufacturing and Modeling Payman Zarkesh-Ha Office: ECE Bldg. 230B Office hours: Wednesday 2:00-3:00PM or by appointment E-mail: pzarkesh@unm.edu Slide: 1 Review

More information

MSE 310/ECE 340: Electrical Properties of Materials Fall 2014 Department of Materials Science and Engineering Boise State University

MSE 310/ECE 340: Electrical Properties of Materials Fall 2014 Department of Materials Science and Engineering Boise State University MSE 310/ECE 340: Electrical Properties of Materials Fall 2014 Department of Materials Science and Engineering Boise State University Practice Final Exam 1 Read the questions carefully Label all figures

More information

Microsystems Technology Laboratories, MIT. Teledyne Scientific Company (TSC)

Microsystems Technology Laboratories, MIT. Teledyne Scientific Company (TSC) Extraction of Virtual-Source Injection Velocity in sub-100 nm III-V HFETs 1,2) D.-H. Kim, 1) J. A. del Alamo, 1) D. A. Antoniadis and 2) B. Brar 1) Microsystems Technology Laboratories, MIT 2) Teledyne

More information

Characteristics of MOSFET with Non-overlapped Source-Drain to Gate

Characteristics of MOSFET with Non-overlapped Source-Drain to Gate IEICE TRANS. ELECTRON., VOL.E85 C, NO.5 MAY 2002 1079 PAPER Special Issue on Advanced Sub-0.1 µm CMOS Devices Characteristics of MOSFET with Non-overlapped Source-Drain to Gate Hyunjin LEE a), Nonmember,

More information

Comparison of Ultra-Thin InAs and InGaAs Quantum Wells and Ultra-Thin-Body Surface-Channel MOSFETs

Comparison of Ultra-Thin InAs and InGaAs Quantum Wells and Ultra-Thin-Body Surface-Channel MOSFETs Comparison of Ultra-Thin InAs and InGaAs Quantum Wells and Ultra-Thin-Body Surface-Channel MOSFETs Cheng-Ying Huang 1, Sanghoon Lee 1, Evan Wilson 3, Pengyu Long 3, Michael Povolotskyi 3, Varistha Chobpattana

More information

MOS Transistor Theory MOSFET Symbols Current Characteristics of MOSFET. MOS Symbols and Characteristics. nmos Enhancement Transistor

MOS Transistor Theory MOSFET Symbols Current Characteristics of MOSFET. MOS Symbols and Characteristics. nmos Enhancement Transistor MOS Transistor Theory MOSFET Symbols Current Characteristics of MOSFET Calculation of t and Important 2 nd Order Effects SmallSignal Signal MOSFET Model Summary Material from: CMOS LSI Design By Weste

More information

Homework 2 due on Wednesday Quiz #2 on Wednesday Midterm project report due next Week (4 pages)

Homework 2 due on Wednesday Quiz #2 on Wednesday Midterm project report due next Week (4 pages) EE241 - Spring 2013 Advanced Digital Integrated Circuits Lecture 12: SRAM Design ECC Timing Announcements Homework 2 due on Wednesday Quiz #2 on Wednesday Midterm project report due next Week (4 pages)

More information

Self-study problems and questions Processing and Device Technology, FFF110/FYSD13

Self-study problems and questions Processing and Device Technology, FFF110/FYSD13 Self-study problems and questions Processing and Device Technology, FFF110/FYSD13 Version 2016_01 In addition to the problems discussed at the seminars and at the lectures, you can use this set of problems

More information

ESE 570: Digital Integrated Circuits and VLSI Fundamentals

ESE 570: Digital Integrated Circuits and VLSI Fundamentals ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 4: January 29, 2019 MOS Transistor Theory, MOS Model Penn ESE 570 Spring 2019 Khanna Lecture Outline! CMOS Process Enhancements! Semiconductor

More information

Device Models (PN Diode, MOSFET )

Device Models (PN Diode, MOSFET ) Device Models (PN Diode, MOSFET ) Instructor: Steven P. Levitan steve@ece.pitt.edu TA: Gayatri Mehta, José Martínez Book: Digital Integrated Circuits: A Design Perspective; Jan Rabaey Lab Notes: Handed

More information

! CMOS Process Enhancements. ! Semiconductor Physics. " Band gaps. " Field Effects. ! MOS Physics. " Cut-off. " Depletion.

! CMOS Process Enhancements. ! Semiconductor Physics.  Band gaps.  Field Effects. ! MOS Physics.  Cut-off.  Depletion. ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 4: January 3, 018 MOS Transistor Theory, MOS Model Lecture Outline! CMOS Process Enhancements! Semiconductor Physics " Band gaps " Field Effects!

More information

Study of Carrier Transport in Strained and Unstrained SOI Tri-gate and Omega-gate Si Nanowire MOSFETs

Study of Carrier Transport in Strained and Unstrained SOI Tri-gate and Omega-gate Si Nanowire MOSFETs 42nd ESSDERC, Bordeaux, France, 17-21 Sept. 2012 A2L-E, High Mobility Devices, 18 Sept. Study of Carrier Transport in Strained and Unstrained SOI Tri-gate and Omega-gate Si Nanowire MOSFETs M. Koyama 1,4,

More information

EE382M-14 CMOS Analog Integrated Circuit Design

EE382M-14 CMOS Analog Integrated Circuit Design EE382M-14 CMOS Analog Integrated Circuit Design Lecture 3, MOS Capacitances, Passive Components, and Layout of Analog Integrated Circuits MOS Capacitances Type of MOS transistor capacitors Depletion capacitance

More information

MOS Transistors. Prof. Krishna Saraswat. Department of Electrical Engineering Stanford University Stanford, CA

MOS Transistors. Prof. Krishna Saraswat. Department of Electrical Engineering Stanford University Stanford, CA MOS Transistors Prof. Krishna Saraswat Department of Electrical Engineering S Stanford, CA 94305 saraswat@stanford.edu 1 1930: Patent on the Field-Effect Transistor! Julius Lilienfeld filed a patent describing

More information

Subthreshold and scaling of PtSi Schottky barrier MOSFETs

Subthreshold and scaling of PtSi Schottky barrier MOSFETs Superlattices and Microstructures, Vol. 28, No. 5/6, 2000 doi:10.1006/spmi.2000.0954 Available online at http://www.idealibrary.com on Subthreshold and scaling of PtSi Schottky barrier MOSFETs L. E. CALVET,

More information

The Pennsylvania State University. Kurt J. Lesker Company. North Carolina State University. Taiwan Semiconductor Manufacturing Company 1

The Pennsylvania State University. Kurt J. Lesker Company. North Carolina State University. Taiwan Semiconductor Manufacturing Company 1 Enhancement Mode Strained (1.3%) Germanium Quantum Well FinFET (W fin =20nm) with High Mobility (μ Hole =700 cm 2 /Vs), Low EOT (~0.7nm) on Bulk Silicon Substrate A. Agrawal 1, M. Barth 1, G. B. Rayner

More information

Electronics with 2D Crystals: Scaling extender, or harbinger of new functions?

Electronics with 2D Crystals: Scaling extender, or harbinger of new functions? Electronics with 2D Crystals: Scaling extender, or harbinger of new functions? 1 st Workshop on Data Abundant Systems Technology Stanford, April 2014 Debdeep Jena (djena@nd.edu) Electrical Engineering,

More information

EE105 Fall 2014 Microelectronic Devices and Circuits. NMOS Transistor Capacitances: Saturation Region

EE105 Fall 2014 Microelectronic Devices and Circuits. NMOS Transistor Capacitances: Saturation Region EE105 Fall 014 Microelectronic Devices and Circuits Prof. Ming C. Wu wu@eecs.berkeley.edu 511 Sutardja Dai Hall (SDH) 1 NMOS Transistor Capacitances: Saturation Region Drain no longer connected to channel

More information

Journal of Electron Devices, Vol. 18, 2013, pp JED [ISSN: ]

Journal of Electron Devices, Vol. 18, 2013, pp JED [ISSN: ] DrainCurrent-Id in linearscale(a/um) Id in logscale Journal of Electron Devices, Vol. 18, 2013, pp. 1582-1586 JED [ISSN: 1682-3427 ] SUITABILITY OF HIGH-k GATE DIELECTRICS ON THE DEVICE PERFORMANCE AND

More information

Ultra-Scaled InAs HEMTs

Ultra-Scaled InAs HEMTs Performance Analysis of Ultra-Scaled InAs HEMTs Neerav Kharche 1, Gerhard Klimeck 1, Dae-Hyun Kim 2,3, Jesús. A. del Alamo 2, and Mathieu Luisier 1 1 Network for Computational ti Nanotechnology and Birck

More information

CMOS INVERTER. Last Lecture. Metrics for qualifying digital circuits. »Cost» Reliability» Speed (delay)»performance

CMOS INVERTER. Last Lecture. Metrics for qualifying digital circuits. »Cost» Reliability» Speed (delay)»performance CMOS INVERTER Last Lecture Metrics for qualifying digital circuits»cost» Reliability» Speed (delay)»performance 1 Today s lecture The CMOS inverter at a glance An MOS transistor model for manual analysis

More information

Digital Integrated Circuits A Design Perspective

Digital Integrated Circuits A Design Perspective Semiconductor Memories Adapted from Chapter 12 of Digital Integrated Circuits A Design Perspective Jan M. Rabaey et al. Copyright 2003 Prentice Hall/Pearson Outline Memory Classification Memory Architectures

More information

LECTURE 3 MOSFETS II. MOS SCALING What is Scaling?

LECTURE 3 MOSFETS II. MOS SCALING What is Scaling? LECTURE 3 MOSFETS II Lecture 3 Goals* * Understand constant field and constant voltage scaling and their effects. Understand small geometry effects for MOS transistors and their implications modeling and

More information

Lecture 040 Integrated Circuit Technology - II (5/11/03) Page ECE Frequency Synthesizers P.E. Allen

Lecture 040 Integrated Circuit Technology - II (5/11/03) Page ECE Frequency Synthesizers P.E. Allen Lecture 040 Integrated Circuit Technology - II (5/11/03) Page 040-1 LECTURE 040 INTEGRATED CIRCUIT TECHNOLOGY - II (Reference [7,8]) Objective The objective of this presentation is: 1.) Illustrate and

More information

Lecture 25. Semiconductor Memories. Issues in Memory

Lecture 25. Semiconductor Memories. Issues in Memory Lecture 25 Semiconductor Memories Issues in Memory Memory Classification Memory Architectures TheMemoryCore Periphery 1 Semiconductor Memory Classification RWM NVRWM ROM Random Access Non-Random Access

More information

A 20 nm gate-length ultra-thin body p-mosfet with silicide source/drain

A 20 nm gate-length ultra-thin body p-mosfet with silicide source/drain Superlattices and Microstructures, Vol. 28, No. 5/6, 2000 doi:10.1006/spmi.2000.0947 Available online at http://www.idealibrary.com on A 20 nm gate-length ultra-thin body p-mosfet with silicide source/drain

More information

Long Channel MOS Transistors

Long Channel MOS Transistors Long Channel MOS Transistors The theory developed for MOS capacitor (HO #2) can be directly extended to Metal-Oxide-Semiconductor Field-Effect transistors (MOSFET) by considering the following structure:

More information

High Mobility Channel Impact On Device Performance High mobility materials (advantages) High Mobility - Low Leakage

High Mobility Channel Impact On Device Performance High mobility materials (advantages) High Mobility - Low Leakage High Mobility Channel Impact On Device Performance High mobility materials (advantages) High mobility materials (disadvantages) energy Low m* transport Increasing µ brings us closer to the ballistic limit

More information

Semiconductor Physics Problems 2015

Semiconductor Physics Problems 2015 Semiconductor Physics Problems 2015 Page and figure numbers refer to Semiconductor Devices Physics and Technology, 3rd edition, by SM Sze and M-K Lee 1. The purest semiconductor crystals it is possible

More information

The Critical Role of Quantum Capacitance in Compact Modeling of Nano-Scaled and Nanoelectronic Devices

The Critical Role of Quantum Capacitance in Compact Modeling of Nano-Scaled and Nanoelectronic Devices The Critical Role of Quantum Capacitance in Compact Modeling of Nano-Scaled and Nanoelectronic Devices Zhiping Yu and Jinyu Zhang Institute of Microelectronics Tsinghua University, Beijing, China yuzhip@tsinghua.edu.cn

More information

Fig. 1 CMOS Transistor Circuits (a) Inverter Out = NOT In, (b) NOR-gate C = NOT (A or B)

Fig. 1 CMOS Transistor Circuits (a) Inverter Out = NOT In, (b) NOR-gate C = NOT (A or B) 1 Introduction to Transistor-Level Logic Circuits 1 By Prawat Nagvajara At the transistor level of logic circuits, transistors operate as switches with the logic variables controlling the open or closed

More information

Future Trends in Microelectronics Impact on Detector Readout. Paul O Connor

Future Trends in Microelectronics Impact on Detector Readout. Paul O Connor Future Trends in Microelectronics Impact on Detector Readout Paul O Connor Outline CMOS Technology Scaling Analog Circuits Radiation Effects Cost Detector Development Symposium Paul O'Connor BNL April

More information

Application of High-κ Gate Dielectrics and Metal Gate Electrodes to enable Silicon and Non-Silicon Logic Nanotechnology

Application of High-κ Gate Dielectrics and Metal Gate Electrodes to enable Silicon and Non-Silicon Logic Nanotechnology Application of High-κ Gate Dielectrics and Metal Gate Electrodes to enable Silicon and Non-Silicon Logic Nanotechnology Robert Chau, Justin Brask, Suman Datta, Gilbert Dewey, Mark Doczy, Brian Doyle, Jack

More information

Fig The electron mobility for a-si and poly-si TFT.

Fig The electron mobility for a-si and poly-si TFT. Fig. 1-1-1 The electron mobility for a-si and poly-si TFT. Fig. 1-1-2 The aperture ratio for a-si and poly-si TFT. 33 Fig. 1-2-1 All kinds defect well. (a) is the Dirac well. (b) is the repulsive Columbic

More information

Prospects for Ge MOSFETs

Prospects for Ge MOSFETs Prospects for Ge MOSFETs Sematech Workshop December 4, 2005 Dimitri A. Antoniadis Microsystems Technology Laboratories MIT Sematech Workshop 2005 1 Channel Transport - I D I D =WQ i (x 0 )v xo v xo : carrier

More information

Device Models (PN Diode, MOSFET )

Device Models (PN Diode, MOSFET ) Device Models (PN Diode, MOSFET ) Instructor: Steven P. Levitan steve@ece.pitt.edu TA: Gayatri Mehta, José Martínez Book: Digital Integrated Circuits: A Design Perspective; Jan Rabaey Lab Notes: Handed

More information

The Devices. Devices

The Devices. Devices The The MOS Transistor Gate Oxyde Gate Source n+ Polysilicon Drain n+ Field-Oxyde (SiO 2 ) p-substrate p+ stopper Bulk Contact CROSS-SECTION of NMOS Transistor Cross-Section of CMOS Technology MOS transistors

More information

CMOS Transistors, Gates, and Wires

CMOS Transistors, Gates, and Wires CMOS Transistors, Gates, and Wires Should the hardware abstraction layers make today s lecture irrelevant? pplication R P C W / R W C W / 6.375 Complex Digital Systems Christopher atten February 5, 006

More information

CMPEN 411 VLSI Digital Circuits Spring 2012

CMPEN 411 VLSI Digital Circuits Spring 2012 CMPEN 411 VLSI Digital Circuits Spring 2012 Lecture 09: Resistance & Inverter Dynamic View [Adapted from Rabaey s Digital Integrated Circuits, Second Edition, 2003 J. Rabaey, A. Chandrakasan, B. Nikolic]

More information

Simple and accurate modeling of the 3D structural variations in FinFETs

Simple and accurate modeling of the 3D structural variations in FinFETs Simple and accurate modeling of the 3D structural variations in FinFETs Donghu Kim Electrical Engineering Program Graduate school of UNIST 2013 Simple and accurate modeling of the 3D structural variations

More information

Lecture 15 OUTLINE. MOSFET structure & operation (qualitative) Review of electrostatics The (N)MOS capacitor

Lecture 15 OUTLINE. MOSFET structure & operation (qualitative) Review of electrostatics The (N)MOS capacitor Lecture 15 OUTLINE MOSFET structure & operation (qualitative) Review of electrostatics The (N)MOS capacitor Electrostatics t ti Charge vs. voltage characteristic Reading: Chapter 6.1 6.2.1 EE105 Fall 2007

More information

VLSI Design The MOS Transistor

VLSI Design The MOS Transistor VLSI Design The MOS Transistor Frank Sill Torres Universidade Federal de Minas Gerais (UFMG), Brazil VLSI Design: CMOS Technology 1 Outline Introduction MOS Capacitor nmos I-V Characteristics pmos I-V

More information

How a single defect can affect silicon nano-devices. Ted Thorbeck

How a single defect can affect silicon nano-devices. Ted Thorbeck How a single defect can affect silicon nano-devices Ted Thorbeck tedt@nist.gov The Big Idea As MOS-FETs continue to shrink, single atomic scale defects are beginning to affect device performance Gate Source

More information

Self-Aligned InGaAs FinFETs with 5-nm Fin-Width and 5-nm Gate-Contact Separation

Self-Aligned InGaAs FinFETs with 5-nm Fin-Width and 5-nm Gate-Contact Separation Self-Aligned InGaAs FinFETs with 5-nm Fin-Width and 5-nm Gate-Contact Separation Alon Vardi, Lisa Kong, Wenjie Lu, Xiaowei Cai, Xin Zhao, Jesús Grajal* and Jesús A. del Alamo Microsystems Technology Laboratories,

More information

Components Research, TMG Intel Corporation *QinetiQ. Contact:

Components Research, TMG Intel Corporation *QinetiQ. Contact: 1 High-Performance 4nm Gate Length InSb P-Channel Compressively Strained Quantum Well Field Effect Transistors for Low-Power (V CC =.5V) Logic Applications M. Radosavljevic,, T. Ashley*, A. Andreev*, S.

More information

EE 5211 Analog Integrated Circuit Design. Hua Tang Fall 2012

EE 5211 Analog Integrated Circuit Design. Hua Tang Fall 2012 EE 5211 Analog Integrated Circuit Design Hua Tang Fall 2012 Today s topic: 1. Introduction to Analog IC 2. IC Manufacturing (Chapter 2) Introduction What is Integrated Circuit (IC) vs discrete circuits?

More information

The Devices. Jan M. Rabaey

The Devices. Jan M. Rabaey The Devices Jan M. Rabaey Goal of this chapter Present intuitive understanding of device operation Introduction of basic device equations Introduction of models for manual analysis Introduction of models

More information

DIFFUSION - Chapter 7

DIFFUSION - Chapter 7 DIFFUSION - Chapter 7 Doping profiles determine many short-channel characteristics in MOS devices. Resistance impacts drive current. Scaling implies all lateral and vertical dimensions scale by the same

More information

TCAD Modeling of Stress Impact on Performance and Reliability

TCAD Modeling of Stress Impact on Performance and Reliability TCAD Modeling of Stress Impact on Performance and Reliability Xiaopeng Xu TCAD R&D, Synopsys March 16, 2010 SEMATECH Workshop on Stress Management for 3D ICs using Through Silicon Vias 1 Outline Introduction

More information

MOS Transistor Theory

MOS Transistor Theory MOS Transistor Theory So far, we have viewed a MOS transistor as an ideal switch (digital operation) Reality: less than ideal EE 261 Krish Chakrabarty 1 Introduction So far, we have treated transistors

More information

ESE534: Computer Organization. Today. Why Care? Why Care. Scaling. Preclass

ESE534: Computer Organization. Today. Why Care? Why Care. Scaling. Preclass ESE534: Computer Organization Today Day 7: February 8, 2010 VLSI Scaling VLSI Scaling Rules Effects Historical/predicted scaling Variations (cheating) Limits 1 2 Why Care? In this game, we must be able

More information

EEC 118 Lecture #2: MOSFET Structure and Basic Operation. Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation

EEC 118 Lecture #2: MOSFET Structure and Basic Operation. Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation EEC 118 Lecture #2: MOSFET Structure and Basic Operation Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation Announcements Lab 1 this week, report due next week Bring

More information

Scaling of Interconnections

Scaling of Interconnections EE 311 Notes/Prof Saraswat of ions of Minimum Feature size and Chip Area 10 10 4 1 pr oduction 10 3 logic 0.1 de velopment 10 2 memor y 0.01 10 1 1970 1980 1990 2000 2010 1970 1980 1990 2000 2010 Year

More information

Low Frequency Noise in MoS 2 Negative Capacitance Field-effect Transistor

Low Frequency Noise in MoS 2 Negative Capacitance Field-effect Transistor Low Frequency Noise in MoS Negative Capacitance Field-effect Transistor Sami Alghamdi, Mengwei Si, Lingming Yang, and Peide D. Ye* School of Electrical and Computer Engineering Purdue University West Lafayette,

More information

Extensive reading materials on reserve, including

Extensive reading materials on reserve, including Section 12: Intro to Devices Extensive reading materials on reserve, including Robert F. Pierret, Semiconductor Device Fundamentals EE143 Ali Javey Bond Model of Electrons and Holes Si Si Si Si Si Si Si

More information

EE5311- Digital IC Design

EE5311- Digital IC Design EE5311- Digital IC Design Module 1 - The Transistor Janakiraman V Assistant Professor Department of Electrical Engineering Indian Institute of Technology Madras Chennai October 28, 2017 Janakiraman, IITM

More information

Lecture 9. Strained-Si Technology I: Device Physics

Lecture 9. Strained-Si Technology I: Device Physics Strain Analysis in Daily Life Lecture 9 Strained-Si Technology I: Device Physics Background Planar MOSFETs FinFETs Reading: Y. Sun, S. Thompson, T. Nishida, Strain Effects in Semiconductors, Springer,

More information

Circuits. L5: Fabrication and Layout -2 ( ) B. Mazhari Dept. of EE, IIT Kanpur. B. Mazhari, IITK. G-Number

Circuits. L5: Fabrication and Layout -2 ( ) B. Mazhari Dept. of EE, IIT Kanpur. B. Mazhari, IITK. G-Number EE610: CMOS Analog Circuits L5: Fabrication and Layout -2 (12.8.2013) B. Mazhari Dept. of EE, IIT Kanpur 44 Passive Components: Resistor Besides MOS transistors, sometimes one requires to implement passive

More information