طزاحي هذار اي VLSI فصل چ ارم: ا ر گز CMOS

Transcription

1 دانشگاه صنعتي اميركبير دانشكده مهندسي برق طزاحي هذار اي VLSI فصل چ ارم: ا ر گز CMOS جيذ ؿا چيا

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3 تزا شیست ر ا تقالي دس تشا ضیؼت س ا تما ی مذاس تاط خش جی چمذس اػت فشض و ي خش جی تشاتش VDD تاؿذ. دس ای حا ت چ V DD VGS=0<Vt اػت تشا ضیؼت س لطغ ی ؿ د. V DD پغ تشای آ ى تشا ضیؼت س س ؿ ت ا ذ حذاوثش تاط خش جی آ تشاتش VDD-Vt خ ا ذ ؿذ. ت ي د ي ی یي تشا ضیؼت س nmos مذاس طمی 1 سا خ ب ػث س ی د ذ.

4 هثال V DD V DD V s = V DD -V tn V DD V DD V DD V DD V DD -V tn V DD -V tn V DD -V tn V s = V tp V DD V DD -V tn V DD V DD -2V tn V SS

5 ار گز ایستا مذ خص ا تما ی سفتاس ایؼتا سفتاس پ یا تح ي ت ا ا شطی طشاحی تشای صشف و

6 هقذه : ار گز ایذ ال

7 هشخص اقعي تز ار گز

8 یادآ ري حاشی یش

9 پیاد ساسي تا ه طق CMOS ایستا V DD دس طك CMOS ایؼتا خش جی اس یه ؼيش ما تی ت VDD یا ص ي داسد. V in V out اس ش پای ذاس ای طمی تشويثی CMOS ایؼتا اػت. C L

10 آ الیش هزتث ا ل حالت ایستا V DD V DD V OL = 0 V OH = V DD R p V out = 1 V out = 0 R n V in = 0 V in = V DD

11 یضگی اي CMOS Full rail-to-rail swing high noise margins Logic levels not dependent upon the relative device sizes transistors can be minimum size ratioless Always a path to V dd or GND in steady state low output impedance (output resistance in k range) large fan-out (albeit with degraded performance) Extremely high input resistance (gate of MOS transistor is near perfect insulator) nearly zero steady-state input current No direct path steady-state between power and ground no static power dissipation Propagation delay function of load capacitance and resistance of transistors

12 ار گز ایستا مذ خص ا تما ی سفتاس ایؼتا سفتاس پ یا تح ي ت ا ا شطی طشاحی تشای صشف و

13 تحلیل عولکزد ار گز DC Response: V out vs. V in for a gate Ex: Inverter When V in = 0 -> V out = V DD When V in = V DD -> V out = 0 In between, V out depends on transistor size and current By KCL, must settle such that I dsn = I dsp We could solve equations But graphical solution gives more insight V in V DD I dsp I dsn V out

14 احی عولکزد تزا شیست ر ا دا ا ص ؼتی ا يشوثيش Current depends on region of transistor behavior For what V in and V out are nmos and pmos in Cutoff? Linear? Saturation?

15 دا ا ص ؼتی ا يشوثيش nmos Operation Cutoff Linear Saturated V gsn < V tn V in < V tn V gsn > V tn V in > V tn V dsn < V gsn V tn V out < V in - V tn V gsn > V tn V in > V tn V dsn > V gsn V tn V out > V in - V tn V DD V gsn = V in V dsn = V out V in I dsp I dsn V out

16 دا ا ص ؼتی ا يشوثيش pmos Operation Cutoff Linear Saturated V gsp > V tp V in > V DD + V tp V gsp < V tp V in < V DD + V tp V dsp > V gsp V tp V out > V in - V tp V gsp < V tp V in < V DD + V tp V dsp < V gsp V tp V out < V in - V tp V DD V gsp = V in - V DD V dsp = V out - V DD V tp < 0 V in I dsp I dsn V out

17 (NMOS) Review: Short Channel I-V Plot دا ا ص ؼتی ا يشوثيش X 10-4 V GS = 2.5V V GS = 2.0V V GS = 1.5V 0.5 V GS = 1.0V V DS (V) NMOS transistor, 0.25um, L d = 0.25um, W/L = 1.5, V DD = 2.5V, V T = 0.4V

18 (PMOS) Review: Short Channel I-V Plot دا ا ص ؼتی ا يشوثيش All polarities of all voltages and currents are reversed -2 V DS (V) V GS = -1.0V -0.2 V GS = -1.5V -0.4 V GS = -2.0V V GS = -2.5V -1 PMOS transistor, 0.25um, L d = 0.25um, W/L = 1.5, V DD = 2.5V, V T = -0.4V X 10-4

19 هشخص جزیاى لتاص تزا شیست ر ا در یک هح ر دا ا ص ؼتی ا يشوثيش Make pmos is wider than nmos such that b n = b p V gsn5 I dsn V gsn4 -V dsp V gsn3 V gsp1 V gsp2 -V DD 0 V DD V gsn2 V gsn1 V gsp3 V dsn V gsp4 -I dsp V gsp5

20 دا ا ص ؼتی ا يشوثيش تثذیل هختصات هشخص pmos I-V Want common coordinate set V in, V out, and I Dn I DSp = -I DSn V GSn = V in ; V GSp = V in - V DD V DSn = V out ; V DSp = V out - V DD I Dn Vout V in = 0 V in = 1.5 V in = 0 V in = 1.5 V GSp = -1 V GSp = -2.5 Mirror around x-axis V in = V DD + V GSp I Dn = -I Dp Horiz. shift over V DD V out = V DD + V DSp

21 دا ا ص ؼتی ا يشوثيش CMOS Inverter Load Lines PMOS V in = 0V X 10-4 NMOS V in = 2.5V V in = 0.5V 1.5 V in = 2.0V V in = 1.0V 1 V in = 2V 0.5 V in = 1.5V V in = 2.0V 0 V in = 2.5V V in = 1.5V V in = 1V V out (V) V in = 1.5V V in = 0.5V V in = 1.0V V in = 0.5V V in = 0V 0.25um, W/L n = 1.5, W/L p = 4.5, V DD = 2.5V, V Tn = 0.4V, V Tp = -0.4V

22 V out (V) دا ا ص ؼتی ا يشوثيش CMOS Inverter VTC NMOS off PMOS res NMOS sat PMOS res V in (V) NMOS sat PMOS sat NMOS res PMOS sat NMOS res PMOS off

23 Operating Regions Revisit transistor operating regions V DD V in V out Region nmos pmos A Cutoff Linear B Saturation Linear C Saturation Saturation D Linear Saturation E Linear Cutoff V out V DD A B 0 C D E V tn V DD /2 V DD +V tp V in V DD

24 نواحي كار وارونگر با ساختار متقارن k V ' n tn k ' p V tp

25 ار گز ایستا مذ خص ا تما ی سفتاس ایؼتا سفتاس پ یا تح ي ت ا ا شطی طشاحی تشای صشف و

26 ذف ذف اص تح ي ایؼتایی تح ي پاسا تش ای اػتحىا اس ش ظيش حاؿث یض تشسػی اثش تغييش پاسا تش ای اتؼادی س ی خص ا تما ی تشا ضیؼت س ی تاؿذ. ؼ ال ی خ ا ي حاؿي یض تيي خص ا تما ی تماس داؿت تاؿي

27 تحلیل رفتار ایستایي )Vin=Vout ( 1- تحلیل نقطه آستانه سوییچینگ VM V out NMOS off PMOS res NMOS sat PMOS res NMOS sat PMOS sat NMOS res PMOS sat فشض ی و ي ش د تشا ضیؼت س وا ا و تا دس احي اؿثاع ػشػت ؼت ذ. NMOS res PMOS off V in

28 تحلیل آستا س ییچی گ ا ش فشض و ي مذاس VDD ؼثت ت تاط آػتا تاط اؿثاع ػشػت تشا ضیؼت س ا تحذ وافی تضسي تاؿذ. تيا ش لذست دسای ؼثی pmos ؼثت ت nmos اػت. ا ش pmos ل یتش تاؿذ R VM اص VDD/2 صیادتش ی ؿ د ا ش NMOS ل یتش تاؿذ و تش ی ؿ د.

29 شزط تقارى V M = V DD /2 (to have comparable high and low noise margins), so want r 1

30 هثال آستا س ییچی گ دا ا ص ؼتی ا يشوثيش In our generic 0.25 micron CMOS process, using the process parameters from slide L03.25, a V DD = 2.5V, and a minimum size NMOS device ((W/L) n of 1.5) V T0 (V) (V 0.5 ) V DSAT (V) k (A/V 2 ) (V -1 ) NMOS x PMOS x (W/L) p 115 x ( /2) = x x = 3.5 (W/L) n -30 x ( /2) (W/L) p = 3.5 x 1.5 = 5.25 for a V M of 1.25V

31 شبيه سازی بستگي آستانه سویيچ كردن به ابعاد دا ا ص ؼتی ا يشوثيش ~ (W/L) p /(W/L) n Note: x-axis is semilog V M is relatively insensitive to variations in device ratio setting the ratio to 3, 2.5 and 2 gives V M s of 1.22V, 1.18V, and 1.13V Increasing the width of the PMOS moves V M towards V DD Increasing the width of the NMOS moves V M toward GND

32 تحلیل رفتار ایستایي 3 V OH = V DD 2 1 V M 2- تحلیل حاشیه نویش By definition, V IH and V IL are where dv out /dv in = -1 (= gain) NM H = V DD - V IH NM L = V IL - GND Approximating: V IH = V M - V M /g V IL = V M + (V DD - V M )/g V OL = GND 0 VIL V in A piece-wise linear approximation of VTC VIH So high gain in the transition region is very desirable

33 تحلیل تا تقزیة محاسثه گین در نقطه VM تا مشتك گزفتن اس معادله فوق نسثت ته Vin

34 تحلیل تا تقزیة تا جایگذاری V1 in تؼت ی ؿذیذ ت پاسا تش ای تى طی ظيش ضشیة ذ الػي ط وا ا تاط آػتا تاط اؿثاع داسد. مؾ طشاح ا تخاب V M تا ػایض ت ذی اػة تشا ضیؼت س ا اػت.

35 V out (V) هثال هحاسث حاشی یش تا استفاد اس گیي دا ا ص ؼتی ا يشوثيش um, (W/L) p /(W/L) n = 3.4 (W/L) n = 1.5 (min size) V DD = 2.5V V M 1.25V, g = V in (V) V IL = 1.2V, V IH = 1.3V NM L = NM H = 1.2 (actual values are V IL = 1.03V, V IH = 1.45V NM L = 1.03V & NM H = 1.05V)

36 V out (V) Impact of Process Variation on VTC Curve دا ا ص ؼتی ا يشوثيش Good PMOS Bad NMOS Bad PMOS Good NMOS Nominal V in (V) Process variations (mostly) cause a shift in the switching threshold

37 V out (V) V out (V) دا ا ص ؼتی ا يشوثيش Scaling the Supply Voltage V in (V) Device threshold voltages are kept (virtually) constant Gain= V in (V) Device threshold voltages are kept (virtually) constant

38 ار گز ایستا مذ خص ا تما ی سفتاس ایؼتا سفتاس پ یا تح ي ت ا ا شطی طشاحی تشای صشف و

39 تحلیل رفتار س ییچی گ دا ا ص ؼتی ا يشوثيش V DD V DD R p V out V out C L R n C L V in = 0 V in = V DD Gate response time is determined by the time to charge C L through R p (discharge C L through R n )

40 تحلیل تاخیز ار گز دا ا ص ؼتی ا يشوثيش Propagation delay is proportional to the time-constant of the network formed by the pull-down resistor and the load capacitance V DD t phl = f(r n, C L ) R n C L V out = 0 t phl = ln(2) R eqn C L = 0.69 R eqn C L t plh = ln(2) R eqp C L = 0.69 R eqp C L V in = V DD t p = (t phl + t plh )/2 = 0.69 C L (R eqn + R eqp )/2 To equalize rise and fall times make the on-resistance of the NMOS and PMOS approximately equal.

41 مولفه های خازن دا ا ص ؼتی ا يشوثيش

42 خازن گیت درین دا ا ص ؼتی ا يشوثيش چ تشا ضیؼت س M1 دس تاط ای س دی VDD/2 > 0 فمط دس احي لطغ یا اؿثاع اػت فمط خاص Overlap داسی و آ تا اػتفاد اص اثش ي ش ی ت ا تي دسی ص ي لشاس داد.

43 خازن درین بدنه دا ا ص ؼتی ا يشوثيش 2 -تشای د تشا ضیؼت س M2 M1 خاص تي دسی تا ص ي ج د داسد و غيش خطی اػت ی ت ا یه خاص ؼاد تا خطی ػاصی تمشیة دس ظش شفت. مذاس ای خاص تؼت ی ت ػطح حيط جا ثی پي ذ دسی تذ داسد. 3 -خاص س دی طثم تؼذ و تاس Fanout ای طثم حؼ ب ی ؿ د. 4- خاص اتصاالت يا ی CW

44 دا ا ص ؼتی ا يشوثيش هثال هحاسث خاسى اي د ار گز cascade تى طی 0.25 µm =0.125 µm تشای تشا ضیؼت س NMOS Ad=4x4 2 +3x1 2 Pd=( ) تشای تشا ضیؼت س PMOS Ad=9x4 2 +9x1 2 Pd=(5+9+5)

45 ادامه مثال دا ا ص ؼتی ا يشوثيش

46 هقذار هقا هت گام پزشذى )خالي شذى( خاسى دا ا ص ؼتی ا يشوثيش تا توجه ته اینکه تاخیز انتشار تا رسیدن ته %50 مقدار نهایی تعزیف می شود. 7 x S V GS V T R o n D اس مدل تزانشستور ته عنوان یک سوییچ تا تقزیة معادله سیز استفاده می کنیم (for V GS = V DD, V DS = V DD V DD /2) V DD (V) R eqn = 3/4 V DD /I DSATn

47 هحاسث تاخیز ا تشار تزاي ار گز د طثق قثلي دا ا ص ؼتی ا يشوثيش تا دس ظش شفت ما ت ای on تشا ضیؼت س ای pmosتاا nmos حاذال اتؼااد ؼاد ( 31 KΩ 13 KΩ تاا ت جا تا ای ىا ػاشض تشا ضیؼا ت س اای nmos pmos ف ق تتشتية تشاتش حذال اتؼاد ؼت ذ. ماذاس ما ات اای آ اا تاا تمؼي ما ت تشا ضیؼت س شجغ ت ضشایة ف ق تذػت ی آیذ زا داسی.

48 دا ا ص ؼتی ا يشوثيش Inverter Transient Response V in V DD =2.5V 0.25m W/L n = 1.5 W/L p = 4.5 R eqn = 13 k ( 1.5) R eqp = 31 k ( 4.5) f t r t phl t plh t t (sec) From simulation: t phl = 39.9 psec and x t phl = 36 psec t plh = 29 psec so t p = 32.5 psec t plh = 31.7 psec

49 پاراهتز اي ه ثز ر ي تاخیز ا تشار ار گز دا ا ص ؼتی ا يشوثيش t phl = 0.69 R eqn C L = 0.69 (3/4 (C L V DD )/I DSATn ) 0.52 C L / (W/L n k n V DSATn ) تا جای ضاسی ما ت ؼاد تمشیثی V DD (V)

50 پاراهتز اي ه ثز در سزعت دا ا ص ؼتی ا يشوثيش Reduce C L internal diffusion capacitance of the gate itself - keep the drain diffusion as small as possible interconnect capacitance Fanout (Cg Next Level)

51 پاراهتز اي ه ثز در سزعت دا ا ص ؼتی ا يشوثيش Increase W/L ratio of the transistor the most powerful and effective performance optimization tool in the hands of the designer watch out for self-loading! when the intrinsic capacitance dominates the extrinsic load Increase V DD can trade-off energy for performance increasing V DD above a certain level yields only very minimal improvements reliability concerns enforce a firm upper bound on V DD

52 دا ا ص ؼتی ا يشوثيش سثت NMOS/PMOS So far have sized the PMOS and NMOS so that the R eq s match (ratio of 3 to 3.5) symmetrical VTC equal high-to-low and low-to-high propagation delays If speed is the only concern, reduce the width of the PMOS device! widening the PMOS degrades the t phl due to larger parasitic capacitance b = (W/L p )/(W/L n ) r = R eqp /R eqn (resistance ratio of identically-sized PMOS and NMOS) b opt = r when wiring capacitance is negligible

53 دا ا ص ؼتی ا يشوثيش PMOS/NMOS Ratio Effects 5 x t plh t phl t p b of 2.4 (= 31 k/13 k) gives symmetrical response 3.5 b of 1.6 to 1.9 gives optimal performance b = (W/L p )/(W/L n )

54 دا ا ص ؼتی ا يشوثيش Device Sizing for Performance Divide capacitive load, C L, into C int : intrinsic - diffusion and Miller effect C ext : extrinsic - wiring and fanout t p = 0.69 R eq C int (1 + C ext /C int ) = t p0 (1 + C ext /C int ) where t p0 = 0.69 R eq C int is the intrinsic (unloaded) delay of the gate Widening both PMOS and NMOS by a factor S reduces R eq by an identical factor (R eq = R ref /S), but raises the intrinsic capacitance by the same factor (C int = SC iref ) t p = 0.69 R ref C iref (1 + C ext /(SC iref )) = t p0 (1 + C ext /(SC iref )) t p0 is independent of the sizing of the gate; with no load the drive of the gate is totally offset by the increased capacitance any S sufficiently larger than (C ext /C int ) yields the best performance gains with least area impact

55 دا ا ص ؼتی ا يشوثيش Sizing Impacts on Delay x for a fixed load S The majority of the improvement is already obtained for S = 5. Sizing factors larger than 10 barely yield any extra gain (and cost significantly more area). self-loading effect (intrinsic capacitance dominates)

56 دا ا ص ؼتی ا يشوثيش Impact of Fanout on Delay Extrinsic capacitance, C ext, is a function of the fanout of the gate - the larger the fanout, the larger the external load. First determine the input loading effect of the inverter. Both C g and C int are proportional to the gate sizing, so C int = C g is independent of gate sizing and t p = t p0 (1 + C ext / C g ) = t p0 (1 + f/) i.e., the delay of an inverter is a function of the ratio between its external load capacitance and its input gate capacitance: the effective fan-out f f = C ext /C g

57 س جیز ار گز ا دا ا ص ؼتی ا يشوثيش حذال وشد تاخيش تا ا تخاب اػة تؼذاد ت ي اتؼاد ت ي اس ش ا In C g,1 1 2 N C L Out the delay of the j-th inverter stage is t p,j = t p0 (1 + C g,j+1 /(C g,j )) = t p0 (1 + f j / ) and t p = t p1 + t p t pn t p = t p,j = t p0 (1 + C g,j+1 /(C g,j ))

58 دا ا ص ؼتی ا يشوثيش Sizing the Inverters in the Chain ی ت ا ا داد حذال يضا تاخيش لتی اتفاق ی افتذ و ت ػثاست دی ش افضایؾ اتؼاد طثمات ؼثت ت یىذی ش تا ؼثت ثاتتی اتفاق تيافتذ و دس آ ضشیة ت اػة ا f اػت اص ساتط صیش تذػت ی آیذ. و دس آ F ؼثت خاص تاس خش جی ت خاص س دی طثم ا اػت. (F = C L /C g,1 ) ت اتشای حذال تاخيش اص ساتط صیش تذػت ی آیذ. تؼذاد طثمات اػت ت اتشای ی ت ا N اػة سا ا تخاب د تا تاخيش ت ي ؿ د. N

59 دا ا ص ؼتی ا يشوثيش Example of Inverter Chain Sizing In Out C g,1 1 f = 2 f 2 = 4 C L = 8 C g,1 C L /C g,1 has to be evenly distributed over N = 3 inverters C L /C g,1 = 8/1 f = 3 8 = 2

60 ا تخاب تعذاد طثقات ت ی N دا ا ص ؼتی ا يشوثيش ا ش تؼذاد طثمات سا صیاد و ي تذ ي تاخيش راتی و دس N ضشب ی ؿ د تاخيش صیاد ی ؿ د ا ش تؼذاد طثمات سا و ت يشی تاخيش اؿی اص Fanout غا ة ی ؿ د. مذاس ت ي اص ح ؼاد صیش تذػت ی آیذ. + F - ( F lnf)/n = 0 For = 0 N = ln (F) and the effective-fan out becomes f = e = For = 1 (the typical case) the optimum effective fan-out (tapering factor) turns out to be close to 3.6

61 دا ا ص ؼتی ا يشوثيش Optimum Effective Fan-Out Choosing f larger than optimum has little effect on delay and reduces the number of stages (and area). Common practice to use f = 4 (for = 1) But too many stages has a substantial negative impact on delay f

62 دا ا ص ؼتی ا يشوثيش Example of Inverter (Buffer) Staging 1 C g,1 = 1 C L = 64 C g,1 N f t p C g,1 = 1 C L = 64 C g, C g,1 = 1 C L = 64 C g, C g,1 = 1 C L = 64 C g,1

63 Impact of Buffer Staging for Large C L F ( = 1) Unbuffered Two Stage Chain Opt. Inverter Chain , ,000 10, Impressive speed-ups with optimized cascaded inverter chain for very large capacitive loads.

64 مثال : تاخير بهينه

65 دا ا ص ؼتی ا يشوثيش Input Signal Rise/Fall Time In reality, the input signal changes gradually (and both PMOS and NMOS conduct for a brief time). This affects the current available for charging/discharging C L and impacts propagation delay. x t p increases linearly with increasing input slope, t s, once t s > t p t s is due to the limited driving capability of the preceding gate t s (sec) for a minimum-size inverter with a fan-out of a single gate x 10-11

66 ار گز ایستا مذ خص ا تما ی سفتاس ایؼتا سفتاس پ یا تح ي ت ا ا شطی طشاحی تشای صشف و

67 ه لف اي تلفات تلفات دینامیکی : در اثز سوییچینگ و مصزف انزصی تزای شارص و دشارص خاسن تار V out NMOS off PMOS res NMOS sat PMOS res NMOS sat PMOS sat NMOS res PMOS sat NMOS res PMOS off تلفات ناشی اس مسیز جزیان مستقیم تلفات استاتیک )جزیان نشتی و سیز آستانه( V in

68 تلفات دی اهیکي ػاختاس اس ش CMOS اػتاتيه ت ای اػت و ت فات ت ا اػتاتيه دس آ اچيض اػت ػ ذ ت فات دس حا ت تغييش ضؼيت اص 0 ت 1 یا تش ػىغ اتفاق ی افتذ. ش تاس و خاص تاس اص ؼيش pmos ؿاسط ی ؿ د تاط آ اص 0 ت VDD ی سػذ. ا شطی صشف ؿذ ت ػط ثغ VDD ا شطی رخيش ؿذ دس خاص سا ی ت ا تا س اتط صیش تتشتية ا داد. فمط ي ی اص ا شطی شفت ؿذ اص ثغ دس خاص تاس رخيش ی ؿ د ي دی ش آ دس تشا ضیؼت س pmos ت ف ی ؿ د. يضا ت فات تؼتىی ت اتؼاد ) ما ت( تشا ضیؼت س pmos ذاسد. دس ػيى دؿاسط ا شطی رخيش ؿذ دس C L ی ؿ د. خاص دس تشا ضیؼت س nmos ت ف ی ؿ د. ت اتش ای ا شطی ت ف ؿذ دس ش ػيى تشاتش VDD 2

69 دا ا ص ؼتی ا يشوثيش Dynamic Power Consumption Vdd Vin Vout C L Energy/transition = C L * V DD 2 * P 01 f 01 P dyn = Energy/transition * f = C L * V DD 2 * P 01 * f P dyn = C EFF * V DD 2 * f where C EFF = P 01 C L Not a function of transistor sizes! Data dependent - a function of switching activity!

70 طزاحي تزاي هصزف کن تا ت ج ت ؼاد ت ا دی ا يىی 3 ػا دس وا ؾ ت ا ثش ؼت ذ وا ؾ تاظ تغزی : چ ت ا صشفی تا ت ا د تاط ت اػة اػت ای ػا ی اػت تا واا ؾ تااظ تاخيش يت صیاد ی ؿ د. ت اتشای یه trade off تي ت ا تاخيش ج د داسد وا ؾ خاص تاس: چ وا ؾ خاص ثش ت فات تاخيش سا وا ؾ ی د ذ وا ؾ آ ط ب اػت. ا ا دس ػ چ تخؾ ػ ذ ای اص خاص تاس خاص ای داخ ی تشا ضیؼت س ث خاص يت ف ر ؼات ذ واا ؾ خاص ا ت ؼ ی و چه ػاصی تشا ضیؼت س اػت و ت ت خ د چ ما ت ؼاد آ ا سا افضایؾ ی د ذ جش ت افضایؾ تاخيش ی ؿ د. وا ؾ احت ا ػ یيچي آتی ت آ اؿاس ی ؿ د ای ض ع سا تا ؼ اسی اػة ذاس تا حذی ی ت ا ا جا داد دس فص اای وا ؾ فشوا غ: ؼ ال تش خالف ي طشاح اػت. ) يت وشد والن ػي ا ای غيش فؼا ( دس ػ تشويثی اص وا ؾ تا ظ ت غزی ا تخااب اػاة ات ؼااد يات ج ات ت ي ا ػااصی تا ا ض اا ج يشی اص افضایؾ تاخيش تيؾ اص حذ ط ب سد اػتفاد لشاس ی يشد. دس ؿثى ای تضسي ت ج ت اتؼاد ثش وا ؾ تاط تغزی ی ت ا ذ صشف ت ا سا تا 10 تشاتش وا ؾ د ذ.

71 دا ا ص ؼتی ا يشوثيش Lowering Dynamic Power Capacitance: Function of fan-out, wire length, transistor sizes Supply Voltage: Has been dropping with successive generations P dyn = C L V DD 2 P 01 f Activity factor: How often, on average, do wires switch? Clock frequency: Increasing

72 تلفات اشي اس هسیز جزیاى هستقین دس حا ت زسا چ ؿية ػي ا س دی حذ د اػت تشای ذت و ی یه ؼيش جشیا ؼتمي تي VDD ص ي ایجاد ی ؿ د. E sc = t sc V DD I peak P 01 P sc = t sc V DD I peak f 01

73 جزیاى پیک اتصال ک تا I peak determined by the saturation current of the P and N transistors which depend on their sizes, process technology, temperature, etc. strong function of the ratio between input and output slopes a function of C L

74 اثز خاسى تار ر ي تلفات هسیز جزیاى هستقین دس حا تيى تاخيش يت صیاد تاؿذ لتی ػي ا س دی تغييش ی و ذ تاط خش جی ص تاالػت زا اختالف پتا ؼي ػ سع دسی pmos اچيض اػت جشیا اتصا و تا اچيض خ ا ذ ت د. دس ػ ض ا ش خاص تاس و چه تاؿذ تاخيش يت و تاؿذ. تاط دسی ػ سع ػشیغ تغييش ی و ذ زا جشیا اتصا و تا صیاد خ ا ذ ت د Large capacitive load Output fall time significantly larger than input rise time. Small capacitive load Output fall time substantially smaller than the input rise time.

75 جزیاى اتصال ک تا تز حسة خاسى تار When load capacitance is small, I peak is large. Short circuit dissipation is minimized by matching the rise/fall times of the input and output signals - slope engineering.

76 دا ا ص ؼتی ا يشوثيش P sc as a Function of Rise/Fall Times V DD = 3.3 V V DD = 2.5 V V DD = 1.5V t sin /t sou When load capacitance is small (t sin /t sout > 2 for V DD > 2V) the power is dominated by P sc If V DD < V Tn + V Tp then P sc is eliminated since both devices are never on at the same time. W/L p = m/0.25 m W/L n = m/0.25 m C L = 30 ff

77 تلفات استاتیک دس حا ت اػتاتيه ت د ي ج د جشیا تی پي ذ ای تایاع ؼى ع دسی ػ سع تا تذ ت فات ایؼتایی داسی. دس ػ ای ت فات اچيض اػت دس حذ pa/m 2 اػت. ا ا ای جشیا تی تا افضایؾ د ا تص ست ایی صیاد ی ؿ د ت ػ ا دس د ای 85 C حذ د 60 تشاتش د ای اطاق ی ؿ د. ي ط س ت فات اؿی اص جشیا صیش آػتا تشای تشا ضیؼت س ا دس حا ت خا ؽ ج د داسد.

78 Standby Power Why worry about power? -- Standby Power Drain leakage will increase as V T decreases to maintain noise margins and meet frequency demands, leading to excessive battery draining standby power consumption. 50% Year Power supply V dd (V) Threshold V T (V) KW and phones leaky! 40% 1.7KW 30% 400W 20% 10% 12W 88W 0% Source: Borkar, De Intel

79 دا ا ص ؼتی ا يشوثيش Leakage as a Function of V T Continued scaling of supply voltage and the subsequent scaling of threshold voltage will make subthreshold conduction a dominate component of power dissipation ID (A) 10-7 VT=0.4V VT=0.1V An 90mV/decade V T roll-off - so each 255mV increase in V T gives 3 orders of magnitude reduction in leakage (but adversely affects performance) VGS (V)

80 TSMC Processes Leakage and V T CL018 G CL018 LP CL018 ULP CL018 HS CL015 HS CL013 HS V dd 1.8 V 1.8 V 1.8 V 2 V 1.5 V 1.2 V T ox (effective) 42 Å 42 Å 42 Å 42 Å 29 Å 24 Å L gate 0.16 m 0.16 m 0.18 m 0.13 m 0.11 m 0.08 m I DSat (n/p) (A/m) 600/ / / / / /400 I off (leakage) (A/m) ,800 13,000 V Tn 0.42 V 0.63 V 0.73 V 0.40 V 0.29 V 0.25 V FET Perf. (GHz)

81 I leakage (na/m) Exponential Increase in Leakage Currents دا ا ص ؼتی ا يشوثيش Temp(C) From De,1999

82 دا ا ص ؼتی ا يشوثيش Energy & Power Equations E = C L V DD 2 P 01 + t sc V DD I peak P 01 + V DD I leakage f 01 = P 01 * f clock P = C L V DD 2 f 01 + t sc V DD I peak f 01 + V DD I leakage Dynamic power (~90% today and decreasing relatively) Short-circuit power (~8% today and decreasing absolutely) Leakage power (~2% today and increasing)

83 کل تلفات حاصلضزب توان در تاخیز و انزصی درتاخیز پاسا تش PDP و حاص ضشب ت ا دس تاخيش اػت. ای پاسا تش ؼياسی اص يضا ا شطی صشفی ی تاؿذ. ا ش اص ت فات اػتاتيه ت فات ؼيش جشیا ؼتمي صشف ظش و ي ی ت ا دیذ PDP ؼاد ا شطی صشفی يت تاصای یه ػ یيچي ی تاؿذ. پاسا تش لات ت ج دی ش حاص ضشب ا شظی دس تاخيش ی تاؿذ و ؼياسی اص ػشػت ا شطی يت اػت.

84 هثال: لتاص تغذی ت ی حاػث تاط ت ي تشای حذال EDP وشد EDP is the average energy consumed multiplied by the computation time required takes into account that one can trade increased delay for lower energy/operation (e.g., via supply voltage scaling that increases delay, but decreases energy consumption) Energy-Delay (normalized) energy-delay 5 energy 0 delay Vdd (V)

85 دا ا ص ؼتی ا يشوثيش Understanding Tradeoffs Which design is the best (fastest, coolest, both)? b Lower EDP c a d 1/Delay better

86 دا ا ص ؼتی ا يشوثيش Power and Energy Design Space Constant Throughput/Latency Variable Throughput/Latency Energy Design Time Non-active Modules Run Time Logic Design DFS, DVS Active Reduced V dd Sizing Multi-V dd Clock Gating Leakage + Multi-V T Multi-V dd Sleep Transistors (Dynamic Freq, Voltage Scaling) + Variable V T Variable V T

87 دا ا ص ؼتی ا يشوثيش Sizing In Out C g1 1 f C ext Goal: Minimize Energy of whole circuit Design parameters: f and V DD tp tpref of circuit with f=1 and V DD =V ref t t p p0 f t p0 1 1 VDD V V DD TE F f

88 دا ا ص ؼتی ا يشوثيش Transistor Sizing Performance Constraint (=1) t t p pref t t p0 p0ref 2 f F f V DD V V 2 3 F V V V 3 F ref ref DD TE TE f F f 1 Energy for single Transition E V E E ref 2 DD C V V g1 DD ref 1 1 f f F 4 F F

89 دا ا ص ؼتی ا يشوثيش Transistor Sizing V DD =f(f) E/E ref =f(f) F=1 vdd (V) F= normalized energy f f

90 normalized energy دا ا ص ؼتی ا يشوثيش Dynamic Power as a Function of Device Size Device sizing affects dynamic energy consumption gain is largest for networks with large overall effective fanouts (F = C L /C g,1 ) The optimal gate sizing factor (f) for dynamic energy is smaller than the one for performance, especially for large F s e.g., for F=20, f opt (energy) = 3.53 while f opt (performance) = 4.47 If energy is a concern avoid oversizing beyond the 0 optimal F=1 F=2 f F=5 F=10 F=20

91 Multi VDD دا ا ص ؼتی ا يشوثيش Prime choice: Reduce voltage! Recent years have seen an acceleration in supply voltage reduction (USE Multi VDD) Reduce switching activity (How?) Reduce physical capacitance Device Sizing: for F=20 - f opt (energy)=3.53, f opt (performance)=4.47

92 دا ا ص ؼتی ا يشوثيش Dynamic Power as a Function of V DD Decreasing the V DD decreases dynamic energy consumption (quadratically) But, increases gate delay (decreases performance) V DD (V) Determine the critical path(s) at design time and use high V DD for the transistors on those paths for speed. Use a lower V DD on the other gates, especially those that drive large capacitances (as this yields the largest energy benefits). 1

93 Multi V T Reducing the V T increases the subthreshold leakage current (exponentially) 90mV reduction in V T increases leakage by an order of magnitude ID (A) But, reducing V T decreases gate delay (increases performance) VGS (V) VT=0.4V VT=0.1V Determine the critical path(s) at design time and use low V T devices on the transistors on those paths for speed. Use a high V T on the other logic for leakage control. A careful assignment of V T s can reduce the leakage by as much as 80%

94 دا ا ص ؼتی ا يشوثيش Dual-Thresholds Inside a Logic Block Minimum energy consumption is achieved if all logic paths are critical (have the same delay) Use lower threshold on timing-critical paths Assignment can be done on a per gate or transistor basis;

95 Variable V T (ABB) V T = V T0 + ( -2 F + V SB - -2 F ) For an n-channel device, the substrate is normally tied to ground (V SB = 0) A negative bias on V SB causes V T to increase Adjusting the substrate bias at run time is called adaptive body-biasing (ABB) Requires a dual well fab process V SB (V)

96 دا ا ص ؼتی ا يشوثيش Logic Design Optimization Switching activity, P 01, has two components A static component function of the logic topology A dynamic component function of the timing behavior (glitching) 2-input NOR Gate A B Out Static transition probability P 01 = P out=0 x P out=1 = P 0 x (1-P 0 ) With input signal probabilities P A=1 = 1/2 P B=1 = 1/2 NOR static transition probability = 3/4 x 1/4 = 3/16

97 دا ا ص ؼتی ا يشوثيش NOR Gate Transition Probabilities Switching activity is a strong function of the input signal statistics P A and P B are the probabilities that inputs A and B are one A B With input signal probabilities P A=1 = 1/2 P B=1 = 1/2 A B Out A B C L P 01 = P 0 x P 1 = (1-(1-P A )(1-P B )) (1-P A )(1-P B )

98 Transition Probabilities for Some Basic Gates P 01 = P out=0 x P out=1 NOR (1 - (1 - P A )(1 - P B )) x (1 - P A )(1 - P B ) OR (1 - P A )(1 - P B ) x (1 - (1 - P A )(1 - P B )) NAND P A P B x (1 - P A P B ) AND (1 - P A P B ) x P A P B XOR (1 - (P A + P B - 2P A P B )) x (P A + P B - 2P A P B ) For X: P 01 = P 0 x P 1 = (1-P A ) P A A B X Z = 0.5 x 0.5 = 0.25 For Z: P 01 = P 0 x P 1 = (1-P X P B ) P X P B = (1 (0.5 x 0.5)) x (0.5 x 0.5) = 3/16

99 دا ا ص ؼتی ا يشوثيش Inter-signal Correlations Determining switching activity is complicated by the fact that signals exhibit correlation in space and time reconvergent fan-out A B (1-0.5)(1-0.5)x(1-(1-0.5)(1-0.5)) = 3/16 P(X=1)=3/4, P(X=0)=1/4 X Z غلط Reconvergent (1-3/4 x 0.5) x (3/4 x 0.5) = 15/64 P(Z=1) = P(B=1) & P(A=1 OR B=1) Z=(A+B)B=AB+B=B(1+A)=B P(Z=1)=1/2 P(0>1)=1/4 Have to use conditional probabilities

100 دا ا ص ؼتی ا يشوثيش Logic Restructuring Logic restructuring: changing the topology of a logic network to reduce transitions 0.5 A B 0.5 AND: P 01 = P 0 x P 1 = (1 - P A P B ) x P A P B (1-0.25)*0.25 = 3/16, P(W=1) = 1/4 W 7/64, P(X=1)=1/8 X 15/256 C 0.5 D F A 0.5 B 0.5 C 0.5 D =0.355 = /16, Y Z 3/16, 15/256 F Chain implementation has a lower overall switching activity than the tree implementation for random inputs

101 دا ا ص ؼتی ا يشوثيش Input Ordering 0.5 A B 0.2 (1-0.5x0.2)x(0.5x0.2)=0.09 X C F 0.1 (1-0.1x0.1)x(0.1x0.1)= B C 0.1 (1-0.2x0.1)x(0.2x0.1)= X A F 0.5 (1-0.02x0.5)x(0.02x0.5)=0.01 =0.1 = Beneficial to postpone the introduction of signals with a high transition rate (signals with signal probability close to 0.5)

102 جلس آی ذ دا ا ص ؼتی ا يشوثيش دسع تؼذی يت ای تشويثی