Low Noise Amplifiers. Prepared by: Heng Zhang. ECEN 665 (ESS) : RF Communication Circuits and Systems

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1 ECEN 665 (ESS) : RF Communication Circuits and Systems Low Noise Amplifiers Prepared by: Heng Zhang Part of the material here provided is based on Dr. Chunyu Xin s and Dr. Xiaohua Fan s dissertation 1

2 What is an LNA? Amplifier S matrix: [ S] s Source reflection coefficient: Load reflection coefficient: Input reflection coefficient: 11 1 = s1 s Output reflection coefficient: s Γ L Γ S s s Γ Γ = 1 1 L in s s Γ L s s s Γ Γ = S out 1 s Γ 11 S

3 LNA Requirements Gain(10-0dB) to amplify the received signal; to reduce the input referred noise of the subsequent stages Good linearity Handling large undesired signals without much distortion Low noise for high sensitivity Input matching Max power gain Preceding filters require 50Ω termination for proper operation Can route the LNA to the antenna which is located an unknown distance away without worrying about the length of the transmission line 3

4 LNA Metrics: Gain Defines small signal amplification capability of LNA For IC implementation, LNA input is interfaced off-chip and usually matched to specific impedance (50Ω or 75Ω). Its output is not necessary matched if directly drive the on-chip block such as mixer. This is characterized by voltage gain or transducer power gain by knowing the load impedance level. Transducer power gain: Power delivered to the load divided by power available from source. 1 ΓS 1 ΓL GT = s 1 1 s Γ 1 s Γ For unilateral device: (i.e. s1 = 0) 11 S L 4

5 LNA Metrics: Nonlinearity Model f 1 f off-band signal f 1 - f f 1 - f f - f 1 f 1 + f f f 1 f f 1 in-band signal Output signal spectrum with f1 and f f f 1 f f Nonlinear System (up to 3 rd order): Two tone input signal: Y = a + a X + a X + a X 3 t 0 1 t t 3 t X = Acos( wt) + Acos( w t) t 1 Usually distortion term: f1-f, f-f1 fall in band. This is characterized by 3 rd order non-linearity. Large in-band blocker can desensitize the circuit. It is measured by 1-dB compression point. 5

6 LNA Metrics: Linearity measurement 1dB compression: Measure gain compression for large input signal IIP3/IIP: Measure inter-modulation behavior Relationship between IIP3 and P1dB: For one tone test: IIP3-P1dB=10dB For two tone test: IIP3-P1dB=15dB 6

7 LNA Metrics: Noise Figure Noise factor is defined by the ratio of output SNR and input SNR. Noise figure is the db form of noise factor. Noise figure shows the degradation of signal s SNR due to the circuits that the signal passes. Sensitivity = Noisefloor( dbm) + SNR + NF tot 174dBm+ 10log BW Noise factor of cascaded system: LNA s noise factor directly appears in the total noise factor of the system. LNA s gain suppress the noise coming from following stages 7

8 MOS Amp Noise Figure Calculation the current gain of the MOS amp is given by: v s 1 io = gmvgs = gm 1 R j Cgs s R ω + g + jωc g g g = vs vs ; ωt = 1+ jωc R + R j C R + R C ( ) ω ( ) gs m m m gs s g gs s g gs 8

9 Noise Figure by Current Gain ω io = Gm( ω) v T 1 s Gm ( ω) = j ω Rs + R the total output noise current is given by: ( ) i = G v + v + i ot, m g s d the noise figure can be easily computed: F iot, iot, vg id = = = 1 + +, i G v v G v o m s s m s γ v = 4 ktr, v = 4 ktr, i = 4kT g α g g s s d m g 9

10 Noise Figure Calculation(cont.) Substitution of the the various noise sources leads to : γ g m R g α ω F = 1+ + Rs + R Rs Rs ωt Rg γ ω 1+ + Rs α ωt g R m s ( ) This expression contains both the channel noise and the gate induced noise 1 Rg = Rpoly + is a good approximation 5g m g 10

11 Minimum Noise for MOS Amp the optimal value of Rs : F R γ ω g R g = + 0 m = s Rs α ωt R s, opt = R = s ωt ω R g γ g α m Thus the minimum Noise Figure is: ω γ Fmin = 1+ gmrg ωt α 11

12 F vs. Rs For an LNA operating at 5.GHz in 0.18 μm CMOS process, according to experience and published literatures, we can choose R g = Ω, γ = 3, α = 0.75, ω T = π*56ghz, g m = 50mA/V and plot F vs. Rs: Rg γ ω F = 1+ + Rs α ωt g R m s 1

13 MOS Amp Example Find Rs, opt for a typical amplifier. Assume ft = 75GHz f = 5 GHz, ( γ α) =, Rpoly is minimized by proper layout, thus intrinsic gate resistance is given by: 1 1 Rg = Rpoly + 5g 5g To make the noise contribution from this term 0.1: R R g s m 10 = 0.1 gm = = 40mS Rs, opt 119 Ω, Fmin = R s In practice, it ll be difficult to get such a low Noise figure and get useful gain with the simple common source due to the bad power match Conflict of minimum noise vs. optimum matching That s why we need input matching schemes for LNA! m 13

14 LNA Metrics: Input Matching Why do we need it? We have learned how to choose optimum source impedance for minimum noise figure One important requirement for LNA is 50 ohm matching The input of a common source amplifier is primarily capacitive and provides very poor power match! Maximum power transfer: P * in Z s Z = V Z V P V1 s in s in in _ LNA _max = = = = Zin Re( Zs ) ( Zin + Zs ) What should we do to have both good NF and good power match? 14

15 LNA Input Matching Topologies Wideband LNA: Resistive termination Common Gate Resistive shunt-feedback Narrowband LNA: Inductive degenerated Resistive terminated 15

16 Resistive Termination LNA VDD Since the input of a CS MOS devices is primarily capacitive then we can R D terminate the input with a resistor Rm=Rs to match the input (at low frequencies) M Z out V out It can be used in both narrowband and the wideband application. But its high NF(usually NF>6dB) characteristic limits its application. V in R s V b Z in R m M 1 I dc 16

17 Noise Analysis Output noise due to source resistor Rs: where V = KTR A = KTR ( g R ) ns, s v s m1 D A g R v and R m1 D D << Zout Output noise due to matching resistor Rm(=Rs): V = KTR ( g R ) nm, s m1 D Output noise due to thermal noise of M1: γ inm, 1= 4KT gm 1 α Output noise due to the load resistor, RD: V = KTR ns, D V in R s V out V n,s * Z in Z out * V n,m R m * n,d i g1 V R D Cgs1 r o i - + n,m V1 g - m1v1 + V gs gm V x - r o1 C gs i n,m1 Output noise due to thermal noise of M: γ sc gs g sc m gs inm, = 4KT gm = inm, 1 α gm sc gs g m1 gm sc + + gs 17

18 Noise Analysis The noise factor of the LNA is: F total output noise = noise due to the source resistor V + V + V + V + V ns, nm, nm, 1 nd, nm, Vns, Noise from RD is attenuated by LNA gain. The noise transfer function of M is smaller due to source degeneration. Both are ignored for simplicity: Rm 4γ 4γ F = 1+ + = + R αg R αg R s m1 s m1 s Therefore, even when gmrs>>4γ, Fmin> (NF>3dB) Resistor termination provides a good power match but greatly degrades the NF The terminating resistor adds its own noise It also drops the gain by 6dB (compared to CS with no termination). As a result the input referred noise of the device and those of the following stages increase by the same factor 18

19 Common Gate(CG) LNA Input impedance: 1 Zin = gm + jωcgs gm if ωcgs << gm ω << ω << ωt Zin Cgs Noise Figure: ignoring poly gate resistance, gate noise, and ro, the output current noise is: i no ind : i = i + i no no, ind no, Rs, drain current noise i no Rs : e ns g m no, R = s = ens ( R ) 1 g s + Rin + mrs i, output noise current due to source resistance 1 g m 19

20 Noise Analysis io = ind + gmvgs ind Rs vgs = ( ind + gmvgs + jωcgsvgs ) Rs vgs = 1+ gv m gs+ jωcv gs gs 1+ jωcgsrs 1 io = ind ind, assume CgsRs << 1 1+ g v + jωc R 1+ g R m gs gs s m s ( ω ) Notice that if gm=1/rs (power match) then only half of drain current noise goes to the output 0

21 Noise Analysis Noise Factor: F 1 ind 1+ g R γ g = 1+ = 1+ g ens 1+ gmrs m s d 0 g m mrs Under the input matching condition: Rs=1/gm we have: F 5 γ g. Long channel d 0 γ = db = 1+ = 1+ = 3 gm α 3 = 4.8 db Short channel 1

22 Resistive Shunt-feedback LNA The negative feedback network is used to implement the input matching The input impedance is determined by open loop gain and the resistor values (R f, R L ), which are easily controlled. The resistor is a noise component and the LNA has moderate noise performance. Voltage gain: A Input impedance: Z v = Output impedance: in ( 1 1 ) R g R L m f R f Rf = 1 + Z out + R L + RL 1 // g R sc = m1 L gs1 R L Rs + Rf // 1 + g R m1 s V in R S Z in R f C f C gs1 R L M 1 Z out V out

23 Noise Analysis Noise Factor: F R f Zout R s RL out id1 Zout 4 i 4 i Z 4 = V A V A V A nr, v nr, v nr, v s s s R f 1+ gm 1R 1 Rf + R s s γ g R m1 f + R s = R s 1 gm 1R f RsR L 1 gm 1R f α R s 1 gm 1R f 3

24 Inductive degenerated LNA Input impedance behaves like a series RLC circuit, gate inductor Lg is added to tune the resonant frequency to align with the operating frequency: ( ) 1 m s Zin = s Lg + Ls + + sc gs g L C Matching occurs when: ( ) ω ( + ) in gs Z jω = R g L 1 m s o =, and Rs = = ωtls L C g Ls Cgs gs L Rs = ω Ls can be selected by: s T if this value is too small to be practical, a capacitor can be inserted in shunt with Cgs to artificially reduce ωt 0 s 4

25 Input impedance-non-idealities 1 1 Z = s L + L + + L + + R + R + R + R sc 1 gs s ωtrls 1 ωo = Rpoly, shw 1 1 Rg = R gnqs, = ( Lg + Ls) Cgs // 1nL 5gm ωtrls ( ) ω, in g s T s Lg g Ls g NQS ( ω ) Z j = ω L + R + R + R + R in 0 T s Lg g Ls g, NQS Inductance loss R Lg : offset Z in R Ls : offset Z in and w 0 Gate resistance R g : offset Z in NQS gate resistance R g,nqs : offset Z in 5

26 Q Boosting At resonance we get Q boosting effect: 1 1 Q = ω ω = ω ( Rs + Ls T) Cgs 0 RC s gs 0 vgs = Q vs 1 ω T i = g v = Qg v = v { R G s ω0 m 1443 d m gs m s s G m Need to watch out for linearity as vgs is Q times larger than the input signal Short channel devices operating in velocity saturation regime (i.e., large overdrive voltage) are more forgiving as their gm is relatively constant. 6

27 Equivalent input network From the source, the amplifier input(ignoring Cgd) is equivalent to: At resonance, the complete circuit is as follows: 7

28 Noise Analysis The output noise current due to Rs and Rg is simply calculated by multiplying the voltage noise sources by Gm The calculation of output noise current due to drain noise is more involved: i d flows partly into the source of the device, it activates the gm of the transistor which produces a correlated noise in shunt with Output noise current: ( ) 1 ω T ino = Gm vr + v,, s R + i g d out Gm = Rs ωo i d 8

29 Noise Analysis: Drain Noise The noise component flowing into the source is given by the current divider: jωls vgs = ( gmvgs + id ) 1 jωls + + jωlg + Rs jωc gs 1 jωc jωls 1 id = ( gmvgs + id) (at resonance) gmvgs = R jωc s gs gs Note that we are not including R g in the small signal model 9

30 Total Output Noise Let s first ignore the correlation of the gate noise and drain current noise. Notice only ¼ of the drain noise flows to output ( ) 1 1 ω T ino = Gm vr + v s R + i g d Gm = 4 Rs ωo F i Rg γ ω o = = 1+ + gmrs G v Rs α ωt no m R s Note that the Noise figure at resonance is the same as CS amplifier w/o inductive degeneration. Inductive degeneration did not raise F min but matched the input! 30

31 Total Output Noise(cont.) If we consider the correlation of the gate noise and drain current noise then one can show (*) Rg γ ω o F = 1+ + χ gmrs Rs α ωt δα δα χ = 1 + cql 1 5γ + 5γ + Q L 1 ω = QC = = gs ω RC ( QL) ( L + L ) o g s R o s gs s Optimal Noise figure happens for a particular Q L. Possible to obtain a noise and power match * D.K. Shaeffer, T.H. Lee, A 1.5V 1.5GHz CMOS Low Noise Amplifier, JSSC, Vol. 3, No. 5. May

32 Optimal Q L If we try to optimize the noise figure while power dissipation is kept constant then: Q L,opt will be independent from the frequency and around 4.5 Fmin is not too sensitive to Q L and only changes by less than 0.1dB for Q L between 3.5 and 5.5 Smaller Q L results in larger bandwidth and smaller inductors, while a larger Q L results in narrower bandwidth and larger inductors 3

33 Linearity Linearity of a MOS transistor in saturation region: 4Veff 8Veff VIIP3, strong MOS = ( + θveff )( 1+ θveff ) > 3 θ 3 θ 1 Veff = Vgs Vth θ = E L E sat ~ 1V/μm for L~0.35 μm-0.18 μm IIP3 is independent of W sat V 16 D 1 IIP3, LNA ( V ) = ( + ρ ) 1+ 3 Po θ P 3 vsatesat ρ = θv P = V ω R eff o DD o s ρ 3 MOS transistor s IIP3 v.s. gate drive voltage 33

34 Design Recipe for Inductive degenerated LNA Step 1: Choose Q L for optimal NF C gs Width(W) ( Q = 1 ω RC ) L o s gs Step : Determine the current(i d ) from power budget Step 3: From W & I d g m and V eff Step 4: From g m and V eff ω T and F min Step 5: Select L s and L g for the input network L = R ω ( L = 1/ ω C ) L s s T g o gs s 34

35 Design Recipe: Iterations NF is not low enough? Increase ω T by increasing I d (with fixed device size) For fixed current density, increasing Q will reduce device size thus reduce total power - NF will increase Linearity doesn t meet spec? Reduce Q (in short channel devices the improvement is limited) Burn more current (not gaining much due to velocity saturation) Apply proper linearization techniques Need to increase gain? Larger Q L Larger g m Larger Load(Z L ) 35

36 Design Example: Specs: Frequency S11 S1 NF IIP3 Current.4GHz <-10dB >15dB <db >-10dBm <10mA Supply 1.8V Process 0.18μm CMOS Step 1: Choose Q L = 4.5. then C = 1Q ω R = 147fF gs L o s Choose minimum length L = 0.18μm W = 110μm Step : Choose the current I d = 9mA Step 3: From W & I d g m = 5mA/V Step 4: From g m and C gs f T = 56GHz Step 5: Select L s and L g for the input network: L = R ω = 0.14nH s s T L C L nh g = 1 ωo gs s = 31 Step 6: S1 requirement Z L = 4Ω 36

37 Simulation Results: S1, S11, NF 37

38 Simulation Results: IIP3 38

39 Summary: Parameters: Calculated Simulated M1 110μm/ μm/0.18 M μm 110μm/0.18 μm 110μm/0.18 L g μm 31nH μm 0nH L s 0.14nH 0.8nH I d 9mA 8.6mA Z L 4Ω 6Ω Performance: Specs Simulation Frequency.4GHz.4GHz S11 <-10dB -3dB S1 >15dB 15.7dB NF <db ~0.6dB IIP3 >-10dBm -6.85dBm Current <10mA 8.6mA Supply 1.8V 1.8V 39

40 Effect of R L on input match We ignored the effect of load impedance on input impedance in previous derivations. Let s revisit it: It can be shown that: ( L ω) 1 r o s Zin = + jlsω+ LsωT + jcgsω ro + RL + jlsω ro 1 ro + jlsω+ [ LsωT] jc ω r + R gs o L R L can be large and it can drop the real part of the input impedance when we use resonators at output Notice that the output impedance influenced the input impedance even in the absence of C gd! 40

41 Differential v.s. Single-ended LNA Differential reject common mode noise and interferer shield the bond wire x double area and current x need balun at input x common-mode stability x linearity limited by bias current Single-ended compact layout size less power for same NF and linearity x susceptive to bond wire and PCB trace x drive single-balance mixer; or use output balun to drive doublebalance mixer 41

42 Differential LNA Common-mode Stability Issue in, com g s m s m 1 ω CC 1 ( ) 1 Z = jω L + L + g L + C g C + C jωcc 1 Real part: R g = L 1 m in, com s C1 ω C Typical differential LNA Common-mode half circuit For passive termination, the real part of the source impedance will always be positive. IF R in,com happens to be negative and cancel the real part of source impedance, oscillation MAY occur. 4

43 Variant of Inductive Degenerated LNA nmos-pmos shunt input Current reuse to save power Larger area due to two degeneration on chip inductor Single-ended version of current reuse LNA (bias not shown) NF: db, Power gain: 17.5dB, IIP3: -6dBm, Id: 8mA from.7v power supply F. Gatta, E. Sacchi, et al, A -db Noise Figure 900MHz Differential CMOS LNA, IJSSC, Vol. 36, No. 10, Oct. 001 pp

44 Variant of Inductive Degenerated LNA Inter-stage inductor with parasitic capacitance form impedance match network between input stage and cascoded stage boost gain lower noise figure. Input match condition will be affected Single-ended version of current reuse LNA (bias not shown) Chunyu Xin, and Edgar Sánchez-Sinencio, A GSM LNA Using Mutual-Coupled Degeneration, IEEE Microwave and Wireless Components Letters, VOL. 15, NO., Feb

45 Comparison of LNA Architectures Resistive Termination Common Gate Shunt Feedback Noise Figure >6dB 3~5dB.8~5dB ~db Inductive Degeneration Gain 10~0dB 10~0dB 10~0dB 15~5dB Sensitivity to Parasitic Less Less Less Large Input Matching Easy Easy Easy Complex Linearity -10~10dBm -5~5dBm -5~5dBm -10~0dBm Power 1~50mW ~5mW >15mW >10mW Highlight Effortless input matching Easy input matching Broadband input/out matching Good narrowband Matching, small NF Drawback Large NF Large NF Stability Large area 45

46 Substrate Noise A MOS device is in fact a 4 terminal device. The 4 th terminal is the substrate. The bulk-source potential modulates the drain current with a transconductance of g mb which has the same polarity as g m (i.e., increasing the bulk potential increases the drain current) The substrate has a finite (nonzero) resistance and therefore has thermal noise To reduce R sub we should put many substrate contacts close to the device 4kTR i = Δf g sub no, sub mb 1+ ( ωrsubcb ) Substrate noise characterization: John T. Colvin et.al: Effects of Substrate Resistances on LNA Performance and a Bondpad, JSSC Sep

47 Substrate Noise(cont.) Solution: Place as many substrate contact as possible! Pros: Reduces possibility of latch up issues Lowers R sub and its associated noise(impacts LNA through backgate effect (g mb ) Absorbs stray electrons from other circuits that will otherwise inject noise into the LNA Cons: takes up a bit extra area 47

48 Package Parasitics As interface to the external world, the LNA must transit from the silicon chip to the package and board environment, which involves bondwires, package leads, and PCB trace. 48

49 Package Parasitics(cont.) Two effects from bondwire and package inductance: Value of degeneration inductor is altered Noise from other circuits couples into LNA 49

50 Package Parasitics(cont.) Some or all of the degeneration inductor L s can be absorbed into the bondwire inductance These parasitics must be absorbed into the LNA design. This requires a good model for the package and bondwires. It should be noted that the inductance of the input loop depends on the arrangement of the bondwires, and hence die size and pad locations. Many designs also require ESD protection, which manifests as increased capacitance on the pads. For more details, please read: 1. B. Razavi, Design of Analog CMOS Integrated Circuits (chapter 18) McGraw-Hill, New York Andrzej Szymañski et.al: Effects of package and process variation on.4 GHz analog integrated circuits, Microelectronics and Reliability, Jan

51 Cadence Simulation for LNA Characterization of the major Figure of merit of an LNA in Cadence S-parameter simulation input and output match noise figure gain Periodic steady state (pss) simulation/spss IIP/IIP3, 1dB point Please refer to Lab 3 manual 51

52 LNA Testing: S parameter Before doing the measurement: Calibrate two lines. Adjust the power level 5

53 LNA Testing: Linearity(IIP3/IIP) RF IN Output Signal 53

54 LNA Testing: Noise Figure Spectrum Analyzer Noise Source 54