Lecture 24 Multistage Amplifiers (I) MULTISTAGE AMPLIFIER

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1 Lecture 24 Multistage Amplifiers (I) MULTISTAGE AMPLIFIER Outline. Introduction 2. CMOS multi-stage voltage amplifier 3. BiCMOS multistage voltage amplifier 4. BiCMOS current buffer 5. Coupling amplifier stages Reading Assignment: Howe and Sodini, Chapter 9, Sections Spring 2009 Lecture 24

2 . Introduction Most often, single stage amplifier does not accomplish design goals: Need more gain than could be provided by a single stage Need to adapt to specified R S and R L to maximize efficiency Multistage amplifier V BIAS Issues: What amplifying stages should be used and in what order? What devices should be used, BJT or MOSFET? How is biasing to be done? 6.02 Spring 2009 Lecture 24 2

3 Summary of single stage amplifier characteristics Stage A vo, A io R in R out Key Function Source Drain Gate Emitter Collector Base A = g r // r ) r o // r oc vo m( o oc g m A vo g m g mb A io A vo =g m (r o //r oc ) A vo A io g m g mb r oc //[r o ( g m R S )] g m g mb rπ r o // r oc π βo ( ro // roc RL ) R S g m r // g m β o r oc //[r o ( g m ( r π // R S ))] Differences between BJT s and MOSFETs BJT MOSFET Transconductance amplifier Voltage Buffer Current buffer Transconductance amplifier Voltage buffer Current buffer r π = β o g m g mb g m g m = I C V th > g m = 2 W L μc ox I D r o = V A I C > r o = λi D 6.02 Spring 2009 Lecture 24 3

4 2. CMOS Multistage Voltage Amplifier Goals: High voltage gain, A vo High input resistance, R in Low output resistance, R out Good starting point: -Source stage: R in = A vo =-g m (r o //r oc ), probably insufficient R out = (r o //r oc ), too high 6.02 Spring 2009 Lecture 24 4

5 CMOS Multistage Voltage Amplifier (contd.) Add second CS stage to get more gain: R in = A vo =g m (r o //r oc ) g m2 (r o2 //r oc2 ) R out = (r o2 //r oc2 ), still too high Add CD stage at output (to reduce R out ): R in = A vo = g m r o r oc R out = g m3 g mb3 ( )g m2 r o2 r oc2 ( ) g m3 g m3 g mb Spring 2009 Lecture 24 5

6 3. BiCMOS multistage voltage amplifier A vo (CE) > A vo (CS) because g m (BJT) > g m (MOSFET), but.. CS stage is best first stage, since R in =. How about adding a CE stage following the CS stage? R S (r o r oc ) (r o2 r oc2 ) v s v A r in v v in v in2 2 A v2 v in2 v out R L CS CE However, inter-stage loading degrades gain: R out = r o r oc >> R in2 = r π2 There is a voltage divider between stages R in2 R out R in2 R in2 R out r π2 r o r oc << Additional gain provided by the CE stage is mostly lost to inter-stage loading Spring 2009 Lecture 24 6

7 BiCMOS multistage voltage amplifier (contd.) Use two CS stages, but add CC stage at output: R S (r o2 r oc2 ) g m3 r o2 r oc2 βo3 v s v in A v A v2 v v in in3 r 3 β o3 (r o3 r oc3 R L ) v in3 v out R L CS CS CC Inter-stage loading: R out2 = r o2 r oc2, R in3 = r π3 β o 3( r o3 r oc3 R L ) Then, inter-stage loss: R in3 R out 2 R in3 = ( ) ( ) r π3 β o3 r o3 r oc3 R L r o2 r oc2 r π3 β o3 r o3 r oc3 R L Better than trying to use a CE stage, but still pretty bad. The good thing is that R out has improved: R out = R out3 = g m3 R out2 β o3 = g m3 r o2 r oc2 β o3 Since, in general g m (BJT) > g m (MOSFET), R out could be better than CD output stage if r o2 r oc2 is not too large. Otherwise, CD output stage is better Spring 2009 Lecture 24 7

8 BiCMOS multistage voltage amplifier (contd.) Better voltage buffer: cascade CC and CD output stages What is the best order? Since R in (CD)=, best to place CD first: R (r o2 r oc2 ) (g m3 g mb3 ) g S m4 β o4 (g m3 g mb3 ) v s v in A v A v2 v in v in3 v in3 v in4 r 4 β o4 (R L r o r oc ) v in4 v out CS CS CD CC R L Inter-stage loading: R in3 R in3 R out2 = R in4 R in4 R out3 = ( ) ( ) r π4 β o4 r o4 r oc4 R L r π4 β o4 r o4 r oc4 R L g m3 g mb3 The output resistance is excellent: R out = R out4 = g m4 R out3 β o4 = g m4 ( ) β o4 g m3 g mb Spring 2009 Lecture 24 8

9 4. BiCMOS current buffer Goals: Unity current gain, A i = Very low input resistance, R in Very high output resistance, R out Start with a common-base stage: A io = R in = g m [ ( )] { } R out = r oc r o g m r π R S Note that if R S is high enough, R out r oc (β o r o ). Can we increase R out further by adding a second CB stage? 6.02 Spring 2009 Lecture 24 9

10 BiCMOS current buffer (contd). CB-CB Current Buffer i in i in2 i out i s R S g m i in β o r o r oc g m2 i in2 R L CB CB Now ( ) { [ ]} R out = R out2 = r oc2 r o2 g m2 r π2 R out Plugging in R out r oc (β o r oc ). { [ ( )]} R out = r oc2 r o2 g m2 r π2 r oc β o r o But, since r π2 << r oc (β r oc ), then [ g m2 r o2 (r 2 β o r o r oc )] r oc2 R out = r oc2 [ r o2 ( g m2 r π2 )] r oc2 ( β o2 r o2 ) Did not improve anything! The base current limits the number of CB stages that can improve the output resistance to just one. Since the CG stage has no gate current, cascade it with the CB stage 6.02 Spring 2009 Lecture 24 0

11 BiCMOS current buffer (contd). CB-CG Current Buffer i in i in2 i out i s R S g m i in β o r o r oc g m2 i in2 R L CB CG [g m2 r o2 (β o r o r oc )] r oc2 R out = R out2 = r oc2 [ r o2 ( g m2 R out )] Plugging in R out r oc (β o r oc ). R out = r oc2 [ r o2 g m2 ( r oc β o r o )] Now R out has improved by about g m2 r o2, but only to the extent that r oc2 is high enough 6.02 Spring 2009 Lecture 24

12 5. Coupling Amplifier Stages CAPACITIVE COUPLG Capacitors that have large enough value behave as AC short, so the signal goes through but bias is independent for each stage. Example, CD-CC voltage buffer: 5.0 V 5.0 V 4.0 V 2.5 V 3.2 V 2.5 V I SUP I SUP2 Assumes V BE = 0.7 V V GS =.5 V Advantages Can select bias point for optimum operation Can select bias point close to the mid-point of the power rails for maximum voltage swing Disadvantages To approximate AC short, large capacitors are needed and they consume large area Spring 2009 Lecture 24 2

13 Coupling Amplifier Stages (contd.) DIRECT COUPLG: share bias points across stages. Example, CD-CC voltage buffer: 5.0 V 5.0 V 4.7 V 3.2 V 2.5 V I SUP I SUP2 Assumes V BE = 0.7 V V GS =.5 V Advantages No capacitors needed compact Disadvantages Bias point shared:constrains designs. Bias shifts from stage to stage and can stray too far from center of range Generally requires level shifting to bring signal back to center of range Spring 2009 Lecture 24 3

14 Coupling Amplifier Stages (contd.) SOLUTION: use PMOS CD stage for level shifting. 5.0 V 5.0 V I SUP 3.2 V.7 V 2.5 V I SUP2 Assumes V BE = 0.7 V V GS =.5 V 6.02 Spring 2009 Lecture 24 4

15 Coupling Amplifier Stages (contd.) Summary of DC shifts through amplifier stages: Amplifier Type Source/ Emitter (CS/CE ) Gate/ Base (CG/CB) Drain/ Collector (CD/CC ) Transistor Type NMOS PMOS npn pnp V V V V i SUP i SUP i SUP i SUP V V V V V V V V i SUP i SUP i i SUP SUP V V i SUP V V V i SUP i SUP V V V V V i SUP V V 6.02 Spring 2009 Lecture 24 5

16 What did we learn today? Summary of Key Concepts To achieve design goals, multistage amplifiers are often needed In multistage amplifiers, different stages are used to accomplish different goals Voltage gain: common-source, common emitter Voltage buffer: common drain, common collector Current buffer: common gate, common base In multistage amplifiers, attention must be paid to inter-stage loading to avoid unnecessary losses Must select compromise bias, Must pay attention to bias shift from stage to stage 6.02 Spring 2009 Lecture 24 6

17 MIT OpenCourseWare Microelectronic Devices and Circuits Spring 2009 For information about citing these materials or our Terms of Use, visit:

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