Lecture 13 MOSFET as an amplifier with an introduction to MOSFET smallsignal model and smallsignal schematics. Lena Peterson


 Cordelia Holt
 2 years ago
 Views:
Transcription
1 Lecture 13 MOSFET as an amplifier with an introduction to MOSFET smallsignal model and smallsignal schematics Lena Peterson
2 Outline (1) Why is the CMOS inverter gain not infinite? Largesignal and smallsignal models Derive two smallsignal parameters: Transconductance: gm Output conductance: 2
3 Outline (2) How derive smallsignal schematic How to bias the transistor: Commonsource amplifier Smallsignal schematic Gain CSamplifier w. active load vs inverter Current mirror (for completeness) 3
4 From lecture 3 & lab 1: noise margin 4
5 CMOS inverter voltage transfer curve (VTC) Spectre simulation 65 nm process L = 1 µm, Wn= 1 µm & Wp = 2 µm 5
6 CMOS inverter VTC closeup gain = ΔVOUT/ΔVIN 140 mv/2 mv = 70 L = 1 µm, Wn= 1 µm & Wp = 2 µm What is the gain? It is NOT infinite! 6
7 The gain curve remember from lab 1 L = 1 µm, Wn= 1 µm & Wp = 2 µm 7
8 How can we calculate the inverter transfer curve? And why is the gain not infinite when both transistors are in saturation? 8
9 Transistor operation: digital and analog Digital: switch V DD Analog: amplifier V DD v IN v OUT v OUT v IN v IN v IN vin = VIN + vin t t v OUT v OUT vout = VOUT + vout t t Large swings i D t 1 t 2 t 3 t 4 t 1 t 2 t 1 i D Small variations around operating (bias) point t 3 t 4 v DS v DS 9
10 Smallsignal models Capture only the deviation part around the bias point Operating point can also be called bias point or quiescent point 10
11 Smallsignal model (1) Drain current is a function of terminal voltages (here three terminals, source terminal is reference) i D = i D (v GS,v DS ) Taylor expansion around operating (bias) point: i D I D + v GS + v DS 11
12 Smallsignal model (2) Divide all currents and voltages into bias point and smallsignal variations around it: i D = I D + i d, v GS = V GS + v gs, v DS = V DS + v ds Draincurrent variation may be expressed as: i d = g m v gs + g d v ds where g m = i D v GS vgs =V GS g ds = i D v DS vds =V DS 12
13 Smallsignal model Our task today: find expressions for the two smallsignal parameters: transconductance: g m output conductance: g d 1 r o Question to ponder: when is a set of smallsignal parameters valid? 13
14 Corresponding smallsignal schematic G D + + vgs gmvgs gd vds S 14
15 Simplest current equations Saturation region: I D = µc ox 2 W L (V GS V T ) 2 Linear region: I D = µc ox W L ((V GS V T )V DS V 2 DS 2 ) MOSFETS in amplifiers are usually biased in saturation 15
16 Transconductance (in saturation) I D = µc ox 2 W L (V GS V T ) 2 g m = I D V GS Find an expression for gm! Also, express gm as a function of ID and either VGS or W/L. 16
17 Transconductance (in saturation) I D = µc ox 2 W L (V GS V T ) 2 g m = I D V GS Effective gate voltage and drain current determine gm! g m = W g m = µc ox L (V GS V T ) 2I D W g m = 2µC ox V GS V T L I D 17
18 MOSFET output diagram w. secondorder effects Figure from Weste and Harris
19 Extended current model Shockley s model in saturation: I D = µc ox 2 W L (V GS V T ) 2 With secondorder effects: I D = µc ox 2 I D = µc ox 2 in saturation W L (V GS 19 V DS V GS V T V T ) 2 (1 + V DS V A ) or often written like this W L (V GS V T ) 2 (1 + V DS ) Weste & Harris section 2.4.2
20 Output conductance With secondorder effects: I D = µc ox 2 W L (V GS V T ) 2 (1 + V DS V A ) Derive expression for output conductance If Early voltage can be written as rds L (where L is the transistor length) what expression do we get? 20 Weste & Harris section 2.4.2
21 Output conductance g d = I D = λ µc ox V DS 2 Lambda is inverse of Early voltage: g d = λi D = λ I D L Some books use r o W L (V GS V T ) 2 λi D = λ = I D V A = Early voltage I D r ds L for transistor output resistance Both are drawn as resistors in model! Note: Longer transistors are more like current generators (lower output conductance) L I D 21
22 Complete smallsignal schematic at low frequencies G D + + S vgs gmvgs gd vds S _ B v bs + _
23 Early Voltage VA (example from bipolar transistor) Large VA is good! More like current source 23
24 DIBL and channellength modulation (in 65nm process) 24
25 Smallsignal parameters important in analog design (derivatives of drain current w r t voltages). Transconductance, gm, is the desired one! Is determined by ratio of drain current (should be large) and effective gate voltage (should be small) Output conductance, gd, undesired (should be as small/large as possible) => make transistors long(er) for analog! pmos and nmos transistors have the same smallsignal model Conclusion ss transistor models
26 How to bias and find the gain for entire circuits 26
27 Commonsource amplifier 5 x Id Vds Vgs=0.5 Vgs=0.6 Vgs=0.7 Vgs=0.8 Vgs=0.9 Vgs= 1 Note the load line 3 Id [A] Common Source stage Vds [V] 3V W L = 10µm 3µm R D =100kΩ v OUT V OUT [V] v IN V [V] IN
28 Operating (or bias or quiescent) point 3 3 Common Source stage v OUT [V] V time v IN [V] W L = 10µm 3µm v IN R D = 100kΩ v OUT time
29 Large signal  small signal 3 3 Common Source stage v OUT [V] V time v [V] IN W L = 10µm 3µm v IN R D = 100kΩ v OUT time
30 Commonsource stage voltage gain V IN V OUT V OUT V IN 30
31 Deriving a smallsignal schematic All constant voltage sources are shorts (because there is 0 change in the voltage = no smallsignal voltage ) thus both VDD and VSS are smallsignal ground All constant current sources are cuts (because there is 0 change in the current = no smallsignal current) Smallsignal schematics for NMOS and PMOS transistors are identical 31
32 CS stage example 3V W L = 10µm 3µm v IN R D = 100kΩ v OUT Parameters for 0.35 μm process: VT = 0.5 V k n= 110 μa/v 2 VA =55 V/μm What VIN gives VOUT = 1.5 V? Draw the smallsignal diagram What is the gain AV then? 32
33 CS stage solution (1) What VIN (=VGS) gives VOUT= VDD/2 = 1.5 V? ID is known from resistor loadline: ID = VDD/(2*RD) = 1.5V/100 kω =15 µa To find VIN (=VGT+VT) solve this equation for VGT: ID =k /2*W/L VGT 2 (1+VOUT/VA) 1.5 =110*10/(2*3)VGT 2 (1+1.5/165) VGT 2 =1.5/(183.3*1.009)=0.09 => VGT = 0.3 V => VIN = 0.8 V 33
34 Smallsignal schematic for CS stage G D v in v gs g m v gs R D Gain for CS stage: r o v out 3V W L = 10µm 3µm v IN R D = 100kΩ v OUT A v = v out R D r o = g m (R D r o )= g m v in R D + r o I D = V R D = 1.5V if VOUT is VDD/2 R L 100k = 15µA r o = V A I D = Lr0 ds I D = 3µm 55V/µm 15µA = 11M 34
35 Transconductance for CS stage g m = I D V GS = I D V G = I OUT V IN Turns input voltage change into output current change 35
36 CS stage intrinsic gain If load resistance RD is large (as for an ideal current source) G D v in v gs g m v gs R D r o v out Find an expression for the smallsignal gain: Av = vout/vin Use expressions for the smallsignal parameters to find an expression for the gain where ID is eliminated 36
37 CS stage intrinsic gain If load resistance RD is large (as for an ideal current source) G D v in v gs g m v gs R D A v = g m r o = g m g m A v 2I D V GS V T g d g d = I D V A = v out For high gain choose low overdrive voltage and long transistor! r o I D LV 0 A 2V A = 2LV A 0 V GS V T V GS V T Early voltage, VA, traditionally scales linearly with length L but not in 65 nm process. We must use VA given for each L 37
38 MOStransistor output resistance r o = V DS I D = 1 I D V DS 0.35um process 38
39 Useful circuit analysis tools Sources can be transformed using Norton/ Thevenin transformations For linear circuits (also smallsignal schematics!) superposition holds: Effects of several independent sources can be calculated separately and added together Sometimes one source can be split into several to take advantage of superposition 39
40 What is bad with biasing with a resistor? Talk to your neighbor! 40
41 Commonsource amplifier Id [A] x 10 5 Id Vds Vgs=0.5 Vgs=0.6 Vgs=0.7 Vgs=0.8 Vgs=0.9 Vgs= Vds [V] 3V 3 Common Source stage With RD the load line is straight: R = V*I With some other current source Ohm s law does not hold: draw the line for an ideal current source! W L = 10µm 3µm v IN R D =100kΩ v OUT V OUT [V] V IN [V] 41
42 CS stage with active load Biasing gain transistor with current source 42
43 CS amplifier with active V DD V DD v in v gs g mn v gs r on v out V B load r op v OUT A v = g mn (r on r op ) I B v IN r out = r on r op Main purpose of active load: decouple biasing of transistor and load output impedance 43
44 Current mirror Use: to copy and scale currents Design principle: i IN R L Design ONE very accurate reference current source Copy (and scale) this current over entire chip for biasing M 1 M 2 i OUT 44
45 Currentmirror operation 1. M1 diodeconnected (drain connected to gate): When on, v GS1 >V T, always in saturation because: v DS1 = v GS1 =>v DS1 v GS1 V T 2. M2 same v GS as M1: v GS1 = v GS2 = v GS 3. When M2 in saturation, v DS2 v GS V T we have: i OUT i IN µc W 2 ox (V L = 2 GS V T ) 2 µc W 1 ox (V L 1 GS V T ) 2 = W 2 L 2 W 1 L 1 Note! this is not a smallsignal gain 45
46 Conclusions commonsource amplifier A v = v out v in = g m (R D r o )= g m R D r o R D + r o r in = r out = R D r o Intrinsic gain: A v = 2V A V GS V T = 2Lr ds V GS V T Active load decouples biasing of transistor and load output impedance 46
47 Summary Smallsignal gain is derivative of VOUT vs VIN curve Transistor smallsignal parameters are derivatives: transconductance: gm (want it high!) drain conductance: gd (want it low!) Longer transistor are more like current sources Intrinsic transistor gain does not depend on current: 2VA/VGT 47
48 Biasing the amplifying transistor without decreasing the gain is tricky: Biasing resistor limits gain of CS stage RD CMOS inverter has high(er) smallsignal gain but is biased by VIN (very sensitive!) Commonsource amplifier with active load: Load transistor acts as current source = sets the bias current for gain transistor Result: Bias (current IB) and output resistance of CS amplifier are decoupled Summary 48
ECE 523/421  Analog Electronics University of New Mexico Solutions Homework 3
ECE 523/42  Analog Electronics University of New Mexico Solutions Homework 3 Problem 7.90 Show that when ro is taken into account, the voltage gain of the source follower becomes G v v o v sig R L r o
More information1/13/12 V DS. I d V GS. C ox ( = f (V GS ,V DS ,V SB = I D. + i d + I ΔV + I ΔV BS V BS. 19 January 2012
/3/ 9 January 0 Study the linear model of MOS transistor around an operating point." MOS in saturation: V GS >V th and V S >V GS V th " VGS vi  I d = I i d VS I d = µ n ( L V V γ Φ V Φ GS th0 F SB F
More informationECE315 / ECE515 Lecture 11 Date:
ecture 11 Date: 15.09.016 MOS Differential Pair Quantitative Analysis differential input Small Signal Analysis MOS Differential Pair ECE315 / ECE515 M 1 and M are perfectly matched (at least in theory!)
More informationDigital Integrated Circuits
Chapter 6 The CMOS Inverter 1 Contents Introduction (MOST models) 0, 1 st, 2 nd order The CMOS inverter : The static behavior: o DC transfer characteristics, o Shortcircuit current The CMOS inverter :
More informationMOS Transistor IV Characteristics and Parasitics
ECEN454 Digital Integrated Circuit Design MOS Transistor IV Characteristics and Parasitics ECEN 454 Facts about Transistors So far, we have treated transistors as ideal switches An ON transistor passes
More informationECE 342 Electronic Circuits. 3. MOS Transistors
ECE 342 Electronic Circuits 3. MOS Transistors Jose E. SchuttAine Electrical & Computer Engineering University of Illinois jschutt@emlab.uiuc.edu 1 NMOS Transistor Typically L = 0.1 to 3 m, W = 0.2 to
More informationBiasing the CE Amplifier
Biasing the CE Amplifier Graphical approach: plot I C as a function of the DC baseemitter voltage (note: normally plot vs. base current, so we must return to EbersMoll): I C I S e V BE V th I S e V th
More informationECE343 Test 2: Mar 21, :008:00, Closed Book. Name : SOLUTION
ECE343 Test 2: Mar 21, 2012 6:008:00, Closed Book Name : SOLUTION 1. (25 pts) (a) Draw a circuit diagram for a differential amplifier designed under the following constraints: Use only BJTs. (You may
More informationLecture 28 FieldEffect Transistors
Lecture 8 FieldEffect Transistors FieldEffect Transistors 1. Understand MOSFET operation.. Analyze basic FET amplifiers using the loadline technique. 3. Analyze bias circuits. 4. Use smallsignal equialent
More informationChapter 13 SmallSignal Modeling and Linear Amplification
Chapter 13 SmallSignal Modeling and Linear Amplification Microelectronic Circuit Design Richard C. Jaeger Travis N. Blalock 1/4/12 Chap 131 Chapter Goals Understanding of concepts related to: Transistors
More informationMOS Transistor Theory
MOS Transistor Theory So far, we have viewed a MOS transistor as an ideal switch (digital operation) Reality: less than ideal EE 261 Krish Chakrabarty 1 Introduction So far, we have treated transistors
More informationLecture 37: Frequency response. Context
EECS 05 Spring 004, Lecture 37 Lecture 37: Frequency response Prof J. S. Smith EECS 05 Spring 004, Lecture 37 Context We will figure out more of the design parameters for the amplifier we looked at in
More informationEE40 Lec 20. MOS Circuits
EE40 Lec 20 MOS Circuits eading: Chap. 12 of Hambley Supplement reading on MOS Circuits http://www.inst.eecs.berkeley.edu/~ee40/fa09/handouts/ee40_mos_circuit.pdf Slide 1 Bias circuits OUTLINE Smallsignal
More informationEECS 105: FALL 06 FINAL
University of California College of Engineering Department of Electrical Engineering and Computer Sciences Jan M. Rabaey TuTh 23:30 Wednesday December 13, 12:303:30pm EECS 105: FALL 06 FINAL NAME Last
More informationCMOS Inverter (static view)
Review: Design Abstraction Levels SYSTEM CMOS Inverter (static view) + MODULE GATE [Adapted from Chapter 5. 5.3 CIRCUIT of G DEVICE Rabaey s Digital Integrated Circuits,, J. Rabaey et al.] S D Review:
More informationToday s lecture. EE141 Spring 2003 Lecture 4. Design Rules CMOS Inverter MOS Transistor Model
 Spring 003 Lecture 4 Design Rules CMOS Inverter MOS Transistor Model Today s lecture Design Rules The CMOS inverter at a glance An MOS transistor model for manual analysis Important! Labs start next
More informationLecture 3: CMOS Transistor Theory
Lecture 3: CMOS Transistor Theory Outline Introduction MOS Capacitor nmos IV Characteristics pmos IV Characteristics Gate and Diffusion Capacitance 2 Introduction So far, we have treated transistors
More informationLecture 15: MOS Transistor models: Body effects, SPICE models. Context. In the last lecture, we discussed the modes of operation of a MOS FET:
Lecture 15: MOS Transistor models: Body effects, SPICE models Context In the last lecture, we discussed the modes of operation of a MOS FET: oltage controlled resistor model I curve (SquareLaw Model)
More informationECE 438: Digital Integrated Circuits Assignment #4 Solution The Inverter
ECE 438: Digital Integrated Circuits Assignment #4 The Inverter Text: Chapter 5, Digital Integrated Circuits 2 nd Ed, Rabaey 1) Consider the CMOS inverter circuit in Figure P1 with the following parameters.
More informationPractice 3: Semiconductors
Practice 3: Semiconductors Digital Electronic Circuits Semester A 2012 VLSI Fabrication Process VLSI Very Large Scale Integration The ability to fabricate many devices on a single substrate within a given
More informationLecture 12: MOSFET Devices
Lecture 12: MOSFET Devices GuYeon Wei Division of Engineering and Applied Sciences Harvard University guyeon@eecs.harvard.edu Wei 1 Overview Reading S&S: Chapter 5.1~5.4 Supplemental Reading Background
More information6.012 Electronic Devices and Circuits Spring 2005
6.012 Electronic Devices and Circuits Spring 2005 May 16, 2005 Final Exam (200 points) OPEN BOOK Problem NAME RECITATION TIME 1 2 3 4 5 Total General guidelines (please read carefully before starting):
More informationECE343 Test 1: Feb 10, :008:00pm, Closed Book. Name : SOLUTION
ECE343 Test : Feb 0, 00 6:008:00pm, Closed Book Name : SOLUTION C Depl = C J0 + V R /V o ) m C Diff = τ F g m ω T = g m C µ + C π ω T = g m I / D C GD + C or V OV GS b = τ i τ i = R i C i ω H b Z = Z
More informationECE 415/515 ANALOG INTEGRATED CIRCUIT DESIGN
ECE 415/515 ANALOG INTEGRATED CIRCUIT DESIGN CMOS PROCESS CHARACTERIZATION VISHAL SAXENA VSAXENA@UIDAHO.EDU Vishal Saxena DESIGN PARAMETERS Analog circuit designers care about: Openloop Gain: g m r o
More informationLecture 12 Digital Circuits (II) MOS INVERTER CIRCUITS
Lecture 12 Digital Circuits (II) MOS INVERTER CIRCUITS Outline NMOS inverter with resistor pullup The inverter NMOS inverter with currentsource pullup Complementary MOS (CMOS) inverter Static analysis
More informationMOS Transistor Properties Review
MOS Transistor Properties Review 1 VLSI Chip Manufacturing Process Photolithography: transfer of mask patterns to the chip Diffusion or ion implantation: selective doping of Si substrate Oxidation: SiO
More information2007 Fall: Electronic Circuits 2 CHAPTER 10. DeogKyoon Jeong School of Electrical Engineering
007 Fall: Electronic Circuits CHAPTER 10 Digital CMOS Logic Circuits DeogKyoon Jeong dkjeong@snu.ac.kr k School of Electrical Engineering Seoul lnational luniversity it Introduction In this chapter, we
More informationTHE INVERTER. Inverter
THE INVERTER DIGITAL GATES Fundamental Parameters Functionality Reliability, Robustness Area Performance» Speed (delay)» Power Consumption» Energy Noise in Digital Integrated Circuits v(t) V DD i(t) (a)
More informationCircle the one best answer for each question. Five points per question.
ID # NAME EE255 EXAM 3 November 8, 2001 Instructor (circle one) Talavage Gray This exam consists of 16 multiple choice questions and one workout problem. Record all answers to the multiple choice questions
More informationEE 330 Lecture 16. Devices in Semiconductor Processes. MOS Transistors
EE 330 Lecture 16 Devices in Semiconductor Processes MOS Transistors Review from Last Time Model Summary I D I V DS V S I B V BS = 0 0 VS VT W VDS ID = μcox VS VT VDS VS V VDS VS VT L T < W μc ( V V )
More information3. Basic building blocks. Analog Design for CMOS VLSI Systems Franco Maloberti
Inverter with active load It is the simplest gain stage. The dc gain is given by the slope of the transfer characteristics. Small signal analysis C = C gs + C gs,ov C 2 = C gd + C gd,ov + C 3 = C db +
More informationCHAPTER 3: TRANSISTOR MOSFET DR. PHAM NGUYEN THANH LOAN. Hà Nội, 9/24/2012
1 CHAPTER 3: TRANSISTOR MOSFET DR. PHAM NGUYEN THANH LOAN Hà Nội, 9/24/2012 Chapter 3: MOSFET 2 Introduction Classifications JFET DFET (Depletion MOS) MOSFET (Enhancement EFET) DC biasing Small signal
More information1. (50 points, BJT curves & equivalent) For the 2N3904 =(npn) and the 2N3906 =(pnp)
HW 3 1. (50 points, BJT curves & equivalent) For the 2N3904 =(npn) and the 2N3906 =(pnp) a) Obtain in Spice the transistor curves given on the course web page except do in separate plots, one for the npn
More informationENGR890 Digital VLSI Design Fall Lecture 4: CMOS Inverter (static view)
ENGR89 Digital VLSI Design Fall 5 Lecture 4: CMOS Inverter (static view) [Adapted from Chapter 5 of Digital Integrated Circuits, 3, J. Rabaey et al.] [Also borrowed from Vijay Narayanan and Mary Jane Irwin]
More informationEE 330 Lecture 16. MOS Device Modeling pchannel nchannel comparisons Model consistency and relationships CMOS Process Flow
EE 330 Lecture 16 MOS Device Modeling pchannel nchannel comparisons Model consistency and relationships CMOS Process Flow Review from Last Time Operation Regions by Applications Id I D 300 250 200 150
More informationECE342 Test 3: Nov 30, :008:00, Closed Book. Name : Solution
ECE342 Test 3: Nov 30, 2010 6:008:00, Closed Book Name : Solution All solutions must provide units as appropriate. Unless otherwise stated, assume T = 300 K. 1. (25 pts) Consider the amplifier shown
More informationChapter 20. Current Mirrors. Basics. Cascoding. Biasing Circuits. Baker Ch. 20 Current Mirrors. Introduction to VLSI
Chapter 20 Current Mirrors Basics Long Channel Matching Biasing Short Channel Temperature Subthreshold Cascoding Simple Low Voltage, Wide Swing Wide Swing, Short Channel Regulated Drain Biasing Circuits
More informationLecture 10 MOSFET (III) MOSFET Equivalent Circuit Models
Lecture 10 MOSFET (III) MOSFET Equivalent Circuit Models Outline Lowfrequency smallsignal equivalent circuit model Highfrequency smallsignal equivalent circuit model Reading Assignment: Howe and Sodini;
More informationMicroelectronics Main CMOS design rules & basic circuits
GBM8320 Dispositifs médicaux intelligents Microelectronics Main CMOS design rules & basic circuits Mohamad Sawan et al. Laboratoire de neurotechnologies Polystim mohamad.sawan@polymtl.ca M5418 6 & 7 September
More informationDC and Transient Responses (i.e. delay) (some comments on power too!)
DC and Transient Responses (i.e. delay) (some comments on power too!) Michael Niemier (Some slides based on lecture notes by David Harris) 1 Lecture 02  CMOS Transistor Theory & the Effects of Scaling
More informationMOS Transistor Theory
CHAPTER 3 MOS Transistor Theory Outline 2 1. Introduction 2. Ideal IV Characteristics 3. Nonideal IV Effects 4. CV Characteristics 5. DC Transfer Characteristics 6. Switchlevel RC Delay Models MOS
More informationCMPEN 411 VLSI Digital Circuits. Lecture 04: CMOS Inverter (static view)
CMPEN 411 VLSI Digital Circuits Lecture 04: CMOS Inverter (static view) Kyusun Choi [Adapted from Rabaey s Digital Integrated Circuits, Second Edition, 2003 J. Rabaey, A. Chandrakasan, B. Nikolic] CMPEN
More informationLecture 13  Digital Circuits (II) MOS Inverter Circuits. March 20, 2003
6.012 Microelectronic Devices and Circuits Spring 2003 Lecture 131 Lecture 13 Digital Circuits (II) MOS Inverter Circuits March 20, 2003 Contents: 1. NMOS inverter with resistor pullup (cont.) 2. NMOS
More informationLecture 18. Common Source Stage
ecture 8 OUTINE Basic MOSFET amplifier MOSFET biasing MOSFET current sources Common source amplifier eading: Chap. 7. 7.7. EE05 Spring 008 ecture 8, Slide Prof. Wu, UC Berkeley Common Source Stage λ =
More informationECE 546 Lecture 10 MOS Transistors
ECE 546 Lecture 10 MOS Transistors Spring 2018 Jose E. SchuttAine Electrical & Computer Engineering University of Illinois jesa@illinois.edu NMOS Transistor NMOS Transistor NChannel MOSFET Built on ptype
More informationEE 330 Lecture 16. MOSFET Modeling CMOS Process Flow
EE 330 Lecture 16 MOSFET Modeling CMOS Process Flow Model Extensions 300 Id 250 200 150 100 50 300 0 0 1 2 3 4 5 Vds Existing Model 250 200 Id 150 100 50 Slope is not 0 0 0 1 2 3 4 Actual Device Vds Model
More informationEE 330 Lecture 17. MOSFET Modeling CMOS Process Flow
EE 330 Lecture 17 MOSFET Modeling CMOS Process Flow Review from Last Lecture Limitations of Existing Models V DD V OUT V OUT V DD?? V IN V OUT V IN V IN V DD SwitchLevel Models V DD Simple squarelaw
More informationEE105 Fall 2014 Microelectronic Devices and Circuits. NMOS Transistor Capacitances: Saturation Region
EE105 Fall 014 Microelectronic Devices and Circuits Prof. Ming C. Wu wu@eecs.berkeley.edu 511 Sutardja Dai Hall (SDH) 1 NMOS Transistor Capacitances: Saturation Region Drain no longer connected to channel
More informationEE105  Fall 2006 Microelectronic Devices and Circuits. Some Administrative Issues
EE105  Fall 006 Microelectronic evices and Circuits Prof. Jan M. Rabaey (jan@eecs Lecture 8: MOS Small Signal Model Some Administrative Issues REIEW Session Next Week Tu Sept 6 6:007:30pm; 060 alley
More informationECE 497 JS Lecture  12 Device Technologies
ECE 497 JS Lecture  12 Device Technologies Spring 2004 Jose E. SchuttAine Electrical & Computer Engineering University of Illinois jose@emlab.uiuc.edu 1 NMOS Transistor 2 ρ Source channel charge density
More informationLecture 5: CMOS Transistor Theory
Lecture 5: CMOS Transistor Theory Slides courtesy of Deming Chen Slides based on the initial set from David Harris CMOS VLSI Design Outline q q q q q q q Introduction MOS Capacitor nmos IV Characteristics
More informationLecture 4: CMOS Transistor Theory
Introduction to CMOS VLSI Design Lecture 4: CMOS Transistor Theory David Harris, Harvey Mudd College Kartik Mohanram and Steven Levitan University of Pittsburgh Outline q Introduction q MOS Capacitor q
More informationEECS 141: FALL 05 MIDTERM 1
University of California College of Engineering Department of Electrical Engineering and Computer Sciences D. Markovic TuTh 111:3 Thursday, October 6, 6:38:pm EECS 141: FALL 5 MIDTERM 1 NAME Last SOLUTION
More informationHomework Assignment 08
Homework Assignment 08 Question 1 (Short Takes) Two points each unless otherwise indicated. 1. Give one phrase/sentence that describes the primary advantage of an active load. Answer: Large effective resistance
More informationEE 230 Lecture 33. Nonlinear Circuits and Nonlinear Devices. Diode BJT MOSFET
EE 230 Lecture 33 Nonlinear Circuits and Nonlinear Devices Diode BJT MOSFET Review from Last Time: nchannel MOSFET Source Gate L Drain W L EFF Poly Gate oxide nactive psub depletion region (electrically
More informationCommon Drain Stage (Source Follower) Claudio Talarico, Gonzaga University
Common Drain Stage (Source Follower) Claudio Talarico, Gonzaga University Common Drain Stage v gs v i  v o V DD v bs  v o R S Vv IN i v i G C gd C+C gd gb B&D v s vv OUT o + V S I B R L C L v gs  C
More informationName: Answers. Grade: Q1 Q2 Q3 Q4 Q5 Total. ESE370 Fall 2015
University of Pennsylvania Department of Electrical and System Engineering CircuitLevel Modeling, Design, and Optimization for Digital Systems ESE370, Fall 2015 Midterm 1 Monday, September 28 5 problems
More informationECE 546 Lecture 11 MOS Amplifiers
ECE 546 Lecture MOS Amplifiers Spring 208 Jose E. SchuttAine Electrical & Computer Engineering University of Illinois jesa@illinois.edu ECE 546 Jose Schutt Aine Amplifiers Definitions Used to increase
More informationECE 342 Solid State Devices & Circuits 4. CMOS
ECE 34 Solid State Devices & Circuits 4. CMOS Jose E. SchuttAine Electrical & Computer Engineering University of Illinois jschutt@emlab.uiuc.edu ECE 34 Jose Schutt Aine 1 Digital Circuits V IH : Input
More informationCMOS INVERTER. Last Lecture. Metrics for qualifying digital circuits. »Cost» Reliability» Speed (delay)»performance
CMOS INVERTER Last Lecture Metrics for qualifying digital circuits»cost» Reliability» Speed (delay)»performance 1 Today s lecture The CMOS inverter at a glance An MOS transistor model for manual analysis
More informationAnnouncements. EE141 Fall 2002 Lecture 7. MOS Capacitances Inverter Delay Power
 Fall 2002 Lecture 7 MOS Capacitances Inverter Delay Power Announcements Wednesday 123pm lab cancelled Lab 4 this week Homework 2 due today at 5pm Homework 3 posted tonight Today s lecture MOS capacitances
More informationIntroduction to CMOS VLSI. Chapter 2: CMOS Transistor Theory. Harris, 2004 Updated by Li Chen, Outline
Introduction to MOS VLSI Design hapter : MOS Transistor Theory copyright@david Harris, 004 Updated by Li hen, 010 Outline Introduction MOS apacitor nmos IV haracteristics pmos IV haracteristics Gate and
More informationLecture 5: DC & Transient Response
Lecture 5: DC & Transient Response Outline q Pass Transistors q DC Response q Logic Levels and Noise Margins q Transient Response q RC Delay Models q Delay Estimation 2 Activity 1) If the width of a transistor
More informationEEC 118 Lecture #2: MOSFET Structure and Basic Operation. Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation
EEC 118 Lecture #2: MOSFET Structure and Basic Operation Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation Announcements Lab 1 this week, report due next week Bring
More informationECE 6412, Spring Final Exam Page 1 FINAL EXAMINATION NAME SCORE /120
ECE 6412, Spring 2002 Final Exam Page 1 FINAL EXAMINATION NAME SCORE /120 Problem 1O 2O 3 4 5 6 7 8 Score INSTRUCTIONS: This exam is closed book with four sheets of notes permitted. The exam consists of
More informationLecture 5 Review Current Source Active Load Modified Large / Small Signal Models Channel Length Modulation
Lecture 5 Review Current Source Active Load Modified Large / Small Signal Models Channel Length Modulation Text sec 1.2 pp. 2832; sec 3.2 pp. 128129 Current source Ideal goal Small signal model: Open
More informationChapter 4 FieldEffect Transistors
Chapter 4 FieldEffect Transistors Microelectronic Circuit Design Richard C. Jaeger Travis N. Blalock 5/5/11 Chap 41 Chapter Goals Describe operation of MOSFETs. Define FET characteristics in operation
More informationLecture 10 MOSFET (III) MOSFET Equivalent Circuit Models
Lecture 1 MOSFET (III) MOSFET Equivalent Circuit Models Outline Lowfrequency smallsignal equivalent circuit model Highfrequency smallsignal equivalent circuit model Reading Assignment: Howe and Sodini;
More informationECE 342 Electronic Circuits. Lecture 6 MOS Transistors
ECE 342 Electronic Circuits Lecture 6 MOS Transistors Jose E. SchuttAine Electrical & Computer Engineering University of Illinois jesa@illinois.edu 1 NMOS Transistor Typically L = 0.1 to 3 m, W = 0.2
More informationCMPEN 411 VLSI Digital Circuits. Lecture 03: MOS Transistor
CMPEN 411 VLSI Digital Circuits Lecture 03: MOS Transistor Kyusun Choi [Adapted from Rabaey s Digital Integrated Circuits, Second Edition, 2003 J. Rabaey, A. Chandrakasan, B. Nikolic] CMPEN 411 L03 S.1
More informationLecture 310 OpenLoop Comparators (3/28/10) Page 3101
Lecture 310 OpenLoop Comparators (3/28/10) Page 3101 LECTURE 310 OPENLOOP COMPARATORS LECTURE ORGANIZATION Outline Characterization of comparators Dominant pole, openloop comparators Twopole, openloop
More informationMOS Transistors. Prof. Krishna Saraswat. Department of Electrical Engineering Stanford University Stanford, CA
MOS Transistors Prof. Krishna Saraswat Department of Electrical Engineering S Stanford, CA 94305 saraswat@stanford.edu 1 1930: Patent on the FieldEffect Transistor! Julius Lilienfeld filed a patent describing
More informationUniversity of Toronto. Final Exam
University of Toronto Final Exam Date  Dec 16, 013 Duration:.5 hrs ECE331 Electronic Circuits Lecturer  D. Johns ANSWER QUESTIONS ON THESE SHEETS USING BACKS IF NECESSARY 1. Equation sheet is on last
More informationEE 434 Lecture 33. Logic Design
EE 434 Lecture 33 Logic Design Review from last time: Ask the inverter how it will interpret logic levels V IN V OUT V H =? V L =? V LARGE V H V L V H Review from last time: The twoinverter loop X Y X
More informationCMOS Technology for Computer Architects
CMOS Technology for Computer Architects Recap Technology Trends Lecture 2: Transistor Inverter Iakovos Mavroidis Giorgos Passas Manolis Katevenis FORTHICS (University of Crete) 1 2 Recap Threshold Voltage
More informationEE 330 Lecture 22. Small Signal Modelling Operating Points for Amplifier Applications Amplification with Transistor Circuits
EE 330 Lecture 22 Small Signal Modelling Operating Points for Amplifier Applications Amplification with Transistor Circuits Exam 2 Friday March 9 Exam 3 Friday April 13 Review Session for Exam 2: 6:00
More informationIntegrated Circuits & Systems
Federal University of Santa Catarina Center for Technology Computer Science & Electronics Engineering Integrated Circuits & Systems INE 5442 Lecture 12 The CMOS Inverter: static behavior guntzel@inf.ufsc.br
More informationEE 230 Lecture 31. THE MOS TRANSISTOR Model Simplifcations THE Bipolar Junction TRANSISTOR
EE 23 Lecture 3 THE MOS TRANSISTOR Model Simplifcations THE Bipolar Junction TRANSISTOR Quiz 3 Determine I X. Assume W=u, L=2u, V T =V, uc OX =  4 A/V 2, λ= And the number is? 3 8 5 2? 6 4 9 7 Quiz 3
More informationDesign of Analog Integrated Circuits
Design of Analog Integrated Circuits Chapter 11: Introduction to Switched Capacitor Circuits Textbook Chapter 13 13.1 General Considerations 13.2 Sampling Switches 13.3 SwitchedCapacitor Amplifiers 13.4
More information3. Design a stick diagram for the PMOS logic shown below [16] Y = (A + B).C. 4. Design a layout diagram for the CMOS logic shown below [16]
Code No: RR420203 Set No. 1 1. (a) Find g m and r ds for an nchannel transistor with V GS = 1.2V; V tn = 0.8V; W/L = 10; µncox = 92 µa/v 2 and V DS = Veff + 0.5V The out put impedance constant. λ = 95.3
More informationDigital Electronics Part II  Circuits
Digital Electronics Part  Circuits Dr.. J. Wassell Gates from Transistors ntroduction Logic circuits are nonlinear, consequently we will introduce a graphical technique for analysing such circuits The
More information6.012 Electronic Devices and Circuits
Page 1 of 12 YOUR NAME Department of Electrical Engineering and Computer Science Massachusetts Institute of Technology 6.012 Electronic Devices and Circuits FINAL EXAMINATION Open book. Notes: 1. Unless
More informationAssignment 3 ELEC 312/Winter 12 R.Raut, Ph.D.
Page 1 of 3 ELEC 312: ELECTRONICS II : ASSIGNMENT3 Department of Electrical and Computer Engineering Winter 2012 1. A commonemitter amplifier that can be represented by the following equivalent circuit,
More informationIntroduction and Background
Analog CMOS Integrated Circuit Design Introduction and Background Dr. Jawdat AbuTaha Department of Electrical and Computer Engineering Islamic University of Gaza jtaha@iugaza.edu.ps 1 Marking Assignments
More informationThe Devices. Digital Integrated Circuits A Design Perspective. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic. July 30, 2002
Digital Integrated Circuits A Design Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic The Devices July 30, 2002 Goal of this chapter Present intuitive understanding of device operation Introduction
More informationEE105  Fall 2005 Microelectronic Devices and Circuits
EE105  Fall 005 Microelectronic Devices and Circuits ecture 7 MOS Transistor Announcements Homework 3, due today Homework 4 due next week ab this week Reading: Chapter 4 1 ecture Material ast lecture
More informationGEORGIA INSTITUTE OF TECHNOLOGY School of Electrical and Computer Engineering
NAME: GEORGIA INSTITUTE OF TECHNOLOGY School of Electrical and Computer Engineering ECE 4430 Third Exam Closed Book and Notes Fall 2002 November 27, 2002 General Instructions: 1. Write on one side of the
More informationLecture 11: MOSFET Modeling
Digital Integrated Circuits (83313) Lecture 11: MOSFET ing Semester B, 201617 Lecturer: Dr. Adam Teman TAs: Itamar Levi, Robert Giterman 18 June 2017 Disclaimer: This course was prepared, in its entirety,
More informationVLSI Design The MOS Transistor
VLSI Design The MOS Transistor Frank Sill Torres Universidade Federal de Minas Gerais (UFMG), Brazil VLSI Design: CMOS Technology 1 Outline Introduction MOS Capacitor nmos IV Characteristics pmos IV
More informationBipolar Junction Transistor (BJT)  Introduction
Bipolar Junction Transistor (BJT)  Introduction It was found in 1948 at the Bell Telephone Laboratories. It is a three terminal device and has three semiconductor regions. It can be used in signal amplification
More informationCHAPTER 5 MOS FIELDEFFECT TRANSISTORS
CHAPTER 5 MOS FIELDEFFECT TRANSISTORS 5.1 The MOS capacitor 5.2 The enhancementtype NMOS transistor 5.3 IV characteristics of enhancement mode MOSFETS 5.4 The PMOS transistor and CMOS technology 5.5
More informationIntegrated Circuits & Systems
Federal University of Santa Catarina Center for Technology Computer Science & Electronics Engineering Integrated Circuits & Systems INE 5442 Lecture 10 MOSFET part 1 guntzel@inf.ufsc.br ualwell TrenchIsolated
More informationObjective and Outline. Acknowledgement. Objective: Power Components. Outline: 1) Acknowledgements. Section 4: Power Components
Objective: Power Components Outline: 1) Acknowledgements 2) Objective and Outline 1 Acknowledgement This lecture note has been obtained from similar courses all over the world. I wish to thank all the
More informationEE5311 Digital IC Design
EE5311 Digital IC Design Module 1  The Transistor Janakiraman V Assistant Professor Department of Electrical Engineering Indian Institute of Technology Madras Chennai October 28, 2017 Janakiraman, IITM
More informationLecture 12 Circuits numériques (II)
Lecture 12 Circuits numériques (II) Circuits inverseurs MOS Outline NMOS inverter with resistor pullup The inverter NMOS inverter with currentsource pullup Complementary MOS (CMOS) inverter Static analysis
More informationEE105  Fall 2006 Microelectronic Devices and Circuits
EE105  Fall 2006 Microelectronic Devices and Circuits Prof. Jan M. Rabaey (jan@eecs) Lecture 7: MOS Transistor Some Administrative Issues Lab 2 this week Hw 2 due on We Hw 3 will be posted same day MIDTERM
More informationEE 435. Lecture 3 Spring Design Space Exploration with applications to singlestage amplifier design
EE 435 Lecture 3 Spring 2016 Design Space Exploration with applications to singlestage amplifier design 1 Review from last lecture: Singleended Op Amp Inverting Amplifier V IN R 1 V 1 R 2 A V V OUT
More informationEE 435. Lecture 3 Spring Design Space Exploration with applications to singlestage amplifier design
EE 435 ecture 3 Spring 2019 Design Space Exploration with applications to singlestage amplifier design 1 Review from last lecture: Singleended Op Amp Inverting Amplifier V IN R 1 V 1 R 2 A V V OUT
More informationImportant! EE141 Fall 2002 Lecture 5. CMOS Inverter MOS Transistor Model
 Fall 00 Lecture 5 CMO Inverter MO Transistor Model Important! Lab 3 this week You must show up in one of the lab sessions this week If you don t show up you will be dropped from the class» Unless you
More informationLecture 24 Multistage Amplifiers (I) MULTISTAGE AMPLIFIER
Lecture 24 Multistage Amplifiers (I) MULTISTAGE AMPLIFIER Outline. Introduction 2. CMOS multistage voltage amplifier 3. BiCMOS multistage voltage amplifier 4. BiCMOS current buffer 5. Coupling amplifier
More information