ECE-342 Test 3: Nov 30, :00-8:00, Closed Book. Name : Solution

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1 ECE-342 Test 3: Nov 30, :00-8:00, Closed Book Name : Solution All solutions must provide units as appropriate. Unless otherwise stated, assume T = 300 K. 1. (25 pts) Consider the amplifier shown below. (a) Solve for the DC bias conditions (Specify I E, I C, I B, V E, V C, V B.) Please ignore base-width modulation (assume V A = ) in determining the DC bias. (b) Redraw the equivalent small-signal model of the amplifier using the hybrid-π model. (Assume mid-band frequencies.) (c) Specify the values of all small-signal parameters Solution: (a) (b) I E = 0.1 ma I C = β β + 1 I E =.098 ma I B = I E = 2.44 µa β + 1 V E = (75 Ω)(.1 ma) = 7.5 mv V B = V E = V V C = V B + (100 kω)(2.44 µa) = V (c) = I C V T r π = β =.098 ma = = 3.78 ma/v 25.8 mv 40 = kω A/V r o = V A = 50 V = kω I C.098 ma

2 2. (10 pts) The amplifier of problem 1 is reproduced below (for a changed bias current, and a changed transistor). A small-signal analysis has been completed to give R in = 263 Ω R out = 87.3 kω A vo = v out v in = 230 RL = Evaluate the voltage gain of the amplifier, v out /v sig. Solution: First use voltage division to get v in (using R in ). Then apply the open circuit gain to get the open-circuit output voltage. Finally, use voltage division to find the output voltage for the applied load. ( ) ( ) v out = (230) = v sig

3 3. (25 pts) The circuit below shows a common-emitter amplifier. You could verify (I hope) that the bias current of the transistor is I C 50 µa. (a) For mid-band frequencies (where the impedance of both capacitors is negligible), derive the amplifier gain, input resistance R in, and output resistance R out. (b) Derive the transfer function v out (s)/v in (s) in terms of the input capacitor value, and sketch the Bode diagram for the amplifier. (Continue to assume that the emitter capacitor has negligible impedance.) (c) Find the restrictions on the input capacitor C so that the amplifier gain is within 3 db of its mid-band gain value for all frequencies above 200 Hz. Solution: The equivalent small-signal model is shown below. I ve included the input capacitance for parts 3b and 3c, although for the first part the capacitor is a short circuit (1/Cs is assumed negligible). = I C 50 µa = V T 25.8 mv = ma/v r π = β = 51.6 kω (a) (shorting the input capacitor) The input resistance and output resistance can be seen by inspection. (For the output resistance, the input source is killed, giving v be = 0. So the controlled current source is off.) R in = 100 kω 170 kω r π = kω R out = 80 kω At midband, v be = v in, giving The amplifier gain is 155 V/V. v out = v be (80 kω) = (80 kω)v in = 155v in (b) To take into account the input capacitor, use voltage division to find the value of v be (c) This gives v be = R in R in + 1/Cs v in = R incs R in Cs + 1 v in R in Cs v out = v be (80 kω) = ( 155) R in Cs + 1 v in v out(s) v in (s) = ( 155) R in Cs R in Cs + 1 The Bode diagram should show the midband gain of -155 (43.8 db), a zero at DC, and a pole at ω 3 db = 1/(R in C) (shown on next page). 1 2πR in C 200 Hz C 1 = 28.1 nf 2πR in (200 Hz)

4

5 4. (20 pts) A PMOS transistor fabricated in a technology for which k p = 300 µa/v 2 and V t = 0.5 V is required to operate with a small v SD as a variable resistor to the +1.8 V supply rail. The resistance must range in value from 100 Ω to 500 Ω. Specify the range required for the control voltage V G (not V GS or V SG ) and the required transistor width W. It is required to use the smallest possible device, as limited by the minimum channel length of this technology (L min =.18 µm) and the maximum allowed voltage of 1.8 V. Solution: The maximum source to gate voltage is 1.8 V, where we re required to have a 100 Ω resistance. 1 (300 µa/v 2 )(W/L)( ) = 100 Ω W L = 1 (300 µa/v 2 )(100 V/A)(1.3 V) = So, select W = 25.64(0.18 µm) = 4.61 µm The resistance will increase as the value of V SG drops. (The resistance is proportional to 1/V ov ). To get 5 times the resistance, drop V ov by a factor of 5, from 1.3 V down to 0.26 V. This corresponds to V SG = = 0.76 V. Since the source is tied to the +1.8 V supply, the gate voltages needed are found by subtracting the values of V SG from +1.8 V. 0 V (for 100 Ω) < V G < 1.04 V (for 500 Ω)

6 5. (20 pts) (a) Complete the design of the circuit below so that M 1 is saturated with I D = 1 ma. Find the restrictions on R 2 so that M 1 remains saturated. k n = 400 µa/v 2 W L = 20 λ = 0 V t = 0.4 V Solution: First, find the required overdrive voltage: I D = 1 ma = k W 2 L V OV 2 = (4 ma/v 2 )VOV 2 V OV = 0.5 V So we need V G = V t = 0.9 V. This determines R 1 = 10 kω For Saturation, we need V D V OV = 0.5 V This gives R kω 1.8 R 2 (1 ma) 0.5 V (b) Complete the design of the circuit below so that Q 1 is forward-active with I C = 1 ma. Find the restrictions on R 4 so that Q 1 remains forward-active. Solution: For I C = 1 ma, we ll have V E 9 V, V B 8.3 V, and I B = I C /β = 10 µa. Now solve for the unknown current I: (I + 10 µa)(200 kω) = 8.3 V I = 31.5 µa To get the required 1.7 V drop across R 3, set R 3 = 1.7/(31.5 µa) = kω Finally, select R 4 to make sure that V EC > 0.2 V. The result is R kω (1 ma)r V

7 ECE-342 Test 3, Fall 2010 (Last Page) ( i C = αi E = βi B = I s e v BE/V T 1 + v ) CE V A V T = kt q 25.8 mv at T = 300 K α = β β + 1 i D = k W L [ (v GS V t )v DS 1 ] 2 v2 DS i D = k W 2 L (v GS V t ) 2 (1 + λv DS ) λ = 1 = λ V A L k 1 = µ n C ox = k W r DS L (V GS V t ) = k W L V OV [ 2φf V t = V t0 + γ + V SB ] 2φ f = I C r 0 = V A + V CE V A V T I C I C r π = β r e = α

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