ECE 6412, Spring Final Exam Page 1

Size: px
Start display at page:

Download "ECE 6412, Spring Final Exam Page 1"

Transcription

1 ECE 64, Spring 005 Final Exam Page FINAL EXAMINATION SOLUTIONS (Average score = 89/00) Problem (0 points This problem is required) A comparator consists of an amplifier cascaded with a latch as shown below. The amplifier has a voltage gain of 0V/V and f 3dB = 00MHz and the latch has a time constant of 0ns. The maximum and minimum voltage swings of the amplifier and latch are V OH and V OL. When should the latch be enabled after the application of a step input to the amplifier of 0.05(V OH V OL ) to get minimum overall propagation time delay? What is the value of the minimum propagation time delay? It may useful to recall that the propagation time delay of the latch is given ast p = L ln V OH V OL v where v il is the latch il input ( V i of the text). v in = 0.05(V OH V OL ) t=0 Amplifier A v (0)=0V/V f 3dB =00MHz The solution is based on the figure shown. We note that, v oa (t) = 0[e 3dBt ]0.05(V OH V OL ). If we define the input voltage to the latch as, v il = x (V OH V OL ) then we can solve for t and t as follows: x (V OH V OL ) = 0[e 3dBt]0.05(V OH V OL ) x = 0.5[e 3dBt] This gives, t = ln 3dB x From the propagation time delay of the latch we get, t = L ln V OH V OL v = L ln il x v oa v il Comparator Enable Latch τ L =0ns v out S0E3P t p = t t = ln 3dB x L ln x dt p dx = 0 gives x = = t = 0ns ln ( ) =.59ns.9856 = 3.6ns and t = 0ns ln =.477ns t p = t t = 3.6ns.477ns = 4.637ns V OH x(v OH V OL ) V OL Amplifier t Latch t t S0E3S

2 ECE 64, Spring 005 Final Exam Page Problem (0 points This problem is required) If the foldedcascode op amp shown having a smallsignal voltage gain of 7464V/V is used as a comparator, find the dominant pole if C L = 5pF. If the input step is 0mV, determine whether the response is linear or slewing and find the propagation delay time. Assume the parameters of the NMOS transistors are K N =0V/μA, V TN = 0.7V, N =0.04V and for the PMOS transistors are K P =50V/μA, V TP = 0.7V, P =0.05V. VBias M4.5V 80μm/μm I 4 = 5μA 80μm/μm I 5 = M5 5μA v in I I M6 M7 80μm/μm 80μm/μm M M I 6 I7 36μm.3V v out μm R = I 9 kω C L M8 M9 M3 I 3 = 36μm 36μm/μm 00μA μm M0 M VBias 36μm/μm 36μm/μm.5V S0FEP V OH and V OL can be found from many approaches. The easiest is simply to assume that V OH and V OL are.5v and.5v, respectively. However, no matter what the input, the values of V OH and V OL will be in the following range, (V DD V ON )< V OH < V DD and V DD < V OH < (V SS V ON ) The reasoning is as follows, suppose V in >0. This gives I >I which gives I 6 <I 7 which gives I 9 <I 7. V out will increase until I 7 equals I 9. The only way this can happen is for M5 and M7 to leave saturation. The same reasoning holds for V in <0. Therefore assuming that V OH and V OL are.5v and.5v, respectively, we get V in (min) = 5V 7464 = 0.67mV k = 0mV 0.67mV = 4.93

3 ECE 64, Spring 005 Final Exam Page 3 Problem Continued The foldedcascode op amp as a comparator can be modeled by a single dominant pole. This pole is found as, p = R out C L where R out g m9 r ds9 r ds [g m7 r ds7 (r ds r ds5 )] g m9 = =77μS, g ds9 =g ds =75x = 3μS, g ds =50x0 6 (0.04)=μS g m7 = =775μS, g ds5 =5x = 6.5μS, g ds7 =50x0 6 (0.05)=3.75μS g m9 r ds9 r ds = (77μS) 3μS 3μS = 85.67M g m7 r ds7 (r ds r ds5 (775μS) 3.75μS μs 6.5μS = 5.05M, R out = 9.4 The dominant pole is found as, p = The time constant is = 96.9μs. R out C = L 9.4x0 6 5pF = 0,38 rps For a dominant pole system, the step response is, v out (t) = A vd (e t/ )V in The slope is the largest at t = 0. Evaluating this slope gives, dv out dt = A vd e t/ V in For t = 0, the slope is A vd V in = μs (0mV) = 0.77V/μs The slew rate of this op amp/comparator is SR = I 3 C L = 00μA 5pF = 0V/μs Therefore, the comparator does not slew and its propagation delay time is found from the linear response as, t P = ln k k = 96.9μs ln =( 96.9μs)(0.034) = 3.3μs

4 ECE 64, Spring 005 Final Exam Page 4 Problem 3 (0 points This problem is optional) An source follower, pushpull output stage is shown. Assume the parameters of the NMOS transistors are 00µA K N =0V/μA, V TN = 0.7V, N =0.04V and for the PMOS transistors are K P =50V/μA, V TP = 0.7V, P =0.05V. a.) If W /L = W /L = 0, find the W 3 /L 3 and W 4 /L 4 so that the drain current in M3 and M4 is ma when v IN = v OUT = 0. v IN b.) What is the ±peak output voltage of this amplifier? Assume the 00 A sources can have a minimum voltage across them of 0.V. c.) What is the ±slew rate of this amplifier in V/ s? R in 00µA M M V M4 V R out M3 00pF 00Ω S05FEP3 vout d.) What is the smallsignal input and output resistance of this amplifier when v IN = v OUT = 0? (Do not include the load resistance in the output resistance.) a.) With v IN = v OUT = 0, the W/L ratios of M3 and M4 are given by the current ratios. Thus, W 3 /L 3 = W 4 /L 4 = 00. b.) The current limit due to ma is ±V. Check to see if voltage limit is less. V GS4 (ma) = ma 0.7 = =.6V 0 00 V out (max) = 0..6 = 0.674V V GS3 (ma) = ma 0.7 = =.33V V out (min) = = 0.467V c.) The slew rate is ±SR = ma 00pF = 0V/ s d.) R in =. R out = g m3 g m4 g m3 = μs = 3.6mS R out = g m4 = μs = 4.69mS = 7

5 ECE 64, Spring 005 Final Exam Page 5 Problem 4 (0 points This problem is optional) The simplified schematic of a feedback amplifier V CC is shown. Use the method of feedback analysis R 3 = to find v /v, R in = v /i, and R out = v /i. 0kΩ Assume that all transistors are matched and that ß R = Q i = 00, r = 5k and r o =. 0kΩ R Q 4 = Q3 0kΩ i Openloop, quasiac model: v Smallsignal, openloop model: R = R 5 = R 6 = v kω 0kΩ kω i R = 0k v v s R = R4 = k 0k Q Q Q3 R 3 = 0k R 5 = 0k v f R 4 = 0k R 6 = k R = k i v o V EE R = i i b ßi i 0k b i b3 b r r v R v s 4 = R = r R4 = R 3 = R 5 = ßi 0k k 0k 0k 0k b3 v ßi f R = R 6 = b k k S0FEP5 i v o R i = v s = r i b (ß)(R R 4 ) = 5k (0)(k 0k ) = 0.9k a = v o = v o v s i b3 i b3 i b i b i b i b v s = (ß)[R 6 (R R 4 )] ßR 5 R 5 r (ß)[R 6 (R R 4 )] ßR 3 R 3 r R i = [(0)(954.55)](8.976)(66.67)(/0.9k ) = V/V R f = = R R 4 = and R o = v o = R i 6 (R R 4 ) r R 5 ß = 8.5 Closedloop quantities are: A vf = v o a = v s af = = 0.5, R if = (af)r i =.848M R out = R of = R o A v ß f = = R in = R R if =.858M and v R if = A v vf = 0.8 V/V R R if

6 ECE 64, Spring 005 Final Exam Page 6 Problem 5 (0 points This problem is optional) A twostage, BiCMOS op amp is shown. For the PMOS transistors, the model.5v parameters are K P =50μA/V, V TP = 0.7V and P = 0.05V 0/ 0/. For the NPN 0/ M8 M5 M7 BJTs, the model parameters are F = 00, 50μA v V CE (sat) = 0.V, V A = 5V, V t = 6mV, out v v C c = I s = 0fA and n=. (a.) Identify which 0/ 0/ 5pF input is positive and which input is M M negative. (b.) Find the numerical values of differential voltage gain, A v (0), GB (in W/L ratios in microns Hertz), the slew rate, SR, and the location Q3 Q4 of the RHP zero. (c.) Find the numerical Q6 value of the maximum and minimum input common mode voltages. S0EP.5V (a.) The plus and minus signs on the schematic show which input is positive and negative. (b.) The differential voltage gain, A v (0), is given as g m g m6 A v (0) = g ds g o4 g 6 g ds7 g o6 r ds = g m = g m = = 58. S 0 = P I D 5 A = 0.8M, r o4 = V A = 5V I C 5 A = M, g m6 = I C = 00 A V t 6mV = 3846 S r 6 = F g m6 = 6k, r ds7 = GB = g m C c SR = 50 A 5pF P I D = 0 00 A = 0.M and r o6 = V A I C = 5V 00 A = 0.5M A v (0) = [58.( )][3846(0. 0.5)]= =,659.6V/V RHP zero = g m6 C c = 58. S 5pF = 0V/ s = 3.6x0 6 rads/sec GB = 5.035MHz = 3.846mS 5pF = 769.4x0 6 rads/sec. (MHz) (c.) The maximum input common mode voltage is given as 50 v icm = V CC V DS5 (sat) V SG = = = 50 0 v icm = V v icm =.5 V BE3 V T =.5 V t ln 5 A 0fA 0.7 = =.6374V

7 ECE 64, Spring 005 Final Exam Page 7 Problem 6 (0 points This problem is optional) Find the midband voltage gain and the 3dB frequency in Hertz for the circuit shown. V in R =kω C = 0pF C =pf V R V = 00 00kΩ C 3 = 5pF The midband voltage gain can be expressed as, V out = V out V V = (0) R V in V V V in R 000 V R V 3 = 00 kω () = 9.9V/V C 4 = 0pF Finding the opencircuit, time constants: R CO : R CO = R = k R CO C = 0ns R CO : v t = R i t R i t V 00 V 00 But v t = V V and V = R i t, v t = R i t R i t R R i t 00 R v t 00 R CO = v t i t = R R 0.0R R 0.0R S05FEP6 = k 00k 000k =.099k R 000 CO C =.ns R C3O : R C3O = R 00 = 99.9 R C3O C 3 = 0.5ns R C4O : R C4O = R 3 = k R C4O C 4 = 0ns T oc = (0.0.50)ns =.6ns 3dB T oc = 44.5x0 6 f 3dB = 7.04 MHz i t v t R V V 000 i t R Vout V 000 V S05ES3

8 ECE 64, Spring 005 Final Exam Page 8 Problem 7 (0 points This problem is optional) Find an expression for the.5v equivalent input noise voltage of the circuit in the previous M9 problem, e eq, in terms of M8 M6 M7 the small signal model v v parameters and the individual 00μA M M equivalent input noise voltages, e ni, of each of the transistors (i = through 7). M0 M5 M3 Assume M and M, M3 and M4, and M6 and M7 are matched. Equivalent noise circuit: M4 S04FEP3 v out e n6 V DD * e n M6 * e n7 M7 v * M M * e n v e n3 e n4 v out M3 * * M4 V SS S99FES6 e out = (g m e n g m e n g m3 e n3 g m4 e n4 g m6 e n6 g m7 e n7 )R out e eq = e out (g m R out ) = e n e n g m3 g ( e n3 e n4 ) m g m6 g ( e n6 e n7 ) m If M through M are matched then g m = g m and we get g m3 g m6 e eq = e n g e n3 m3 g e m n6

ECE 6412, Spring Final Exam Page 1 FINAL EXAMINATION NAME SCORE /120

ECE 6412, Spring Final Exam Page 1 FINAL EXAMINATION NAME SCORE /120 ECE 6412, Spring 2002 Final Exam Page 1 FINAL EXAMINATION NAME SCORE /120 Problem 1O 2O 3 4 5 6 7 8 Score INSTRUCTIONS: This exam is closed book with four sheets of notes permitted. The exam consists of

More information

V in (min) and V in (min) = (V OH -V OL ) dv out (0) dt = A p 1 V in = = 10 6 = 1V/µs

V in (min) and V in (min) = (V OH -V OL ) dv out (0) dt = A p 1 V in = = 10 6 = 1V/µs ECE 642, Spring 2003 - Final Exam Page FINAL EXAMINATION (ALLEN) - SOLUTION (Average Score = 9/20) Problem - (20 points - This problem is required) An open-loop comparator has a gain of 0 4, a dominant

More information

PRACTICE PROBLEMS FOR CMOS ANALOG CIRCUIT DESIGN, 2 ND EDITION

PRACTICE PROBLEMS FOR CMOS ANALOG CIRCUIT DESIGN, 2 ND EDITION Practice Problems (5/27/07) Page PRACTICE PROBLEMS FOR CMOS ANALOG CIRCUIT DESIGN, 2 ND EDITION TECHNOLOGY Problem (044430E3P5) The following questions pertain to a standard npn BJT process. a.) Give the

More information

ECE 3050A, Spring 2004 Page 1. FINAL EXAMINATION - SOLUTIONS (Average score = 78/100) R 2 = R 1 =

ECE 3050A, Spring 2004 Page 1. FINAL EXAMINATION - SOLUTIONS (Average score = 78/100) R 2 = R 1 = ECE 3050A, Spring 2004 Page Problem (20 points This problem must be attempted) The simplified schematic of a feedback amplifier is shown. Assume that all transistors are matched and g m ma/v and r ds.

More information

Lecture 140 Simple Op Amps (2/11/02) Page 140-1

Lecture 140 Simple Op Amps (2/11/02) Page 140-1 Lecture 40 Simple Op Amps (2//02) Page 40 LECTURE 40 SIMPLE OP AMPS (READING: TextGHLM 425434, 453454, AH 249253) INTRODUCTION The objective of this presentation is:.) Illustrate the analysis of BJT and

More information

Lecture 150 Simple BJT Op Amps (1/28/04) Page 150-1

Lecture 150 Simple BJT Op Amps (1/28/04) Page 150-1 Lecture 50 Simple BJT Op Amps (/28/04) Page 50 LECTURE 50 SIMPLE BJT OP AMPS (READING: TextGHLM 425434, 453454, AH 249253) INTRODUCTION The objective of this presentation is:.) Illustrate the analysis

More information

Lecture 310 Open-Loop Comparators (3/28/10) Page 310-1

Lecture 310 Open-Loop Comparators (3/28/10) Page 310-1 Lecture 310 Open-Loop Comparators (3/28/10) Page 310-1 LECTURE 310 OPEN-LOOP COMPARATORS LECTURE ORGANIZATION Outline Characterization of comparators Dominant pole, open-loop comparators Two-pole, open-loop

More information

ECE-343 Test 2: Mar 21, :00-8:00, Closed Book. Name : SOLUTION

ECE-343 Test 2: Mar 21, :00-8:00, Closed Book. Name : SOLUTION ECE-343 Test 2: Mar 21, 2012 6:00-8:00, Closed Book Name : SOLUTION 1. (25 pts) (a) Draw a circuit diagram for a differential amplifier designed under the following constraints: Use only BJTs. (You may

More information

LECTURE 380 TWO-STAGE OPEN-LOOP COMPARATORS - II (READING: AH ) Trip Point of an Inverter

LECTURE 380 TWO-STAGE OPEN-LOOP COMPARATORS - II (READING: AH ) Trip Point of an Inverter Lecture 380 Two-Stage Open-Loop Comparators-II (4/5/02) Page 380-1 LECTURE 380 TWO-STAGE OPEN-LOOP COMPARATORS - II (READING: AH 445-461) Trip Point of an Inverter V DD In order to determine the propagation

More information

6.2 INTRODUCTION TO OP AMPS

6.2 INTRODUCTION TO OP AMPS Introduction to Op Amps (7/17/00) Page 1 6.2 INTRODUCTION TO OP AMPS INTRODUCTION Objective The objective of this presentation is: 1.) Characterize the operational amplifier 2.) Illustrate the analysis

More information

Lecture 320 Improved Open-Loop Comparators and Latches (3/28/10) Page 320-1

Lecture 320 Improved Open-Loop Comparators and Latches (3/28/10) Page 320-1 Lecture 32 Improved OpenLoop Comparators and es (3/28/1) Page 321 LECTURE 32 IMPROVED OPENLOOP COMPARATORS AND LATCHES LECTURE ORGANIZATION Outline Autozeroing Hysteresis Simple es Summary CMOS Analog

More information

Errata of CMOS Analog Circuit Design 2 nd Edition By Phillip E. Allen and Douglas R. Holberg

Errata of CMOS Analog Circuit Design 2 nd Edition By Phillip E. Allen and Douglas R. Holberg Errata nd Ed. (0/9/07) Page Errata of CMOS Analog Circuit Design nd Edition By Phillip E. Allen and Douglas R. Holberg Page Errata 8 Line 4 after figure 3.3, CISW CJSW 0 Line from bottom: F F 5 Replace

More information

ECE 438: Digital Integrated Circuits Assignment #4 Solution The Inverter

ECE 438: Digital Integrated Circuits Assignment #4 Solution The Inverter ECE 438: Digital Integrated Circuits Assignment #4 The Inverter Text: Chapter 5, Digital Integrated Circuits 2 nd Ed, Rabaey 1) Consider the CMOS inverter circuit in Figure P1 with the following parameters.

More information

Errata of CMOS Analog Circuit Design 2 nd Edition By Phillip E. Allen and Douglas R. Holberg

Errata of CMOS Analog Circuit Design 2 nd Edition By Phillip E. Allen and Douglas R. Holberg Errata 2 nd Ed. (5/22/2) Page Errata of CMOS Analog Circuit Design 2 nd Edition By Phillip E. Allen and Douglas R. Holberg Page Errata 82 Line 4 after figure 3.2-3, CISW CJSW 88 Line between Eqs. (3.3-2)

More information

and V DS V GS V T (the saturation region) I DS = k 2 (V GS V T )2 (1+ V DS )

and V DS V GS V T (the saturation region) I DS = k 2 (V GS V T )2 (1+ V DS ) ECE 4420 Spring 2005 Page 1 FINAL EXAMINATION NAME SCORE /100 Problem 1O 2 3 4 5 6 7 Sum Points INSTRUCTIONS: This exam is closed book. You are permitted four sheets of notes (three of which are your sheets

More information

Lecture 37: Frequency response. Context

Lecture 37: Frequency response. Context EECS 05 Spring 004, Lecture 37 Lecture 37: Frequency response Prof J. S. Smith EECS 05 Spring 004, Lecture 37 Context We will figure out more of the design parameters for the amplifier we looked at in

More information

Lecture 400 Discrete-Time Comparators (4/8/02) Page 400-1

Lecture 400 Discrete-Time Comparators (4/8/02) Page 400-1 Lecture 400 DiscreteTime omparators (4/8/02) Page 4001 LETURE 400 DISRETETIME OMPARATORS (LATHES) (READING: AH 475483) Objective The objective of this presentation is: 1.) Illustrate discretetime comparators

More information

CMOS Inverter (static view)

CMOS Inverter (static view) Review: Design Abstraction Levels SYSTEM CMOS Inverter (static view) + MODULE GATE [Adapted from Chapter 5. 5.3 CIRCUIT of G DEVICE Rabaey s Digital Integrated Circuits,, J. Rabaey et al.] S D Review:

More information

CHAPTER 6 CMOS OPERATIONAL AMPLIFIERS

CHAPTER 6 CMOS OPERATIONAL AMPLIFIERS Chapter 6 Introduction (6/24/06) Page 6.0 CHAPTER 6 CMOS OPERATIONAL AMPLIFIERS INTRODUCTION Chapter Outline 6. CMOS Op Amps 6.2 Compensation of Op Amps 6.3 TwoStage Operational Amplifier Design 6.4 Cascode

More information

University of Toronto. Final Exam

University of Toronto. Final Exam University of Toronto Final Exam Date - Dec 16, 013 Duration:.5 hrs ECE331 Electronic Circuits Lecturer - D. Johns ANSWER QUESTIONS ON THESE SHEETS USING BACKS IF NECESSARY 1. Equation sheet is on last

More information

Homework Assignment 08

Homework Assignment 08 Homework Assignment 08 Question 1 (Short Takes) Two points each unless otherwise indicated. 1. Give one phrase/sentence that describes the primary advantage of an active load. Answer: Large effective resistance

More information

Systematic Design of Operational Amplifiers

Systematic Design of Operational Amplifiers Systematic Design of Operational Amplifiers Willy Sansen KULeuven, ESAT-MICAS Leuven, Belgium willy.sansen@esat.kuleuven.be Willy Sansen 10-05 061 Table of contents Design of Single-stage OTA Design of

More information

Lecture 050 Followers (1/11/04) Page ECE Analog Integrated Circuits and Systems II P.E. Allen

Lecture 050 Followers (1/11/04) Page ECE Analog Integrated Circuits and Systems II P.E. Allen Lecture 5 Followers (1/11/4) Page 51 LECTURE 5 FOLLOWERS (READING: GHLM 344362, AH 221226) Objective The objective of this presentation is: Show how to design stages that 1.) Provide sufficient output

More information

Final Exam. 55:041 Electronic Circuits. The University of Iowa. Fall 2013.

Final Exam. 55:041 Electronic Circuits. The University of Iowa. Fall 2013. Final Exam Name: Max: 130 Points Question 1 In the circuit shown, the op-amp is ideal, except for an input bias current I b = 1 na. Further, R F = 10K, R 1 = 100 Ω and C = 1 μf. The switch is opened at

More information

ECE-342 Test 3: Nov 30, :00-8:00, Closed Book. Name : Solution

ECE-342 Test 3: Nov 30, :00-8:00, Closed Book. Name : Solution ECE-342 Test 3: Nov 30, 2010 6:00-8:00, Closed Book Name : Solution All solutions must provide units as appropriate. Unless otherwise stated, assume T = 300 K. 1. (25 pts) Consider the amplifier shown

More information

Assignment 3 ELEC 312/Winter 12 R.Raut, Ph.D.

Assignment 3 ELEC 312/Winter 12 R.Raut, Ph.D. Page 1 of 3 ELEC 312: ELECTRONICS II : ASSIGNMENT-3 Department of Electrical and Computer Engineering Winter 2012 1. A common-emitter amplifier that can be represented by the following equivalent circuit,

More information

EE105 Fall 2014 Microelectronic Devices and Circuits. NMOS Transistor Capacitances: Saturation Region

EE105 Fall 2014 Microelectronic Devices and Circuits. NMOS Transistor Capacitances: Saturation Region EE105 Fall 014 Microelectronic Devices and Circuits Prof. Ming C. Wu wu@eecs.berkeley.edu 511 Sutardja Dai Hall (SDH) 1 NMOS Transistor Capacitances: Saturation Region Drain no longer connected to channel

More information

ENGR890 Digital VLSI Design Fall Lecture 4: CMOS Inverter (static view)

ENGR890 Digital VLSI Design Fall Lecture 4: CMOS Inverter (static view) ENGR89 Digital VLSI Design Fall 5 Lecture 4: CMOS Inverter (static view) [Adapted from Chapter 5 of Digital Integrated Circuits, 3, J. Rabaey et al.] [Also borrowed from Vijay Narayanan and Mary Jane Irwin]

More information

MICROELECTRONIC CIRCUIT DESIGN Second Edition

MICROELECTRONIC CIRCUIT DESIGN Second Edition MICROELECTRONIC CIRCUIT DESIGN Second Edition Richard C. Jaeger and Travis N. Blalock Answers to Selected Problems Updated 10/23/06 Chapter 1 1.3 1.52 years, 5.06 years 1.5 2.00 years, 6.65 years 1.8 113

More information

Microelectronic Circuit Design 4th Edition Errata - Updated 4/4/14

Microelectronic Circuit Design 4th Edition Errata - Updated 4/4/14 Chapter Text # Inside back cover: Triode region equation should not be squared! i D = K n v GS "V TN " v & DS % ( v DS $ 2 ' Page 49, first exercise, second answer: -1.35 x 10 6 cm/s Page 58, last exercise,

More information

CMPEN 411 VLSI Digital Circuits. Lecture 04: CMOS Inverter (static view)

CMPEN 411 VLSI Digital Circuits. Lecture 04: CMOS Inverter (static view) CMPEN 411 VLSI Digital Circuits Lecture 04: CMOS Inverter (static view) Kyusun Choi [Adapted from Rabaey s Digital Integrated Circuits, Second Edition, 2003 J. Rabaey, A. Chandrakasan, B. Nikolic] CMPEN

More information

EECS 141: FALL 05 MIDTERM 1

EECS 141: FALL 05 MIDTERM 1 University of California College of Engineering Department of Electrical Engineering and Computer Sciences D. Markovic TuTh 11-1:3 Thursday, October 6, 6:3-8:pm EECS 141: FALL 5 MIDTERM 1 NAME Last SOLUTION

More information

Lecture 120 Compensation of Op Amps-I (1/30/02) Page ECE Analog Integrated Circuit Design - II P.E. Allen

Lecture 120 Compensation of Op Amps-I (1/30/02) Page ECE Analog Integrated Circuit Design - II P.E. Allen Lecture 20 Compensation of Op AmpsI (/30/02) Page 20 LECTURE 20 COMPENSATION OF OP AMPS I (READING: GHLM 425434 and 624638, AH 249260) INTRODUCTION The objective of this presentation is to present the

More information

Biasing the CE Amplifier

Biasing the CE Amplifier Biasing the CE Amplifier Graphical approach: plot I C as a function of the DC base-emitter voltage (note: normally plot vs. base current, so we must return to Ebers-Moll): I C I S e V BE V th I S e V th

More information

Electronics II. Midterm II

Electronics II. Midterm II The University of Toledo f4ms_elct7.fm - Section Electronics II Midterm II Problems Points. 7. 7 3. 6 Total 0 Was the exam fair? yes no The University of Toledo f4ms_elct7.fm - Problem 7 points Given in

More information

ECE 342 Solid State Devices & Circuits 4. CMOS

ECE 342 Solid State Devices & Circuits 4. CMOS ECE 34 Solid State Devices & Circuits 4. CMOS Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jschutt@emlab.uiuc.edu ECE 34 Jose Schutt Aine 1 Digital Circuits V IH : Input

More information

Circle the one best answer for each question. Five points per question.

Circle the one best answer for each question. Five points per question. ID # NAME EE-255 EXAM 3 November 8, 2001 Instructor (circle one) Talavage Gray This exam consists of 16 multiple choice questions and one workout problem. Record all answers to the multiple choice questions

More information

Advanced Current Mirrors and Opamps

Advanced Current Mirrors and Opamps Advanced Current Mirrors and Opamps David Johns and Ken Martin (johns@eecg.toronto.edu) (martin@eecg.toronto.edu) slide 1 of 26 Wide-Swing Current Mirrors I bias I V I in out out = I in V W L bias ------------

More information

6.012 Electronic Devices and Circuits Spring 2005

6.012 Electronic Devices and Circuits Spring 2005 6.012 Electronic Devices and Circuits Spring 2005 May 16, 2005 Final Exam (200 points) -OPEN BOOK- Problem NAME RECITATION TIME 1 2 3 4 5 Total General guidelines (please read carefully before starting):

More information

Lecture 13 MOSFET as an amplifier with an introduction to MOSFET small-signal model and small-signal schematics. Lena Peterson

Lecture 13 MOSFET as an amplifier with an introduction to MOSFET small-signal model and small-signal schematics. Lena Peterson Lecture 13 MOSFET as an amplifier with an introduction to MOSFET small-signal model and small-signal schematics Lena Peterson 2015-10-13 Outline (1) Why is the CMOS inverter gain not infinite? Large-signal

More information

Lecture 12 Digital Circuits (II) MOS INVERTER CIRCUITS

Lecture 12 Digital Circuits (II) MOS INVERTER CIRCUITS Lecture 12 Digital Circuits (II) MOS INVERTER CIRCUITS Outline NMOS inverter with resistor pull-up The inverter NMOS inverter with current-source pull-up Complementary MOS (CMOS) inverter Static analysis

More information

ECE Analog Integrated Circuit Design - II P.E. Allen

ECE Analog Integrated Circuit Design - II P.E. Allen Lecture 290 Feedback Analysis using Return Ratio (3/20/02) Page 2901 LECTURE 290 FEEDBACK CIRCUIT ANALYSIS USING RETURN RATIO (READING: GHLM 599613) Objective The objective of this presentation is: 1.)

More information

Lecture 04: Single Transistor Ampliers

Lecture 04: Single Transistor Ampliers Lecture 04: Single Transistor Ampliers Analog IC Design Dr. Ryan Robucci Department of Computer Science and Electrical Engineering, UMBC Spring 2015 Dr. Ryan Robucci Lecture IV 1 / 37 Single-Transistor

More information

Lecture 14 - Digital Circuits (III) CMOS. April 1, 2003

Lecture 14 - Digital Circuits (III) CMOS. April 1, 2003 6.12 - Microelectronic Devices and Circuits - Spring 23 Lecture 14-1 Lecture 14 - Digital Circuits (III) CMOS April 1, 23 Contents: 1. Complementary MOS (CMOS) inverter: introduction 2. CMOS inverter:

More information

Lecture 13 - Digital Circuits (II) MOS Inverter Circuits. March 20, 2003

Lecture 13 - Digital Circuits (II) MOS Inverter Circuits. March 20, 2003 6.012 Microelectronic Devices and Circuits Spring 2003 Lecture 131 Lecture 13 Digital Circuits (II) MOS Inverter Circuits March 20, 2003 Contents: 1. NMOS inverter with resistor pullup (cont.) 2. NMOS

More information

1/13/12 V DS. I d V GS. C ox ( = f (V GS ,V DS ,V SB = I D. + i d + I ΔV + I ΔV BS V BS. 19 January 2012

1/13/12 V DS. I d V GS. C ox ( = f (V GS ,V DS ,V SB = I D. + i d + I ΔV + I ΔV BS V BS. 19 January 2012 /3/ 9 January 0 Study the linear model of MOS transistor around an operating point." MOS in saturation: V GS >V th and V S >V GS -V th " VGS vi - I d = I i d VS I d = µ n ( L V V γ Φ V Φ GS th0 F SB F

More information

Lecture Stage Frequency Response - I (1/10/02) Page ECE Analog Integrated Circuits and Systems II P.E.

Lecture Stage Frequency Response - I (1/10/02) Page ECE Analog Integrated Circuits and Systems II P.E. Lecture 070 Stage Frequency esponse I (/0/0) Page 070 LECTUE 070 SINGLESTAGE FEQUENCY ESPONSE I (EADING: GHLM 488504) Objective The objective of this presentation is:.) Illustrate the frequency analysis

More information

CARLETON UNIVERSITY. FINAL EXAMINATION December DURATION 3 HOURS No. of Students 130

CARLETON UNIVERSITY. FINAL EXAMINATION December DURATION 3 HOURS No. of Students 130 ALETON UNIVESITY FINAL EXAMINATION December 005 DUATION 3 HOUS No. of Students 130 Department Name & ourse Number: Electronics ELE 3509 ourse Instructor(s): Prof. John W. M. ogers and alvin Plett AUTHOIZED

More information

Chapter 13 Small-Signal Modeling and Linear Amplification

Chapter 13 Small-Signal Modeling and Linear Amplification Chapter 13 Small-Signal Modeling and Linear Amplification Microelectronic Circuit Design Richard C. Jaeger Travis N. Blalock 1/4/12 Chap 13-1 Chapter Goals Understanding of concepts related to: Transistors

More information

Homework Assignment 09

Homework Assignment 09 Homework Assignment 09 Question 1 (Short Takes) Two points each unless otherwise indicated. 1. What is the 3-dB bandwidth of the amplifier shown below if r π = 2.5K, r o = 100K, g m = 40 ms, and C L =

More information

55:041 Electronic Circuits The University of Iowa Fall Exam 2

55:041 Electronic Circuits The University of Iowa Fall Exam 2 Exam 2 Name: Score /60 Question 1 One point unless indicated otherwise. 1. An engineer measures the (step response) rise time of an amplifier as t r = 0.35 μs. Estimate the 3 db bandwidth of the amplifier.

More information

3. Basic building blocks. Analog Design for CMOS VLSI Systems Franco Maloberti

3. Basic building blocks. Analog Design for CMOS VLSI Systems Franco Maloberti Inverter with active load It is the simplest gain stage. The dc gain is given by the slope of the transfer characteristics. Small signal analysis C = C gs + C gs,ov C 2 = C gd + C gd,ov + C 3 = C db +

More information

ECE 546 Lecture 10 MOS Transistors

ECE 546 Lecture 10 MOS Transistors ECE 546 Lecture 10 MOS Transistors Spring 2018 Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jesa@illinois.edu NMOS Transistor NMOS Transistor N-Channel MOSFET Built on p-type

More information

Lecture 12 Circuits numériques (II)

Lecture 12 Circuits numériques (II) Lecture 12 Circuits numériques (II) Circuits inverseurs MOS Outline NMOS inverter with resistor pull-up The inverter NMOS inverter with current-source pull-up Complementary MOS (CMOS) inverter Static analysis

More information

DESIGN MICROELECTRONICS ELCT 703 (W17) LECTURE 3: OP-AMP CMOS CIRCUIT. Dr. Eman Azab Assistant Professor Office: C

DESIGN MICROELECTRONICS ELCT 703 (W17) LECTURE 3: OP-AMP CMOS CIRCUIT. Dr. Eman Azab Assistant Professor Office: C MICROELECTRONICS ELCT 703 (W17) LECTURE 3: OP-AMP CMOS CIRCUIT DESIGN Dr. Eman Azab Assistant Professor Office: C3.315 E-mail: eman.azab@guc.edu.eg 1 TWO STAGE CMOS OP-AMP It consists of two stages: First

More information

EECS 105: FALL 06 FINAL

EECS 105: FALL 06 FINAL University of California College of Engineering Department of Electrical Engineering and Computer Sciences Jan M. Rabaey TuTh 2-3:30 Wednesday December 13, 12:30-3:30pm EECS 105: FALL 06 FINAL NAME Last

More information

Lecture 11 VTCs and Delay. No lab today, Mon., Tues. Labs restart next week. Midterm #1 Tues. Oct. 7 th, 6:30-8:00pm in 105 Northgate

Lecture 11 VTCs and Delay. No lab today, Mon., Tues. Labs restart next week. Midterm #1 Tues. Oct. 7 th, 6:30-8:00pm in 105 Northgate EE4-Fall 2008 Digital Integrated Circuits Lecture VTCs and Delay Lecture # Announcements No lab today, Mon., Tues. Labs restart next week Midterm # Tues. Oct. 7 th, 6:30-8:00pm in 05 Northgate Exam is

More information

EEE 421 VLSI Circuits

EEE 421 VLSI Circuits EEE 421 CMOS Properties Full rail-to-rail swing high noise margins» Logic levels not dependent upon the relative device sizes transistors can be minimum size ratioless Always a path to V dd or GND in steady

More information

Lecture 5: DC & Transient Response

Lecture 5: DC & Transient Response Lecture 5: DC & Transient Response Outline q Pass Transistors q DC Response q Logic Levels and Noise Margins q Transient Response q RC Delay Models q Delay Estimation 2 Activity 1) If the width of a transistor

More information

P. R. Nelson 1 ECE418 - VLSI. Midterm Exam. Solutions

P. R. Nelson 1 ECE418 - VLSI. Midterm Exam. Solutions P. R. Nelson 1 ECE418 - VLSI Midterm Exam Solutions 1. (8 points) Draw the cross-section view for A-A. The cross-section view is as shown below.. ( points) Can you tell which of the metal1 regions is the

More information

CPE/EE 427, CPE 527 VLSI Design I L06: CMOS Inverter, CMOS Logic Gates. Course Administration. CMOS Inverter: A First Look

CPE/EE 427, CPE 527 VLSI Design I L06: CMOS Inverter, CMOS Logic Gates. Course Administration. CMOS Inverter: A First Look CPE/EE 47, CPE 57 VLSI esign I L6: CMOS Inverter, CMOS Logic Gates epartment of Electrical and Computer Engineering University of labama in Huntsville leksandar Milenkovic ( www.ece.uah.edu/~milenka )

More information

ESE570 Spring University of Pennsylvania Department of Electrical and System Engineering Digital Integrated Cicruits AND VLSI Fundamentals

ESE570 Spring University of Pennsylvania Department of Electrical and System Engineering Digital Integrated Cicruits AND VLSI Fundamentals University of Pennsylvania Department of Electrical and System Engineering Digital Integrated Cicruits AND VLSI Fundamentals ESE570, Spring 017 Final Wednesday, May 3 4 Problems with point weightings shown.

More information

The CMOS Inverter: A First Glance

The CMOS Inverter: A First Glance The CMOS Inverter: A First Glance V DD S D V in V out C L D S CMOS Inverter N Well V DD V DD PMOS 2λ PMOS Contacts In Out In Out Metal 1 NMOS Polysilicon NMOS GND CMOS Inverter: Steady State Response V

More information

MOSFET and CMOS Gate. Copy Right by Wentai Liu

MOSFET and CMOS Gate. Copy Right by Wentai Liu MOSFET and CMOS Gate CMOS Inverter DC Analysis - Voltage Transfer Curve (VTC) Find (1) (2) (3) (4) (5) (6) V OH min, V V OL min, V V IH min, V V IL min, V OHmax OLmax IHmax ILmax NM L = V ILmax V OL max

More information

ESE 570: Digital Integrated Circuits and VLSI Fundamentals

ESE 570: Digital Integrated Circuits and VLSI Fundamentals ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 10: February 15, 2018 MOS Inverter: Dynamic Characteristics Penn ESE 570 Spring 2018 Khanna Lecture Outline! Inverter Power! Dynamic Characteristics

More information

Common Drain Stage (Source Follower) Claudio Talarico, Gonzaga University

Common Drain Stage (Source Follower) Claudio Talarico, Gonzaga University Common Drain Stage (Source Follower) Claudio Talarico, Gonzaga University Common Drain Stage v gs v i - v o V DD v bs - v o R S Vv IN i v i G C gd C+C gd gb B&D v s vv OUT o + V S I B R L C L v gs - C

More information

CMOS Inverter: CPE/EE 427, CPE 527 VLSI Design I L06: CMOS Inverter, CMOS Logic Gates. Course Administration. CMOS Properties.

CMOS Inverter: CPE/EE 427, CPE 527 VLSI Design I L06: CMOS Inverter, CMOS Logic Gates. Course Administration. CMOS Properties. CMOS Inverter: Steady State Response CPE/EE 47, CPE 57 VLSI esign I L6: CMOS Inverter, CMOS Logic Gates R p V OL = V OH = V M = f(r n, R p ) epartment of Electrical and Computer Engineering University

More information

2007 Fall: Electronic Circuits 2 CHAPTER 10. Deog-Kyoon Jeong School of Electrical Engineering

2007 Fall: Electronic Circuits 2 CHAPTER 10. Deog-Kyoon Jeong School of Electrical Engineering 007 Fall: Electronic Circuits CHAPTER 10 Digital CMOS Logic Circuits Deog-Kyoon Jeong dkjeong@snu.ac.kr k School of Electrical Engineering Seoul lnational luniversity it Introduction In this chapter, we

More information

CMOS Analog Circuits

CMOS Analog Circuits CMOS Analog Circuits L6: Common Source Amplifier-1 (.8.13) B. Mazhari Dept. of EE, IIT Kanpur 19 Problem statement : Design an amplifier which has the following characteristics: + CC O in R L - CC A 100

More information

EE105 Fall 2014 Microelectronic Devices and Circuits

EE105 Fall 2014 Microelectronic Devices and Circuits EE05 Fall 204 Microelectronic Devices and Circuits Prof. Ming C. Wu wu@eecs.berkeley.edu 5 Sutardja Dai Hall (SDH) Terminal Gain and I/O Resistances of BJT Amplifiers Emitter (CE) Collector (CC) Base (CB)

More information

ESE570 Spring University of Pennsylvania Department of Electrical and System Engineering Digital Integrated Cicruits AND VLSI Fundamentals

ESE570 Spring University of Pennsylvania Department of Electrical and System Engineering Digital Integrated Cicruits AND VLSI Fundamentals University of Pennsylvania Department of Electrical and System Engineering Digital Integrated Cicruits AND VLSI Fundamentals ESE570, Spring 2016 Final Friday, May 6 5 Problems with point weightings shown.

More information

UNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences

UNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences UNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences E. Alon Final EECS 240 Monday, May 19, 2008 SPRING 2008 You should write your results on the exam

More information

Properties of CMOS Gates Snapshot

Properties of CMOS Gates Snapshot MOS logic 1 Properties of MOS Gates Snapshot High noise margins: V OH and V OL are at V DD and GND, respectively. No static power consumption: There never exists a direct path between V DD and V SS (GND)

More information

THE INVERTER. Inverter

THE INVERTER. Inverter THE INVERTER DIGITAL GATES Fundamental Parameters Functionality Reliability, Robustness Area Performance» Speed (delay)» Power Consumption» Energy Noise in Digital Integrated Circuits v(t) V DD i(t) (a)

More information

Miscellaneous Lecture topics. Mary Jane Irwin [Adapted from Rabaey s Digital Integrated Circuits, 2002, J. Rabaey et al.]

Miscellaneous Lecture topics. Mary Jane Irwin [Adapted from Rabaey s Digital Integrated Circuits, 2002, J. Rabaey et al.] Miscellaneous Lecture topics Mary Jane Irwin [dapted from Rabaey s Digital Integrated Circuits, 2002, J. Rabaey et al.] MOS Switches MOS transistors can be viewed as simple switches. In an N-Switch, the

More information

DC & Transient Responses

DC & Transient Responses ECEN454 Digital Integrated Circuit Design DC & Transient Responses ECEN 454 DC Response DC Response: vs. for a gate Ex: Inverter When = -> = When = -> = In between, depends on transistor size and current

More information

ECE-343 Test 1: Feb 10, :00-8:00pm, Closed Book. Name : SOLUTION

ECE-343 Test 1: Feb 10, :00-8:00pm, Closed Book. Name : SOLUTION ECE-343 Test : Feb 0, 00 6:00-8:00pm, Closed Book Name : SOLUTION C Depl = C J0 + V R /V o ) m C Diff = τ F g m ω T = g m C µ + C π ω T = g m I / D C GD + C or V OV GS b = τ i τ i = R i C i ω H b Z = Z

More information

CMOS INVERTER. Last Lecture. Metrics for qualifying digital circuits. »Cost» Reliability» Speed (delay)»performance

CMOS INVERTER. Last Lecture. Metrics for qualifying digital circuits. »Cost» Reliability» Speed (delay)»performance CMOS INVERTER Last Lecture Metrics for qualifying digital circuits»cost» Reliability» Speed (delay)»performance 1 Today s lecture The CMOS inverter at a glance An MOS transistor model for manual analysis

More information

EE115C Digital Electronic Circuits Homework #3

EE115C Digital Electronic Circuits Homework #3 Electrical Engineering Department Spring 1 EE115C Digital Electronic Circuits Homework #3 Due Thursday, April, 6pm @ 56-147E EIV Solution Problem 1 VTC and Inverter Analysis Figure 1a shows a standard

More information

Operational Amplifiers

Operational Amplifiers Operational Amplifiers A Linear IC circuit Operational Amplifier (op-amp) An op-amp is a high-gain amplifier that has high input impedance and low output impedance. An ideal op-amp has infinite gain and

More information

Chapter 4 Field-Effect Transistors

Chapter 4 Field-Effect Transistors Chapter 4 Field-Effect Transistors Microelectronic Circuit Design Richard C. Jaeger Travis N. Blalock 5/5/11 Chap 4-1 Chapter Goals Describe operation of MOSFETs. Define FET characteristics in operation

More information

L ECE 4211 UConn F. Jain Scaling Laws for NanoFETs Chapter 10 Logic Gate Scaling

L ECE 4211 UConn F. Jain Scaling Laws for NanoFETs Chapter 10 Logic Gate Scaling L13 04202017 ECE 4211 UConn F. Jain Scaling Laws for NanoFETs Chapter 10 Logic Gate Scaling Scaling laws: Generalized scaling (GS) p. 610 Design steps p.613 Nanotransistor issues (page 626) Degradation

More information

V = = A = ln V

V = = A = ln V Chapter Problem Solutions. a. b. c. γ + γ + BE + C + + γ + ( γ ( γ C γ + BE + BE γ BE and C γ ( γ + or C BE + C ma.5 kω.7 ( ma + 4. kω.5 kω C. (a ln C BE T S (i μ 6 A,.6 ln.588 μa C BE 4 (ii μ 6 A,.6 ln.5987

More information

The Devices. Jan M. Rabaey

The Devices. Jan M. Rabaey The Devices Jan M. Rabaey Goal of this chapter Present intuitive understanding of device operation Introduction of basic device equations Introduction of models for manual analysis Introduction of models

More information

Figure Circuit for Question 1. Figure Circuit for Question 2

Figure Circuit for Question 1. Figure Circuit for Question 2 Exercises 10.7 Exercises Multiple Choice 1. For the circuit of Figure 10.44 the time constant is A. 0.5 ms 71.43 µs 2, 000 s D. 0.2 ms 4 Ω 2 Ω 12 Ω 1 mh 12u 0 () t V Figure 10.44. Circuit for Question

More information

ECE2210 Final given: Spring 08

ECE2210 Final given: Spring 08 ECE Final given: Spring 0. Note: feel free to show answers & work right on the schematic 1. (1 pts) The ammeter, A, reads 30 ma. a) The power dissipated by R is 0.7 W, what is the value of R. Assume that

More information

Electronics II. Final Examination

Electronics II. Final Examination The University of Toledo f17fs_elct27.fm 1 Electronics II Final Examination Problems Points 1. 11 2. 14 3. 15 Total 40 Was the exam fair? yes no The University of Toledo f17fs_elct27.fm 2 Problem 1 11

More information

EE141Microelettronica. CMOS Logic

EE141Microelettronica. CMOS Logic Microelettronica CMOS Logic CMOS logic Power consumption in CMOS logic gates Where Does Power Go in CMOS? Dynamic Power Consumption Charging and Discharging Capacitors Short Circuit Currents Short Circuit

More information

GEORGIA INSTITUTE OF TECHNOLOGY School of Electrical and Computer Engineering

GEORGIA INSTITUTE OF TECHNOLOGY School of Electrical and Computer Engineering NAME: GEORGIA INSTITUTE OF TECHNOLOGY School of Electrical and Computer Engineering ECE 4430 Third Exam Closed Book and Notes Fall 2002 November 27, 2002 General Instructions: 1. Write on one side of the

More information

ECE 497 JS Lecture - 12 Device Technologies

ECE 497 JS Lecture - 12 Device Technologies ECE 497 JS Lecture - 12 Device Technologies Spring 2004 Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jose@emlab.uiuc.edu 1 NMOS Transistor 2 ρ Source channel charge density

More information

Electronics II. Final Examination

Electronics II. Final Examination f3fs_elct7.fm - The University of Toledo EECS:3400 Electronics I Section Student Name Electronics II Final Examination Problems Points.. 3 3. 5 Total 40 Was the exam fair? yes no Analog Electronics f3fs_elct7.fm

More information

P-MOS Device and CMOS Inverters

P-MOS Device and CMOS Inverters Lecture 23 P-MOS Device and CMOS Inverters A) P-MOS Device Structure and Oeration B) Relation of Current to t OX, µ V LIMIT C) CMOS Device Equations and Use D) CMOS Inverter V OUT vs. V IN E) CMOS Short

More information

4.10 The CMOS Digital Logic Inverter

4.10 The CMOS Digital Logic Inverter 11/11/2004 section 4_10 The CMOS Digital Inverter blank.doc 1/1 4.10 The CMOS Digital Logic Inverter Reading Assignment: pp. 336346 Complementary MOSFET (CMOS) is the predominant technology for constructing

More information

CE/CS Amplifier Response at High Frequencies

CE/CS Amplifier Response at High Frequencies .. CE/CS Amplifier Response at High Frequencies INEL 4202 - Manuel Toledo August 20, 2012 INEL 4202 - Manuel Toledo CE/CS High Frequency Analysis 1/ 24 Outline.1 High Frequency Models.2 Simplified Method.3

More information

Electronic Circuits Summary

Electronic Circuits Summary Electronic Circuits Summary Andreas Biri, D-ITET 6.06.4 Constants (@300K) ε 0 = 8.854 0 F m m 0 = 9. 0 3 kg k =.38 0 3 J K = 8.67 0 5 ev/k kt q = 0.059 V, q kt = 38.6, kt = 5.9 mev V Small Signal Equivalent

More information

Studio 9 Review Operational Amplifier Stability Compensation Miller Effect Phase Margin Unity Gain Frequency Slew Rate Limiting Reading: Text sec 5.

Studio 9 Review Operational Amplifier Stability Compensation Miller Effect Phase Margin Unity Gain Frequency Slew Rate Limiting Reading: Text sec 5. Studio 9 Review Operational Amplifier Stability Compensation Miller Effect Phase Margin Unity Gain Frequency Slew Rate Limiting Reading: Text sec 5.2 pp. 232-242 Two-stage op-amp Analysis Strategy Recognize

More information

5.0 CMOS Inverter. W.Kucewicz VLSICirciuit Design 1

5.0 CMOS Inverter. W.Kucewicz VLSICirciuit Design 1 5.0 CMOS Inverter W.Kucewicz VLSICirciuit Design 1 Properties Switching Threshold Dynamic Behaviour Capacitance Propagation Delay nmos/pmos Ratio Power Consumption Contents W.Kucewicz VLSICirciuit Design

More information

EE5311- Digital IC Design

EE5311- Digital IC Design EE5311- Digital IC Design Module 3 - The Inverter Janakiraman V Assistant Professor Department of Electrical Engineering Indian Institute of Technology Madras Chennai September 6, 2017 Janakiraman, IITM

More information

Lecture 5 Review Current Source Active Load Modified Large / Small Signal Models Channel Length Modulation

Lecture 5 Review Current Source Active Load Modified Large / Small Signal Models Channel Length Modulation Lecture 5 Review Current Source Active Load Modified Large / Small Signal Models Channel Length Modulation Text sec 1.2 pp. 28-32; sec 3.2 pp. 128-129 Current source Ideal goal Small signal model: Open

More information

Amplifiers, Source followers & Cascodes

Amplifiers, Source followers & Cascodes Amplifiers, Source followers & Cascodes Willy Sansen KULeuven, ESAT-MICAS Leuven, Belgium willy.sansen@esat.kuleuven.be Willy Sansen 0-05 02 Operational amplifier Differential pair v- : B v + Current mirror

More information