ECE 6412, Spring Final Exam Page 1


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1 ECE 64, Spring 005 Final Exam Page FINAL EXAMINATION SOLUTIONS (Average score = 89/00) Problem (0 points This problem is required) A comparator consists of an amplifier cascaded with a latch as shown below. The amplifier has a voltage gain of 0V/V and f 3dB = 00MHz and the latch has a time constant of 0ns. The maximum and minimum voltage swings of the amplifier and latch are V OH and V OL. When should the latch be enabled after the application of a step input to the amplifier of 0.05(V OH V OL ) to get minimum overall propagation time delay? What is the value of the minimum propagation time delay? It may useful to recall that the propagation time delay of the latch is given ast p = L ln V OH V OL v where v il is the latch il input ( V i of the text). v in = 0.05(V OH V OL ) t=0 Amplifier A v (0)=0V/V f 3dB =00MHz The solution is based on the figure shown. We note that, v oa (t) = 0[e 3dBt ]0.05(V OH V OL ). If we define the input voltage to the latch as, v il = x (V OH V OL ) then we can solve for t and t as follows: x (V OH V OL ) = 0[e 3dBt]0.05(V OH V OL ) x = 0.5[e 3dBt] This gives, t = ln 3dB x From the propagation time delay of the latch we get, t = L ln V OH V OL v = L ln il x v oa v il Comparator Enable Latch τ L =0ns v out S0E3P t p = t t = ln 3dB x L ln x dt p dx = 0 gives x = = t = 0ns ln ( ) =.59ns.9856 = 3.6ns and t = 0ns ln =.477ns t p = t t = 3.6ns.477ns = 4.637ns V OH x(v OH V OL ) V OL Amplifier t Latch t t S0E3S
2 ECE 64, Spring 005 Final Exam Page Problem (0 points This problem is required) If the foldedcascode op amp shown having a smallsignal voltage gain of 7464V/V is used as a comparator, find the dominant pole if C L = 5pF. If the input step is 0mV, determine whether the response is linear or slewing and find the propagation delay time. Assume the parameters of the NMOS transistors are K N =0V/μA, V TN = 0.7V, N =0.04V and for the PMOS transistors are K P =50V/μA, V TP = 0.7V, P =0.05V. VBias M4.5V 80μm/μm I 4 = 5μA 80μm/μm I 5 = M5 5μA v in I I M6 M7 80μm/μm 80μm/μm M M I 6 I7 36μm.3V v out μm R = I 9 kω C L M8 M9 M3 I 3 = 36μm 36μm/μm 00μA μm M0 M VBias 36μm/μm 36μm/μm.5V S0FEP V OH and V OL can be found from many approaches. The easiest is simply to assume that V OH and V OL are.5v and.5v, respectively. However, no matter what the input, the values of V OH and V OL will be in the following range, (V DD V ON )< V OH < V DD and V DD < V OH < (V SS V ON ) The reasoning is as follows, suppose V in >0. This gives I >I which gives I 6 <I 7 which gives I 9 <I 7. V out will increase until I 7 equals I 9. The only way this can happen is for M5 and M7 to leave saturation. The same reasoning holds for V in <0. Therefore assuming that V OH and V OL are.5v and.5v, respectively, we get V in (min) = 5V 7464 = 0.67mV k = 0mV 0.67mV = 4.93
3 ECE 64, Spring 005 Final Exam Page 3 Problem Continued The foldedcascode op amp as a comparator can be modeled by a single dominant pole. This pole is found as, p = R out C L where R out g m9 r ds9 r ds [g m7 r ds7 (r ds r ds5 )] g m9 = =77μS, g ds9 =g ds =75x = 3μS, g ds =50x0 6 (0.04)=μS g m7 = =775μS, g ds5 =5x = 6.5μS, g ds7 =50x0 6 (0.05)=3.75μS g m9 r ds9 r ds = (77μS) 3μS 3μS = 85.67M g m7 r ds7 (r ds r ds5 (775μS) 3.75μS μs 6.5μS = 5.05M, R out = 9.4 The dominant pole is found as, p = The time constant is = 96.9μs. R out C = L 9.4x0 6 5pF = 0,38 rps For a dominant pole system, the step response is, v out (t) = A vd (e t/ )V in The slope is the largest at t = 0. Evaluating this slope gives, dv out dt = A vd e t/ V in For t = 0, the slope is A vd V in = μs (0mV) = 0.77V/μs The slew rate of this op amp/comparator is SR = I 3 C L = 00μA 5pF = 0V/μs Therefore, the comparator does not slew and its propagation delay time is found from the linear response as, t P = ln k k = 96.9μs ln =( 96.9μs)(0.034) = 3.3μs
4 ECE 64, Spring 005 Final Exam Page 4 Problem 3 (0 points This problem is optional) An source follower, pushpull output stage is shown. Assume the parameters of the NMOS transistors are 00µA K N =0V/μA, V TN = 0.7V, N =0.04V and for the PMOS transistors are K P =50V/μA, V TP = 0.7V, P =0.05V. a.) If W /L = W /L = 0, find the W 3 /L 3 and W 4 /L 4 so that the drain current in M3 and M4 is ma when v IN = v OUT = 0. v IN b.) What is the ±peak output voltage of this amplifier? Assume the 00 A sources can have a minimum voltage across them of 0.V. c.) What is the ±slew rate of this amplifier in V/ s? R in 00µA M M V M4 V R out M3 00pF 00Ω S05FEP3 vout d.) What is the smallsignal input and output resistance of this amplifier when v IN = v OUT = 0? (Do not include the load resistance in the output resistance.) a.) With v IN = v OUT = 0, the W/L ratios of M3 and M4 are given by the current ratios. Thus, W 3 /L 3 = W 4 /L 4 = 00. b.) The current limit due to ma is ±V. Check to see if voltage limit is less. V GS4 (ma) = ma 0.7 = =.6V 0 00 V out (max) = 0..6 = 0.674V V GS3 (ma) = ma 0.7 = =.33V V out (min) = = 0.467V c.) The slew rate is ±SR = ma 00pF = 0V/ s d.) R in =. R out = g m3 g m4 g m3 = μs = 3.6mS R out = g m4 = μs = 4.69mS = 7
5 ECE 64, Spring 005 Final Exam Page 5 Problem 4 (0 points This problem is optional) The simplified schematic of a feedback amplifier V CC is shown. Use the method of feedback analysis R 3 = to find v /v, R in = v /i, and R out = v /i. 0kΩ Assume that all transistors are matched and that ß R = Q i = 00, r = 5k and r o =. 0kΩ R Q 4 = Q3 0kΩ i Openloop, quasiac model: v Smallsignal, openloop model: R = R 5 = R 6 = v kω 0kΩ kω i R = 0k v v s R = R4 = k 0k Q Q Q3 R 3 = 0k R 5 = 0k v f R 4 = 0k R 6 = k R = k i v o V EE R = i i b ßi i 0k b i b3 b r r v R v s 4 = R = r R4 = R 3 = R 5 = ßi 0k k 0k 0k 0k b3 v ßi f R = R 6 = b k k S0FEP5 i v o R i = v s = r i b (ß)(R R 4 ) = 5k (0)(k 0k ) = 0.9k a = v o = v o v s i b3 i b3 i b i b i b i b v s = (ß)[R 6 (R R 4 )] ßR 5 R 5 r (ß)[R 6 (R R 4 )] ßR 3 R 3 r R i = [(0)(954.55)](8.976)(66.67)(/0.9k ) = V/V R f = = R R 4 = and R o = v o = R i 6 (R R 4 ) r R 5 ß = 8.5 Closedloop quantities are: A vf = v o a = v s af = = 0.5, R if = (af)r i =.848M R out = R of = R o A v ß f = = R in = R R if =.858M and v R if = A v vf = 0.8 V/V R R if
6 ECE 64, Spring 005 Final Exam Page 6 Problem 5 (0 points This problem is optional) A twostage, BiCMOS op amp is shown. For the PMOS transistors, the model.5v parameters are K P =50μA/V, V TP = 0.7V and P = 0.05V 0/ 0/. For the NPN 0/ M8 M5 M7 BJTs, the model parameters are F = 00, 50μA v V CE (sat) = 0.V, V A = 5V, V t = 6mV, out v v C c = I s = 0fA and n=. (a.) Identify which 0/ 0/ 5pF input is positive and which input is M M negative. (b.) Find the numerical values of differential voltage gain, A v (0), GB (in W/L ratios in microns Hertz), the slew rate, SR, and the location Q3 Q4 of the RHP zero. (c.) Find the numerical Q6 value of the maximum and minimum input common mode voltages. S0EP.5V (a.) The plus and minus signs on the schematic show which input is positive and negative. (b.) The differential voltage gain, A v (0), is given as g m g m6 A v (0) = g ds g o4 g 6 g ds7 g o6 r ds = g m = g m = = 58. S 0 = P I D 5 A = 0.8M, r o4 = V A = 5V I C 5 A = M, g m6 = I C = 00 A V t 6mV = 3846 S r 6 = F g m6 = 6k, r ds7 = GB = g m C c SR = 50 A 5pF P I D = 0 00 A = 0.M and r o6 = V A I C = 5V 00 A = 0.5M A v (0) = [58.( )][3846(0. 0.5)]= =,659.6V/V RHP zero = g m6 C c = 58. S 5pF = 0V/ s = 3.6x0 6 rads/sec GB = 5.035MHz = 3.846mS 5pF = 769.4x0 6 rads/sec. (MHz) (c.) The maximum input common mode voltage is given as 50 v icm = V CC V DS5 (sat) V SG = = = 50 0 v icm = V v icm =.5 V BE3 V T =.5 V t ln 5 A 0fA 0.7 = =.6374V
7 ECE 64, Spring 005 Final Exam Page 7 Problem 6 (0 points This problem is optional) Find the midband voltage gain and the 3dB frequency in Hertz for the circuit shown. V in R =kω C = 0pF C =pf V R V = 00 00kΩ C 3 = 5pF The midband voltage gain can be expressed as, V out = V out V V = (0) R V in V V V in R 000 V R V 3 = 00 kω () = 9.9V/V C 4 = 0pF Finding the opencircuit, time constants: R CO : R CO = R = k R CO C = 0ns R CO : v t = R i t R i t V 00 V 00 But v t = V V and V = R i t, v t = R i t R i t R R i t 00 R v t 00 R CO = v t i t = R R 0.0R R 0.0R S05FEP6 = k 00k 000k =.099k R 000 CO C =.ns R C3O : R C3O = R 00 = 99.9 R C3O C 3 = 0.5ns R C4O : R C4O = R 3 = k R C4O C 4 = 0ns T oc = (0.0.50)ns =.6ns 3dB T oc = 44.5x0 6 f 3dB = 7.04 MHz i t v t R V V 000 i t R Vout V 000 V S05ES3
8 ECE 64, Spring 005 Final Exam Page 8 Problem 7 (0 points This problem is optional) Find an expression for the.5v equivalent input noise voltage of the circuit in the previous M9 problem, e eq, in terms of M8 M6 M7 the small signal model v v parameters and the individual 00μA M M equivalent input noise voltages, e ni, of each of the transistors (i = through 7). M0 M5 M3 Assume M and M, M3 and M4, and M6 and M7 are matched. Equivalent noise circuit: M4 S04FEP3 v out e n6 V DD * e n M6 * e n7 M7 v * M M * e n v e n3 e n4 v out M3 * * M4 V SS S99FES6 e out = (g m e n g m e n g m3 e n3 g m4 e n4 g m6 e n6 g m7 e n7 )R out e eq = e out (g m R out ) = e n e n g m3 g ( e n3 e n4 ) m g m6 g ( e n6 e n7 ) m If M through M are matched then g m = g m and we get g m3 g m6 e eq = e n g e n3 m3 g e m n6
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