EE 330 Lecture 16. MOS Device Modeling p-channel n-channel comparisons Model consistency and relationships CMOS Process Flow

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1 EE 330 Lecture 16 MOS Device Modeling p-channel n-channel comparisons Model consistency and relationships CMOS Process Flow

2 Review from Last Time Operation Regions by Applications Id I D Triode Region Saturation Region Analog Circuits Cutoff Region Vds Digital Circuits V DS Most analog circuits operate in the saturation region (basic VVR operates in triode and is an exception) Most digital circuits operate in triode and cutoff regions and switch between these two with Boolean inputs

3 Review from Last Time Output Impedance Model in Saturation Region I D 300 Analog Circuits Id In saturation region W I=μC V V 2L Vds 2 ( ) [ 1+λV ] D OX GS T DS W W I=μC V V μc V V 2L 2L ( ) + λ ( ) 2 2 V DS V D OX GS T OX GS T DS W 1 I =μc ( V V ) 2 + V 2L R DEQ D OX GS T DS 1 R = DEQ W λμc V V 2L ( ) OX GS T 2

4 Review from Last Time Model Status Simple dc Model Square-Law Model Small Signal Better Analytical dc Model Sophisticated Model for Computer Simulations BSIM Model Square-Law Model (with extensions for λ,γ effects) Short-Channel α-law Model Frequency Dependent Small Signal Simpler dc Model Switch-Level Models Ideal switches R SW and C GS

5 Review from Last Time In the next few slides, the models we have developed will be listed and reviewed Square-law Model Switch-level Models Extended Square-law model Short-channel model BSIM Model BSIM Binning Model Corner Models

6 Review from Last Time Square-Law Model I D V GS4 V GS3 V DS V GS2 V GS1 0 V V GS T W V = < L 2 W ( ) 2L DS I μc V V V V V V V V D OX GS T DS GS T DS GS T 2 μc V V V V V V V OX GS T GS T DS GS T Model Parameters : {μ,c OX,V T0 } Design Parameters : {W,L} but only one degree of freedom W/L

7 Review from Last Time Switch-Level Models Drain Gate G D Source R SW C GS V GS Switch closed for V GS = 1 S Switch-level model including gate capacitance and drain resistance C GS and R SW dependent upon device sizes and process For minimum-sized devices in a 0.5u process 2KΩ n channel C GS 1.5fF R sw 6KΩ p channel Considerable emphasis will be placed upon device sizing to manage C GS and R SW Model Parameters : {C GS,R SW }

8 Review from Last Time Extended Square-Law Model I I G B = 0 = 0 0 V V GS T W V = < L 2 W 2 μc ( V V ) ( 1+ λv ) V V V V V 2L DS I μc V V V V V V V V D OX GS T DS GS T DS GS T V T OX GS T DS GS T DS GS T ( φ V φ ) = VT0 + γ BS Model Parameters : {μ,c OX,V T0,φ,γ,λ} Design Parameters : {W,L} but only one degree of freedom W/L

9 Review from Last Time Short-Channel Model 0 V V GS T θ W I = D μc V V V V V V < V OX GS T DS GS T DS 1 GS θ L 1 W θμc V V V V V V 2 OX GS T GS T DS 1 GS L α ( ) θ ( V ) α α ( ) θ ( V ) T T α 2 α is the velocity saturation index, 2 α 1 Channel length modulation (λ) and bulk effects can be added to the velocity Saturation as well

10 Review from Last Time BSIM model Note this model has 95 model parameters!

11 Review from Last Time BSIM Binning Model - Bin on device sizes - multiple BSIM models! With 32 bins, this model has 3040 model parameters!

12 Review from Last Time BSIM Corner Models - Often 4 corners in addition to nominal TT, FF, FS, SF, and SS - five different BSIM models! TT: typical-typical FF: fast n, fast p FS: fast n, slow p SF: slow n, fast p SS: slow n, slow p With 4 corners, this model has 475 model parameters!

13 Review from Last Time Hierarchical Model Comparisons Accuracy Complexity BSIM Binning Models Analytical Numerical (for simulation only) L Number of Model Parameters BSIM Models Number of Model Parameters Square-Law Models Number of Model Parameters Switch-Level Models Approx 3000 (for 30 bins) Approx to 6 W Number of Model Parameters 0 to 2

14 Review from Last Time Corner Models Basic Model { FF (Fast n, Fast p) FS (Fast n, Slow p) TT Typical-Typical SF (Slow n, Fast p) SS (Slow n, Slow p) Corner Model Applicable at any level in model hierarchy (same model, different parameters) Often 4 corners (FF, FS, SF, SS) used but sometimes many more Designers must provide enough robustness so good yield at all corners

15 n-channel. p-channel modeling Source Gate Drain Bulk I D 3 V GS4 2.5 D n-channel MOSFET D V GS3 V GS2 G S G D S VDS GS4 GS3 GS2 GS1 V GS1 V > V > V > V > 0 V DS G I G G V GS I D B S D S I B B V BS V DS 0 V V GS Tn W V = < L 2 W ( ) 2L I =I =0 DS I μc V V V V V V V V D n OX GS Tn DS GS Tn DS GS Tn G B (for enhancement devices) 2 μ C V V V V V V V n OX GS Tn GS Tn DS GS Tn Positive V DS and V GS cause a positive I D

16 Bulk Source n-channel. p-channel modeling Gate Drain (for enhancement devices) p-channel MOSFET S S G G D D D G B 0 V V GS Tp S W VDS I = -μc V V V V V V > V V S L 2 V GS W 2 G B V BS -μ C p OX ( V V GS Tp ) V V V V V GS Tp DS GS Tp V I DS 2L G I B I =I =0 G B I D D D p OX GS Tp DS GS Tp DS GS Tp Negative V DS and V GS cause a negative I D Functional form of models are the same, just sign differences and some parameter differences (usually mobility is the most important)

17 n-channel. p-channel modeling Bulk Source Gate Drain V GS G I G I D S B D I B V BS V DS p-channel MOSFET (for enhancement devices) 0 V V GS Tp W V L 2 W ( ) 2L I =I =0 DS I = -μc V V V V V V > V V D p OX GS Tp DS GS Tp DS GS Tp G B 2 -μ C V V V V V V V p OX GS Tp GS Tp DS GS Tp Alternate equivalent representation 0 V V GS Tp W V L 2 W ( ) 2L I =I =0 G B These look like those for the n-channel device but with DS I = μc V V V V V V < V V D p OX GS Tp DS GS Tp DS GS Tp 2 μ C V V V V V V V p OX GS Tp GS Tp DS GS Tp

18 D n-channel. p-channel modeling D S S G G G G S D S D D D G B G B S S G I G V GS I D D S I B B V BS V DS V GS G I G I D S B D I B V BS V DS I D V GS4 V GS3 Models essentially the same with different signs and model parameters 1 V GS V GS V DS VDS VGS4 > VGS3 > VGS2 > V GS1> 0 0 V V GS Tn W V = < L 2 W 2 μ C ( V V ) V V V V V 2L I =I =0 DS I μc V V V V V V V V D n OX GS Tn DS GS Tn DS GS Tn G B n OX GS Tn GS Tn DS GS Tn 0 V V GS Tp W V L 2 W ( ) 2L I =I =0 DS I = -μc V V V V V V > V V D p OX GS Tp DS GS Tp DS GS Tp G B 2 -μ C p OX VGS VTp VGS VTp VDS VGS VTp

19 Model Relationships Determine R SW and C GS for an n-channel MOSFET from square-law model In the 0.5u CMOS process if L=1u, W=1u (Assume μc OX =100μAV -2, C OX =2.5fFu -2,V T0 =1V, V DD =3.5V, V SS =0) 0 V V GS T W V = < L 2 W ( ) 2L DS I μc V V V V V V V V D OX GS T DS GS T DS GS T 2 μc V V V V V V V OX GS T GS T DS GS T when SW is on, operation is deep triode

20 Model Relationships This image cannot currently be displayed. Determine R SW and C GS for an n-channel MOSFET from square-law model In the 0.5u CMOS process if L=1u, W=1u (Assume μc OX =100μAV -2, C OX =2.5fFu -2,V T0 =1V, V DD =3.5V, V SS =0) W V W L 2 L ( ) DS I = μc V V V μc V V V D OX GS T DS OX GS T DS V 1 1 DS R = = = = 4KΩ SQ I W 1 D V GS =VDD μc ( V V ) ( E 4) ( OX GS T ) L V GS =3.5V 1 C GS = C OX WL = (2.5fFµ -2 )(1µ 2 ) = 2.5fF

21 Model Relationships Determine R SW and C GS for an p-channel MOSFET from square-law model In the 0.5u CMOS process if L=1u, W=1u ( C OX =2.5fFu -2,V T0 =1V, V DD =3.5V, V SS =0) Observe µ n \ µ p 3 0 V V GS T W V = < L 2 W ( ) 2L DS I μc V V V V V V V V D OX GS T DS GS T DS GS T 2 μc V V V V V V V OX GS T GS T DS GS T When SW is on, operation is deep triode

22 Model Relationships Determine R SW and C GS for an p-channel MOSFET from square-law model In the 0.5u CMOS process if L=1u, W=1u ( C OX =2.5fFu -2,V T0 =1V, V DD =3.5V, V SS =0) Observe µ n \ µ p 3 0 V V GS T W V = < L 2 W ( ) 2L DS I μc V V V V V V V V D OX GS T DS GS T DS GS T 2 μc V V V V V V V OX GS T GS T DS GS T When SW is on, operation is deep triode

23 Model Relationships Determine R This image cannot currently be displayed. SW and C GS for an p-channel MOSFET from square-law model In the 0.5u CMOS process if L=1u, W=1u Observe µ n \ µ p 3 ( C OX =2.5fFu -2,V T0 =1V, V DD =3.5V, V SS =0) W V W DS I = μc V V V μc ( V V ) V L 2 L D p OX GS T DS p OX GS T DS V 1 1 DS R = = = = 12KΩ SQ I W 1 1 D V GS =VDD μc ( V V ) ( E 4) ( p OX GS T ) L V GS =3.5V 3 1 C GS = C OX WL = (2.5fFµ -2 )(1µ 2 ) = 2.5fF Observe the resistance of the p-channel device is approximately 3 times larger than that of the n-channel device for same bias and dimensions!

24 Modeling of the MOSFET Goal: Obtain a mathematical relationship between the port variables of a device. I = f ( V,V,V ) I I D G B 1 = f = f 2 3 GS DS BS ( VGS,VDS,VBS ) ( V ) GS,VDS,VBS Gate Drain I D I D I B V DS Bulk Simple dc Model V GS V BS Small Signal Better Analytical dc Model Sophisticated Model for Computer Simulations Frequency Dependent Small Signal Simpler dc Model

25 Small-Signal Model Goal with small signal model is to predict performance of circuit or device in the vicinity of an operating point Operating point is often termed Q-point

26 Small-Signal Model y Y Q Q-point X Q x Analytical expressions for small signal model will be developed later

27 Design Rules Technology Files Process Flow (Fabrication Technology) Model Parameters

28 n-well n-well n- p-

29

30

31 Bulk CMOS Process Description n-well process Single Metal Only Depicted Double Poly

32 Components Shown n-channel MOSFET p-channel MOSFET Poly Resistor Doubly Poly Capacitor

33 C D A A B B C D

34 Consider Basic Components Only Well Contacts and Guard Rings Will be Discussed Later

35 A A B B

36 A A B B

37 Metal details hidden to reduce clutter A A D G S B D B S B n-channel MOSFET G

38 A A D G S B B B W L

39 A A Capacitor Resistor p-channel MOSFET B B n-channel MOSFET

40 n-well n-well n- p-

41 N-well Mask A A B B

42 N-well Mask A A B B

43 Detailed Description of First Photolithographic Steps Only Top View Cross-Section View

44 ~ Blank Wafer Implant n-well Photoresist Mask A A p-doped Substrate B Develop Expose B

45 Develop N-well Exposure Photoresist Mask A-A Section B-B Section

46 Implant A-A Section B-B Section

47 N-well Mask A-A Section B-B Section

48 n-well n-well n- p-

49 Active Mask A A B B

50 Active Mask A A B B

51 Active Mask Field Oxide A-A Section Field Oxide Field Oxide Field Oxide B-B Section

52 n-well n-well n- p-

53 Poly1 Mask A A B B

54 Poly1 Mask A A B B

55 Poly plays a key role in all four types of devices! A A Capacitor Resistor P-channel MOSFET B B n-channel MOSFET

56 Poly 1 Mask A-A Section Gate Oxide Gate Oxide B-B Section

57 n-well n-well n- p-

58

59 Poly 2 Mask A A B B

60 Poly 2 Mask A A B B

61 Poly 2 Mask A-A Section B-B Section

62 n-well n-well n- p-

63

64 P-Select A A B B

65 P-Select A A B B

66 P-Select Mask p-diffusion p-diffusion A-A Section Note the gate is self aligned!! B-B Section

67 P-Select Mask n-diffusion A-A Section n-diffusion B-B Section

68 n-well n-well n- p-

69

70

71 Contact Mask A A B B

72 Contact Mask A A B B

73 Contact Mask A-A Section B-B Section

74 n-well n-well n- p-

75

76

77 Metal 1 Mask A A B B

78 Metal 1 Mask A A B B

79 Metal Mask A-A Section B-B Section

80 A A B B

81 A A Capacitor Resistor P-channel MOSFET B B n-channel MOSFET

82 End of Lecture 16

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