The Devices. Devices

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1 The

2 The MOS Transistor Gate Oxyde Gate Source n+ Polysilicon Drain n+ Field-Oxyde (SiO 2 ) p-substrate p+ stopper Bulk Contact CROSS-SECTION of NMOS Transistor

3 Cross-Section of CMOS Technology

4 MOS transistors - types and symbols D D D D G G G G B S NMOS Enhancement S S NMOS PMOS Depletion Enhancement S

5 Threshold Voltage: Concept S - V GS + G D n+ n+ n-channel p-substrate Depletion Region B

6 The Threshold Voltage Q B V = φ 2φ T ms F C ox Q SS C ox Q I C ox Workfunction Difference Implants Surface Charge Depletion LayerCharge Body Effect Coefficient V = V + γ T T0 2φ + V F SB 2φ F with Q B0 V = φ 2φ T0 ms F C ox Q SS C ox Q I C ox and γ = 2qε N si A C ox

7 Current-Voltage Relations Linear Region: V DS V GS - V T I D = V 2 W k' ---- DS n L V V V GS T DS 2 with µ ε n ox k' = µ C = n n ox t ox Process Transconductance Parameter Saturation Mode: V DS V GS - V T Channel Length Modulation I D = k' n W L V V λvds GS T

8 Transistor in Saturation V GS G V DS > V GS - V T S D n+ - V GS - V T + n+

9 I-V Relations V DS = V GS -V T V GS = 5V I D (ma) 2 1 Triode Saturation V GS = 4V V GS = 3V Square Dependence I D Subthreshold Current V GS = 2V V GS = 1V V DS (V) (a) I D as a function of V DS 0.0 V T V GS (V) (b) I D as a function of V GS (for V DS = 5V). NMOS Enhancement Transistor: W = 100 µm, L = 20 µm

10 The Sub-Micron MOS Transistor Threshold Variations Parasitic Resistances Velocity Sauturation and Mobility Degradation Subthreshold Conduction Latchup

11 Parasitic Resistances G Polysilicon gate L D Drain contact V GS,eff S D W R S R D Drain

12 Velocity Saturation (1) υ n (cm/sec) υ sat = 10 7 constant velocity Constant mobility (slope = µ) µ n (cm 2 /Vs) µ n0 E sat = 1.5 E (V/µm) 0 E t (V/µm) 100 (a) Velocity saturation (b) Mobility degradation

13 Velocity Satruration (2) V GS = 5 I D (ma) V GS = 4 V GS = 3 V GS = 2 Linear Dependence I D (ma) V GS = V DS (V) (a) I D as a function of V DS V GS (V) (b) I D as a function of V GS (for V DS = 5 V). Linear Dependence on V GS

14 Sub-threshold Conduction Linear region ln(i D ) (A) Subthreshold exponential region V T V GS (V)

15 Latchup V DD V DD p + n + n + p + p + n + R nwell p-source n-well R nwell R psubs p-substrate n-source R psubs (a) Origin of latchup (b) Equivalent circuit

16 SPICE MODELS Level 1: Long Channel Equations - Very Simple Level 2: Physical Model - Includes Velocity Saturation and Threshold Variations Level 3: Semi-Emperical - Based on curve fitting to measured devices Level 4 (BSIM): Emperical - Simple and Popular

17 MAIN MOS SPICE PARAMETERS Parameter Name Symbol SPICE Name Units Default Value SPICE Model Index LEVEL - 1 Zero-Bias Threshold Voltage VT0 VT0 V 0 Process Transconductance k KP A/V2 2.E-5 Body-Bias Parameter g GAMMA V0.5 0 Channel Modulation l LAMBDA 1/V 0 Oxide Thickness tox TOX m 1.0E-7 Lateral Diffusion xd LD m 0 Metallurgical Junction Depth xj XJ m 0 Surface Inversion Potential 2 ff PHI V 0.6 Substrate Doping NA,ND NSUB cm-3 0 Surface State Density Qss/q NSS cm-3 0 Fast Surface State Density NFS cm-3 0 Total Channel Charge Coefficient NEFF - 1 Type of Gate Material TPG - 1 Surface Mobility m0 U0 cm2/v-sec 600 Maximum Drift Velocity umax VMAX m/s 0 Mobility Critical Field xcrit UCRIT V/cm 1.0E4 Critical Field Exponent in Mobility Degradation UEXP - 0 Transverse Field Exponent (mobility) UTRA - 0

18 SPICE Parameters for Parasitics Parameter Name Symbol SPICE Name Units Default Value Source resistance R S RS Ω 0 Drain resistance R D RD Ω 0 Sheet resistance (Source/Drain) R RSH Ω/ 0 Zero Bias Bulk Junction Cap C j0 CJ F/m 2 0 Bulk Junction Grading Coeff. m MJ Zero Bias Side Wall Junction Cap C jsw0 CJSW F/m 0 Side Wall Grading Coeff. m sw MJSW Gate-Bulk Overlap Capacitance C gbo CGBO F/m 0 Gate-Source Overlap Capacitance C gso CGSO F/m 0 Gate-Drain Overlap Capacitance C gdo CGDO F/m 0 Bulk Junction Leakage Current I S IS A 0 Bulk Junction Leakage Current J S JS A/m 2 1E-8 Density Bulk Junction Potential φ 0 PB V 0.8

19 SPICE Transistor Parameters Parameter Name Symbol SPICE Name Units Default Value Drawn Length L L m - Effective Width W W m - Source Area AREA AS m2 0 Drain Area AREA AD m2 0 Source Perimeter PERIM PS m 0 Drain Perimeter PERIM PD m 0 Squares of Source Diffusion NRS - 1 Squares of Drain Diffusion NRD - 1

20 Matching Manual and SPICE Models I D Region of Matching Short Channel I-V Curve V GS = 5V Long Channel Approximation V DS = 5V V DS

21 Dynamic Behavior of MOS Transistor G C GS C GD S D C SB C GB C DB B

22 The Gate Capacitance Polysilicon gate (a) Top view. Source Drain W n + n + x d x d L Gate-bulk overlap Gate oxide t ox (b) Cross-section. n + L eff n + C gate = ε ox WL t ox

23 Diffusion Capacitance Channel-stop implant N A + Side wall W Source N D Bottom x j L S Side wall Substrate N A Channel

24 Junction Capacitance abrupt junction C j (ff) linear junction C j V D (V) C j = C j V φ m D 0

25 Technology Evolution. Year of Introduction Channel length (µm) Gate oxide (nm) V DD (V) V T (V) NMOS I Dsat (ma/µm) V GS = V DD ) PMOS I Dsat (ma/µm) V GS = V DD )

26 The Diode

27 Depletion Region hole diffusion electron diffusion p n (a) Current flow. hole drift electron drift Charge Density - ρ + x Distance (b) Charge density. Electrical Field ξ x (c) Electric field. Potential V ψ 0 -W 1 W 2 x (d) Electrostatic potential.

28 Diode Current I D (ma) I D (V) V D (V) (a) On a linear scale V D (V) (b) On a logarithmic scale (forward bias). I D = I e V D φ T S 1

29 Forward Bias p n (W 2 ) p n0 L p n p0 p-region -W 1 0 W 2 n-region x diffusion

30 Reverse Bias p n0 n p0 p-region -W 1 0 W 2 n-region x diffusion

31 Junction Capacitance abrupt junction C j (ff) linear junction C j V D (V)

32 Diode Switching Time V D t 1 20 t 2 time (nsec) 30

33 Diode Model R S + V D - I D C D

34 SPICE Parameters Parameter Name Symbol SPICE Name Units Default Value Saturation current I S IS A 1.0 E-14 Emission coefficient n N - 1 Series resistance R S RS Ω 0 Transit time τ T TT sec 0 Zero-bias junction C j0 CJ0 F 0 capacitance Grading coefficient m M Junction potential φ 0 VJ V 1 First Order SPICE diode model parameters.

35 Bipolar Transistor E B C p + isolation n + p + p n-epitaxy n + p + n + buried layer p-substrate (a) Cross-sectional view. B E n + p n C (b) Idealized transistor structure.

36 Forward Active Operation Carrier Concentration Depletion Regions E B C n b (0) p c0 p e0 n b0 x 0 W W B

37 Current Components E B C I E 1 I C 2 3 x I B electrons holes

38 Reverse Active Carrier Concentration E B C n b (W) p e0 n b (0) n b0 0 W p c0 x W B

39 Saturation Mode Carrier Concentration n b (0) E B C Q A n b (W) p e0 QS n b0 0 W p c0 x W B

40 Cutoff Carrier Concentration E B C p e0 nb (0) n b0 n b (W) 0 W p c0 x W B

41 Early Voltage I C Saturation Forward Active V BE3 V BE2 V BE1 V A V CE

42 Parasitic Resistances E B C p + r E n + p p + n + isolation n-epitaxy r C3 r B r C1 p + n + buried layer r C2 p-substrate

43 Beta Variations ln (I) I KF I C High Level Injection β F Recombination I B V BE (linear)

44 Bipolar Transistor Operation I C (ma) I B =25 µa I B =50 µa I B =75 µa I B =100 µa Reverse Operation I C (ma) Forward Operation Active I B =100 µa I B =75 µa I B =50 µa I B =25 µa V CE (V) Saturation V CE (V)

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