ECE 546 Lecture 10 MOS Transistors


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1 ECE 546 Lecture 10 MOS Transistors Spring 2018 Jose E. SchuttAine Electrical & Computer Engineering University of Illinois
2 NMOS Transistor NMOS Transistor NChannel MOSFET Built on ptype substrate MOS devices are smaller than BJTs MOS devices consume less power than BJTs 2
3 NMOS Transistor  Layout Top View Cross Section 3
4 MOS Regions of Operation Resistive Triode V V GS DS V T small Nonlinear V GS V T V < ( V V ) DS GS T Active Saturation V GS V T V V V DS GS T 4
5 MOS Transistor Operation As V G increases from zero Holes in the p substrate are repelled from the gate area leaving negative ions behind A depletion region is created No current flows since no carriers are available As V G increases The width of the depletion region and the potential at the oxidesilicon interface also increase When the interface potential reaches a sufficiently positive value, electrons flow in the channel. The transistor is turned on As V G rises further The charge in the depletion region remains relatively constant The channel current continues to increase 5
6 MOS Triode Region  1 W ID Cox VGS VT VDS L V V V DS GS T C ox t ox ox 3.9 o t ox C ox : gate oxide capacitance : electron mobility L: channel length W: channel width V T : threshold voltage 6
7 MOS Triode Region FET is like a linear resistor with r ds 1 C W V L V n ox GS T 7
8 MOS Triode Region  2 V GS V T V V V DS GS T Charge distribution is nonuniform across channel Less charge induced in proximity of drain W 1 I C V V V V L 2 2 D n ox GS T DS DS 8
9 MOS Active Region V V V V Saturation occurs at pinch off when DS GS T DSP V GS V T V V V DS GS T (saturation) W I C V V 2L 2 D n ox GS T 9
10 MOS Threshold Voltage The value of V G for which the channel is inverted is called the threshold voltage V T (or V t ). Characteristics of the threshold voltage Depends on equilibrium potential Controlled by inversion in channel Adjusted by implantation of dopants into the channel Can be positive or negative Influenced by the body effect 10
11 MOS Active Region Saturation Channel is pinched off Increase in V DS has little effect on i D Squarelaw behavior wrt (V GS V T ) Acts like a current source 11
12 Body Effect The body effect V T varies with bias between source and body Leads to modulation of V T Potential on substrate affects threshold voltage V ( ) T VSB VTo 2F VSB 2F 1/2 1/2 F kt N a ln q ni Fermi potential of material 2qN 1/2 a C ox s Body bias coefficient 12
13 ChannelLength Modulation With depletion layer widening, the channel length is in effect reduced from L to LL Channellength modulation This leads to the following IV relationship 1 i k W v V v 2 L ' 2 D n GS T 1 DS Where is a process technology parameter 13
14 ChannelLength Modulation Channellength modulation causes i D to increase with v DS in saturation region 14
15 Gate Capacitance V 0 V 0, V small GT GT DS Capacitance Depends on bias Fringing fields are present Account for overlap C V GT 0, V large DS 15
16 Capacitance Gate Capacitance C G determines the amount of charge to switch gate Several distributed components Large discontinuity as device turns on At saturation capacitance is entirely between gate and source Define VDS X V V GS T 2 1 X Cgs Cgso WLCox X 2 1 Cgd Cgdo WLCox X
17 MOS Capacitances Expect capacitance between every two of the four terminals. 17
18 PMOS Transistor 0 PMOS VGS= VGS=1.0 VGS=1.5 VGS=2.0 VGS= All polarities are reversed from nmos  v GS, v DS and V t are negative  Current i D enters source and leaves through drain  Hole mobility is lower low transconductance  nmos favored over pmos Vds 18
19 Complementary MOS CMOS Characteristics Combine nmos and pmos transistors pmos size is larger for electrical symmetry 19
20 CMOS Advantages Virtually, no DC power consumed No DC path between power and ground Excellent noise margins (V OL =0, V OH =V DD ) Inverter has sharp transfer curve Drawbacks Requires more transistors Process is more complicated pmos size larger to achieve electrical symmetry Latch up 20
21 Voltage Transfer Characteristics (VTC) The static operation of a logic circuit is determined by its VTC In low state: noise margin is NM L NM V V L IL OL In high state: noise margin is NM H NM V V H OH IH An ideal VTC will maximize noise margins NM L NM H V IL and V IH are the points where the slope of the VTC=1 Optimum: NM NM V L H DD /2 21
22 Switching Time & Propagation Delay input output 22
23 Switching Time & Propagation Delay t r =rise time (from 10% to 90%) t f =fall time (from 90% to 10%) t plh =lowtohigh propagation delay t phl =hightolow propagation delay Inverter propagation delay: t p tplh tphl
24 NMOS Switch 24
25 CMOS Switch CMOS switch is called an inverter The body of each device is connected to its source NO BODY EFFECT 25
26 CMOS Switch Input Low GSN NMOS V V OFF TN r dsn high r dsp PMOS 1 k W V V ' p DD TP L p r dsp is low 26
27 r dsn CMOS Switch Input High NMOS 1 W k V V r dsn is low ' n DD TN L n GSP PMOS V V OFF TP r dsp high 27
28 CMOS Inverter r dsn 1 k W V V ' N DD T L n r dsp 1 k W V V ' P DD T L p Short switching transient current low power 28
29 CMOS Inverter Advantages of CMOS inverter Output voltage levels are 0 and V DD signal swing is maximum possible Static power dissipation is zero Low resistance paths to V DD and ground when needed High output driving capability increased speed Input resistance is infinite high fanout Load driving capability of CMOS is high. Transistors can sink or source large load currents that can be used to charge and discharge load capacitances. 29
30 Matched CMOS Inverter VTC CMOS inverter can be made to switch at specific threshold voltage by appropriately sizing the transistors W n W L L p p Symmetrical transfer characteristics is obtained via matching equal current driving capabilities in both directions (pullup and pulldown) n 30
31 CMOS Dynamic Operation Exact analysis is too tedious Replace all the capacitances in the circuit by a single equivalent capacitance C connected between the output node of the inverter and ground Analyze capacitively loaded inverter to determine propagation delay 31
32 CMOS Dynamic Operation 1 t t t 2 P PHL PLH Components can be equalized by matching transistors t P is proportional to C reduce capacitance Larger V DD means lower t p Conflicting requirements exist 32
33 CMOS Dynamic Power Dissipation In every cycle Q N dissipate ½ CV DD2 of energy Q P dissipate ½ CV DD2 of energy Total energy dissipation is CV DD 2 If inverter is switched at f cycles per second, dynamic 2 power dissipation is: P D fcv DD 33
34 De Morgan s Law Digital Logic  Generalization ABC... ABC... ABC... ABC... Distributive Law AB AC BC BD A( B C) B( C D) General Procedure 1. Design PDN to satisfy logic function 2. Construct PUN to be complementary of PDN in every way 3. Optimize using distributive rule 34
35 PullDown and PullUp PDNparallel NMOS PUNseries PMOS Truth Tables YDP AB YUS AB 35
36 TwoInput NOR Gate Y AB AB 36
37 PullDown and PullUp PDNSeries NMOS PUNParallel PMOS YDS AB Truth Tables Y A B UP 37
38 TwoInput NAND Gate Y AB AB 38
39 CMOS Logic Gate Circuits Two Networks Pulldown network (PDN) with NMOS Pullup network (PUN) with PMOS PUN conducts when inputs are low and consists of PMOS transistors PDN consists of NMOS transistors and is active when inputs are high PDN and PUN utilize devices In parallel to form OR functions In series to form AND functions 39
40 Basic Logic Function Basic Function INVERTER NOR NAND Symbol # Devices PUN 1 PMOS 2 PMOSSeries 2 PMOSParallel # Devices PDN 1 NMOS 2 NMOSParallel 2 NMOSSeries Truth Table 40
41 pull down Example Implement the function Y AB C pull up Y ABC ABC ( AB) C 41
42 ExclusiveOR (XOR) Function Y AB AB Y ( AB)( AB) XOR pull down A B Y pull up 42
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