ECE 546 Lecture 10 MOS Transistors

Save this PDF as:
 WORD  PNG  TXT  JPG

Size: px
Start display at page:

Download "ECE 546 Lecture 10 MOS Transistors"

Transcription

1 ECE 546 Lecture 10 MOS Transistors Spring 2018 Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois

2 NMOS Transistor NMOS Transistor N-Channel MOSFET Built on p-type substrate MOS devices are smaller than BJTs MOS devices consume less power than BJTs 2

3 NMOS Transistor - Layout Top View Cross Section 3

4 MOS Regions of Operation Resistive Triode V V GS DS V T small Nonlinear V GS V T V < ( V V ) DS GS T Active Saturation V GS V T V V V DS GS T 4

5 MOS Transistor Operation As V G increases from zero Holes in the p substrate are repelled from the gate area leaving negative ions behind A depletion region is created No current flows since no carriers are available As V G increases The width of the depletion region and the potential at the oxide-silicon interface also increase When the interface potential reaches a sufficiently positive value, electrons flow in the channel. The transistor is turned on As V G rises further The charge in the depletion region remains relatively constant The channel current continues to increase 5

6 MOS Triode Region - 1 W ID Cox VGS VT VDS L V V V DS GS T C ox t ox ox 3.9 o t ox C ox : gate oxide capacitance : electron mobility L: channel length W: channel width V T : threshold voltage 6

7 MOS Triode Region FET is like a linear resistor with r ds 1 C W V L V n ox GS T 7

8 MOS Triode Region - 2 V GS V T V V V DS GS T Charge distribution is nonuniform across channel Less charge induced in proximity of drain W 1 I C V V V V L 2 2 D n ox GS T DS DS 8

9 MOS Active Region V V V V Saturation occurs at pinch off when DS GS T DSP V GS V T V V V DS GS T (saturation) W I C V V 2L 2 D n ox GS T 9

10 MOS Threshold Voltage The value of V G for which the channel is inverted is called the threshold voltage V T (or V t ). Characteristics of the threshold voltage Depends on equilibrium potential Controlled by inversion in channel Adjusted by implantation of dopants into the channel Can be positive or negative Influenced by the body effect 10

11 MOS Active Region Saturation Channel is pinched off Increase in V DS has little effect on i D Square-law behavior wrt (V GS -V T ) Acts like a current source 11

12 Body Effect The body effect V T varies with bias between source and body Leads to modulation of V T Potential on substrate affects threshold voltage V ( ) T VSB VTo 2F VSB 2F 1/2 1/2 F kt N a ln q ni Fermi potential of material 2qN 1/2 a C ox s Body bias coefficient 12

13 Channel-Length Modulation With depletion layer widening, the channel length is in effect reduced from L to L-L Channel-length modulation This leads to the following I-V relationship 1 i k W v V v 2 L ' 2 D n GS T 1 DS Where is a process technology parameter 13

14 Channel-Length Modulation Channel-length modulation causes i D to increase with v DS in saturation region 14

15 Gate Capacitance V 0 V 0, V small GT GT DS Capacitance Depends on bias Fringing fields are present Account for overlap C V GT 0, V large DS 15

16 Capacitance Gate Capacitance C G determines the amount of charge to switch gate Several distributed components Large discontinuity as device turns on At saturation capacitance is entirely between gate and source Define VDS X V V GS T 2 1 X Cgs Cgso WLCox X 2 1 Cgd Cgdo WLCox X

17 MOS Capacitances Expect capacitance between every two of the four terminals. 17

18 PMOS Transistor 0 PMOS VGS= VGS=-1.0 VGS=-1.5 VGS=-2.0 VGS= All polarities are reversed from nmos - v GS, v DS and V t are negative - Current i D enters source and leaves through drain - Hole mobility is lower low transconductance - nmos favored over pmos Vds 18

19 Complementary MOS CMOS Characteristics Combine nmos and pmos transistors pmos size is larger for electrical symmetry 19

20 CMOS Advantages Virtually, no DC power consumed No DC path between power and ground Excellent noise margins (V OL =0, V OH =V DD ) Inverter has sharp transfer curve Drawbacks Requires more transistors Process is more complicated pmos size larger to achieve electrical symmetry Latch up 20

21 Voltage Transfer Characteristics (VTC) The static operation of a logic circuit is determined by its VTC In low state: noise margin is NM L NM V V L IL OL In high state: noise margin is NM H NM V V H OH IH An ideal VTC will maximize noise margins NM L NM H V IL and V IH are the points where the slope of the VTC=-1 Optimum: NM NM V L H DD /2 21

22 Switching Time & Propagation Delay input output 22

23 Switching Time & Propagation Delay t r =rise time (from 10% to 90%) t f =fall time (from 90% to 10%) t plh =low-to-high propagation delay t phl =high-to-low propagation delay Inverter propagation delay: t p tplh tphl

24 NMOS Switch 24

25 CMOS Switch CMOS switch is called an inverter The body of each device is connected to its source NO BODY EFFECT 25

26 CMOS Switch Input Low GSN NMOS V V OFF TN r dsn high r dsp PMOS 1 k W V V ' p DD TP L p r dsp is low 26

27 r dsn CMOS Switch Input High NMOS 1 W k V V r dsn is low ' n DD TN L n GSP PMOS V V OFF TP r dsp high 27

28 CMOS Inverter r dsn 1 k W V V ' N DD T L n r dsp 1 k W V V ' P DD T L p Short switching transient current low power 28

29 CMOS Inverter Advantages of CMOS inverter Output voltage levels are 0 and V DD signal swing is maximum possible Static power dissipation is zero Low resistance paths to V DD and ground when needed High output driving capability increased speed Input resistance is infinite high fan-out Load driving capability of CMOS is high. Transistors can sink or source large load currents that can be used to charge and discharge load capacitances. 29

30 Matched CMOS Inverter VTC CMOS inverter can be made to switch at specific threshold voltage by appropriately sizing the transistors W n W L L p p Symmetrical transfer characteristics is obtained via matching equal current driving capabilities in both directions (pull-up and pull-down) n 30

31 CMOS Dynamic Operation Exact analysis is too tedious Replace all the capacitances in the circuit by a single equivalent capacitance C connected between the output node of the inverter and ground Analyze capacitively loaded inverter to determine propagation delay 31

32 CMOS Dynamic Operation 1 t t t 2 P PHL PLH Components can be equalized by matching transistors t P is proportional to C reduce capacitance Larger V DD means lower t p Conflicting requirements exist 32

33 CMOS Dynamic Power Dissipation In every cycle Q N dissipate ½ CV DD2 of energy Q P dissipate ½ CV DD2 of energy Total energy dissipation is CV DD 2 If inverter is switched at f cycles per second, dynamic 2 power dissipation is: P D fcv DD 33

34 De Morgan s Law Digital Logic - Generalization ABC... ABC... ABC... ABC... Distributive Law AB AC BC BD A( B C) B( C D) General Procedure 1. Design PDN to satisfy logic function 2. Construct PUN to be complementary of PDN in every way 3. Optimize using distributive rule 34

35 Pull-Down and Pull-Up PDN-parallel NMOS PUN-series PMOS Truth Tables YDP AB YUS AB 35

36 Two-Input NOR Gate Y AB AB 36

37 Pull-Down and Pull-Up PDN-Series NMOS PUN-Parallel PMOS YDS AB Truth Tables Y A B UP 37

38 Two-Input NAND Gate Y AB AB 38

39 CMOS Logic Gate Circuits Two Networks Pull-down network (PDN) with NMOS Pull-up network (PUN) with PMOS PUN conducts when inputs are low and consists of PMOS transistors PDN consists of NMOS transistors and is active when inputs are high PDN and PUN utilize devices In parallel to form OR functions In series to form AND functions 39

40 Basic Logic Function Basic Function INVERTER NOR NAND Symbol # Devices PUN 1 PMOS 2 PMOS-Series 2 PMOS-Parallel # Devices PDN 1 NMOS 2 NMOS-Parallel 2 NMOS-Series Truth Table 40

41 pull down Example Implement the function Y AB C pull up Y ABC ABC ( AB) C 41

42 Exclusive-OR (XOR) Function Y AB AB Y ( AB)( AB) XOR pull down A B Y pull up 42

ECE 342 Electronic Circuits. 3. MOS Transistors

ECE 342 Electronic Circuits. 3. MOS Transistors ECE 342 Electronic Circuits 3. MOS Transistors Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jschutt@emlab.uiuc.edu 1 NMOS Transistor Typically L = 0.1 to 3 m, W = 0.2 to

More information

ECE 342 Electronic Circuits. Lecture 6 MOS Transistors

ECE 342 Electronic Circuits. Lecture 6 MOS Transistors ECE 342 Electronic Circuits Lecture 6 MOS Transistors Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jesa@illinois.edu 1 NMOS Transistor Typically L = 0.1 to 3 m, W = 0.2

More information

ECE 342 Solid State Devices & Circuits 4. CMOS

ECE 342 Solid State Devices & Circuits 4. CMOS ECE 34 Solid State Devices & Circuits 4. CMOS Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jschutt@emlab.uiuc.edu ECE 34 Jose Schutt Aine 1 Digital Circuits V IH : Input

More information

ECE 497 JS Lecture - 12 Device Technologies

ECE 497 JS Lecture - 12 Device Technologies ECE 497 JS Lecture - 12 Device Technologies Spring 2004 Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jose@emlab.uiuc.edu 1 NMOS Transistor 2 ρ Source channel charge density

More information

ECE 342 Electronic Circuits. Lecture 34 CMOS Logic

ECE 342 Electronic Circuits. Lecture 34 CMOS Logic ECE 34 Electronic Circuits Lecture 34 CMOS Logic Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jesa@illinois.edu 1 De Morgan s Law Digital Logic - Generalization ABC... ABC...

More information

ECE 342 Electronic Circuits. Lecture 35 CMOS Delay Model

ECE 342 Electronic Circuits. Lecture 35 CMOS Delay Model ECE 34 Electronic Circuits Lecture 35 CMOS Delay Model Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jesa@illinois.edu ECE 34 Jose Schutt Aine 1 Digital Circuits V IH : Input

More information

2007 Fall: Electronic Circuits 2 CHAPTER 10. Deog-Kyoon Jeong School of Electrical Engineering

2007 Fall: Electronic Circuits 2 CHAPTER 10. Deog-Kyoon Jeong School of Electrical Engineering 007 Fall: Electronic Circuits CHAPTER 10 Digital CMOS Logic Circuits Deog-Kyoon Jeong dkjeong@snu.ac.kr k School of Electrical Engineering Seoul lnational luniversity it Introduction In this chapter, we

More information

CMPEN 411 VLSI Digital Circuits. Lecture 04: CMOS Inverter (static view)

CMPEN 411 VLSI Digital Circuits. Lecture 04: CMOS Inverter (static view) CMPEN 411 VLSI Digital Circuits Lecture 04: CMOS Inverter (static view) Kyusun Choi [Adapted from Rabaey s Digital Integrated Circuits, Second Edition, 2003 J. Rabaey, A. Chandrakasan, B. Nikolic] CMPEN

More information

DC and Transient Responses (i.e. delay) (some comments on power too!)

DC and Transient Responses (i.e. delay) (some comments on power too!) DC and Transient Responses (i.e. delay) (some comments on power too!) Michael Niemier (Some slides based on lecture notes by David Harris) 1 Lecture 02 - CMOS Transistor Theory & the Effects of Scaling

More information

Fig. 1 CMOS Transistor Circuits (a) Inverter Out = NOT In, (b) NOR-gate C = NOT (A or B)

Fig. 1 CMOS Transistor Circuits (a) Inverter Out = NOT In, (b) NOR-gate C = NOT (A or B) 1 Introduction to Transistor-Level Logic Circuits 1 By Prawat Nagvajara At the transistor level of logic circuits, transistors operate as switches with the logic variables controlling the open or closed

More information

CMOS INVERTER. Last Lecture. Metrics for qualifying digital circuits. »Cost» Reliability» Speed (delay)»performance

CMOS INVERTER. Last Lecture. Metrics for qualifying digital circuits. »Cost» Reliability» Speed (delay)»performance CMOS INVERTER Last Lecture Metrics for qualifying digital circuits»cost» Reliability» Speed (delay)»performance 1 Today s lecture The CMOS inverter at a glance An MOS transistor model for manual analysis

More information

ENGR890 Digital VLSI Design Fall Lecture 4: CMOS Inverter (static view)

ENGR890 Digital VLSI Design Fall Lecture 4: CMOS Inverter (static view) ENGR89 Digital VLSI Design Fall 5 Lecture 4: CMOS Inverter (static view) [Adapted from Chapter 5 of Digital Integrated Circuits, 3, J. Rabaey et al.] [Also borrowed from Vijay Narayanan and Mary Jane Irwin]

More information

MOS Transistor Theory

MOS Transistor Theory MOS Transistor Theory So far, we have viewed a MOS transistor as an ideal switch (digital operation) Reality: less than ideal EE 261 Krish Chakrabarty 1 Introduction So far, we have treated transistors

More information

Today s lecture. EE141- Spring 2003 Lecture 4. Design Rules CMOS Inverter MOS Transistor Model

Today s lecture. EE141- Spring 2003 Lecture 4. Design Rules CMOS Inverter MOS Transistor Model - Spring 003 Lecture 4 Design Rules CMOS Inverter MOS Transistor Model Today s lecture Design Rules The CMOS inverter at a glance An MOS transistor model for manual analysis Important! Labs start next

More information

MOS Transistor Theory

MOS Transistor Theory CHAPTER 3 MOS Transistor Theory Outline 2 1. Introduction 2. Ideal I-V Characteristics 3. Nonideal I-V Effects 4. C-V Characteristics 5. DC Transfer Characteristics 6. Switch-level RC Delay Models MOS

More information

CHAPTER 15 CMOS DIGITAL LOGIC CIRCUITS

CHAPTER 15 CMOS DIGITAL LOGIC CIRCUITS CHAPTER 5 CMOS DIGITAL LOGIC CIRCUITS Chapter Outline 5. CMOS Logic Gate Circuits 5. Digital Logic Inverters 5.3 The CMOS Inverter 5.4 Dynamic Operation of the CMOS Inverter 5.5 Transistor Sizing 5.6 Power

More information

THE INVERTER. Inverter

THE INVERTER. Inverter THE INVERTER DIGITAL GATES Fundamental Parameters Functionality Reliability, Robustness Area Performance» Speed (delay)» Power Consumption» Energy Noise in Digital Integrated Circuits v(t) V DD i(t) (a)

More information

Lecture 12 Digital Circuits (II) MOS INVERTER CIRCUITS

Lecture 12 Digital Circuits (II) MOS INVERTER CIRCUITS Lecture 12 Digital Circuits (II) MOS INVERTER CIRCUITS Outline NMOS inverter with resistor pull-up The inverter NMOS inverter with current-source pull-up Complementary MOS (CMOS) inverter Static analysis

More information

CMOS Inverter (static view)

CMOS Inverter (static view) Review: Design Abstraction Levels SYSTEM CMOS Inverter (static view) + MODULE GATE [Adapted from Chapter 5. 5.3 CIRCUIT of G DEVICE Rabaey s Digital Integrated Circuits,, J. Rabaey et al.] S D Review:

More information

ECE 438: Digital Integrated Circuits Assignment #4 Solution The Inverter

ECE 438: Digital Integrated Circuits Assignment #4 Solution The Inverter ECE 438: Digital Integrated Circuits Assignment #4 The Inverter Text: Chapter 5, Digital Integrated Circuits 2 nd Ed, Rabaey 1) Consider the CMOS inverter circuit in Figure P1 with the following parameters.

More information

Lecture 14 - Digital Circuits (III) CMOS. April 1, 2003

Lecture 14 - Digital Circuits (III) CMOS. April 1, 2003 6.12 - Microelectronic Devices and Circuits - Spring 23 Lecture 14-1 Lecture 14 - Digital Circuits (III) CMOS April 1, 23 Contents: 1. Complementary MOS (CMOS) inverter: introduction 2. CMOS inverter:

More information

EEE 421 VLSI Circuits

EEE 421 VLSI Circuits EEE 421 CMOS Properties Full rail-to-rail swing high noise margins» Logic levels not dependent upon the relative device sizes transistors can be minimum size ratioless Always a path to V dd or GND in steady

More information

Lecture 5: DC & Transient Response

Lecture 5: DC & Transient Response Lecture 5: DC & Transient Response Outline q Pass Transistors q DC Response q Logic Levels and Noise Margins q Transient Response q RC Delay Models q Delay Estimation 2 Activity 1) If the width of a transistor

More information

Lecture 12: MOSFET Devices

Lecture 12: MOSFET Devices Lecture 12: MOSFET Devices Gu-Yeon Wei Division of Engineering and Applied Sciences Harvard University guyeon@eecs.harvard.edu Wei 1 Overview Reading S&S: Chapter 5.1~5.4 Supplemental Reading Background

More information

Lecture 12 Circuits numériques (II)

Lecture 12 Circuits numériques (II) Lecture 12 Circuits numériques (II) Circuits inverseurs MOS Outline NMOS inverter with resistor pull-up The inverter NMOS inverter with current-source pull-up Complementary MOS (CMOS) inverter Static analysis

More information

EEC 118 Lecture #6: CMOS Logic. Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation

EEC 118 Lecture #6: CMOS Logic. Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation EEC 118 Lecture #6: CMOS Logic Rajeevan mirtharajah University of California, Davis Jeff Parkhurst Intel Corporation nnouncements Quiz 1 today! Lab 2 reports due this week Lab 3 this week HW 3 due this

More information

EE 434 Lecture 33. Logic Design

EE 434 Lecture 33. Logic Design EE 434 Lecture 33 Logic Design Review from last time: Ask the inverter how it will interpret logic levels V IN V OUT V H =? V L =? V LARGE V H V L V H Review from last time: The two-inverter loop X Y X

More information

Lecture 6: DC & Transient Response

Lecture 6: DC & Transient Response Lecture 6: DC & Transient Response Slides courtesy of Deming Chen Slides based on the initial set from David Harris CMOS VLSI Design Outline Pass Transistors DC Response Logic Levels and Noise Margins

More information

High-to-Low Propagation Delay t PHL

High-to-Low Propagation Delay t PHL High-to-Low Propagation Delay t PHL V IN switches instantly from low to high. Driver transistor (n-channel) immediately switches from cutoff to saturation; the p-channel pull-up switches from triode to

More information

Properties of CMOS Gates Snapshot

Properties of CMOS Gates Snapshot MOS logic 1 Properties of MOS Gates Snapshot High noise margins: V OH and V OL are at V DD and GND, respectively. No static power consumption: There never exists a direct path between V DD and V SS (GND)

More information

Lecture 5: DC & Transient Response

Lecture 5: DC & Transient Response Lecture 5: DC & Transient Response Outline Pass Transistors DC Response Logic Levels and Noise Margins Transient Response RC Delay Models Delay Estimation 2 Pass Transistors We have assumed source is grounded

More information

DC & Transient Responses

DC & Transient Responses ECEN454 Digital Integrated Circuit Design DC & Transient Responses ECEN 454 DC Response DC Response: vs. for a gate Ex: Inverter When = -> = When = -> = In between, depends on transistor size and current

More information

The CMOS Inverter: A First Glance

The CMOS Inverter: A First Glance The CMOS Inverter: A First Glance V DD S D V in V out C L D S CMOS Inverter N Well V DD V DD PMOS 2λ PMOS Contacts In Out In Out Metal 1 NMOS Polysilicon NMOS GND CMOS Inverter: Steady State Response V

More information

CMPEN 411 VLSI Digital Circuits. Lecture 03: MOS Transistor

CMPEN 411 VLSI Digital Circuits. Lecture 03: MOS Transistor CMPEN 411 VLSI Digital Circuits Lecture 03: MOS Transistor Kyusun Choi [Adapted from Rabaey s Digital Integrated Circuits, Second Edition, 2003 J. Rabaey, A. Chandrakasan, B. Nikolic] CMPEN 411 L03 S.1

More information

Lecture 4: DC & Transient Response

Lecture 4: DC & Transient Response Introduction to CMOS VLSI Design Lecture 4: DC & Transient Response David Harris Harvey Mudd College Spring 004 Outline DC Response Logic Levels and Noise Margins Transient Response Delay Estimation Slide

More information

5.0 CMOS Inverter. W.Kucewicz VLSICirciuit Design 1

5.0 CMOS Inverter. W.Kucewicz VLSICirciuit Design 1 5.0 CMOS Inverter W.Kucewicz VLSICirciuit Design 1 Properties Switching Threshold Dynamic Behaviour Capacitance Propagation Delay nmos/pmos Ratio Power Consumption Contents W.Kucewicz VLSICirciuit Design

More information

4.10 The CMOS Digital Logic Inverter

4.10 The CMOS Digital Logic Inverter 11/11/2004 section 4_10 The CMOS Digital Inverter blank.doc 1/1 4.10 The CMOS Digital Logic Inverter Reading Assignment: pp. 336346 Complementary MOSFET (CMOS) is the predominant technology for constructing

More information

The Physical Structure (NMOS)

The Physical Structure (NMOS) The Physical Structure (NMOS) Al SiO2 Field Oxide Gate oxide S n+ Polysilicon Gate Al SiO2 SiO2 D n+ L channel P Substrate Field Oxide contact Metal (S) n+ (G) L W n+ (D) Poly 1 Transistor Resistance Two

More information

Important! EE141- Fall 2002 Lecture 5. CMOS Inverter MOS Transistor Model

Important! EE141- Fall 2002 Lecture 5. CMOS Inverter MOS Transistor Model - Fall 00 Lecture 5 CMO Inverter MO Transistor Model Important! Lab 3 this week You must show up in one of the lab sessions this week If you don t show up you will be dropped from the class» Unless you

More information

EE5780 Advanced VLSI CAD

EE5780 Advanced VLSI CAD EE5780 Advanced VLSI CAD Lecture 4 DC and Transient Responses, Circuit Delays Zhuo Feng 4.1 Outline Pass Transistors DC Response Logic Levels and Noise Margins Transient Response RC Delay Models Delay

More information

MOSFET: Introduction

MOSFET: Introduction E&CE 437 Integrated VLSI Systems MOS Transistor 1 of 30 MOSFET: Introduction Metal oxide semiconductor field effect transistor (MOSFET) or MOS is widely used for implementing digital designs Its major

More information

EEC 116 Lecture #5: CMOS Logic. Rajeevan Amirtharajah Bevan Baas University of California, Davis Jeff Parkhurst Intel Corporation

EEC 116 Lecture #5: CMOS Logic. Rajeevan Amirtharajah Bevan Baas University of California, Davis Jeff Parkhurst Intel Corporation EEC 116 Lecture #5: CMOS Logic Rajeevan mirtharajah Bevan Baas University of California, Davis Jeff Parkhurst Intel Corporation nnouncements Quiz 1 today! Lab 2 reports due this week Lab 3 this week HW

More information

EE 330 Lecture 36. Digital Circuits. Transfer Characteristics of the Inverter Pair One device sizing strategy Multiple-input gates

EE 330 Lecture 36. Digital Circuits. Transfer Characteristics of the Inverter Pair One device sizing strategy Multiple-input gates EE 330 Lecture 36 Digital Circuits Transfer Characteristics of the Inverter Pair One device sizing strategy Multiple-input gates Review from Last Time The basic logic gates It suffices to characterize

More information

Miscellaneous Lecture topics. Mary Jane Irwin [Adapted from Rabaey s Digital Integrated Circuits, 2002, J. Rabaey et al.]

Miscellaneous Lecture topics. Mary Jane Irwin [Adapted from Rabaey s Digital Integrated Circuits, 2002, J. Rabaey et al.] Miscellaneous Lecture topics Mary Jane Irwin [dapted from Rabaey s Digital Integrated Circuits, 2002, J. Rabaey et al.] MOS Switches MOS transistors can be viewed as simple switches. In an N-Switch, the

More information

DC and Transient. Courtesy of Dr. Daehyun Dr. Dr. Shmuel and Dr.

DC and Transient. Courtesy of Dr. Daehyun Dr. Dr. Shmuel and Dr. DC and Transient Courtesy of Dr. Daehyun Lim@WSU, Dr. Harris@HMC, Dr. Shmuel Wimer@BIU and Dr. Choi@PSU http://csce.uark.edu +1 (479) 575-604 yrpeng@uark.edu Pass Transistors We have assumed source is

More information

EEC 116 Lecture #3: CMOS Inverters MOS Scaling. Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation

EEC 116 Lecture #3: CMOS Inverters MOS Scaling. Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation EEC 116 Lecture #3: CMOS Inverters MOS Scaling Rajeevan Amirtharajah University of California, Davis Jeff Parhurst Intel Corporation Outline Review: Inverter Transfer Characteristics Lecture 3: Noise Margins,

More information

The Devices. Digital Integrated Circuits A Design Perspective. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic. July 30, 2002

The Devices. Digital Integrated Circuits A Design Perspective. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic. July 30, 2002 Digital Integrated Circuits A Design Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic The Devices July 30, 2002 Goal of this chapter Present intuitive understanding of device operation Introduction

More information

The CMOS Inverter: A First Glance

The CMOS Inverter: A First Glance The CMOS Inverter: A First Glance V DD V in V out C L CMOS Properties Full rail-to-rail swing Symmetrical VTC Propagation delay function of load capacitance and resistance of transistors No static power

More information

MOSFET and CMOS Gate. Copy Right by Wentai Liu

MOSFET and CMOS Gate. Copy Right by Wentai Liu MOSFET and CMOS Gate CMOS Inverter DC Analysis - Voltage Transfer Curve (VTC) Find (1) (2) (3) (4) (5) (6) V OH min, V V OL min, V V IH min, V V IL min, V OHmax OLmax IHmax ILmax NM L = V ILmax V OL max

More information

Lecture 15: MOS Transistor models: Body effects, SPICE models. Context. In the last lecture, we discussed the modes of operation of a MOS FET:

Lecture 15: MOS Transistor models: Body effects, SPICE models. Context. In the last lecture, we discussed the modes of operation of a MOS FET: Lecture 15: MOS Transistor models: Body effects, SPICE models Context In the last lecture, we discussed the modes of operation of a MOS FET: oltage controlled resistor model I- curve (Square-Law Model)

More information

EE105 - Fall 2006 Microelectronic Devices and Circuits

EE105 - Fall 2006 Microelectronic Devices and Circuits EE105 - Fall 2006 Microelectronic Devices and Circuits Prof. Jan M. Rabaey (jan@eecs) Lecture 7: MOS Transistor Some Administrative Issues Lab 2 this week Hw 2 due on We Hw 3 will be posted same day MIDTERM

More information

Digital Integrated Circuits A Design Perspective

Digital Integrated Circuits A Design Perspective Digital Integrated Circuits Design Perspective Jan M. Rabaey nantha Chandrakasan orivoje Nikolić Designing Combinational Logic Circuits November 2002. 1 Combinational vs. Sequential Logic In Combinational

More information

EE141Microelettronica. CMOS Logic

EE141Microelettronica. CMOS Logic Microelettronica CMOS Logic CMOS logic Power consumption in CMOS logic gates Where Does Power Go in CMOS? Dynamic Power Consumption Charging and Discharging Capacitors Short Circuit Currents Short Circuit

More information

EE5311- Digital IC Design

EE5311- Digital IC Design EE5311- Digital IC Design Module 3 - The Inverter Janakiraman V Assistant Professor Department of Electrical Engineering Indian Institute of Technology Madras Chennai September 6, 2017 Janakiraman, IITM

More information

Digital Microelectronic Circuits ( ) The CMOS Inverter. Lecture 4: Presented by: Adam Teman

Digital Microelectronic Circuits ( ) The CMOS Inverter. Lecture 4: Presented by: Adam Teman Digital Microelectronic Circuits (361-1-301 ) Presented by: Adam Teman Lecture 4: The CMOS Inverter 1 Last Lectures Moore s Law Terminology» Static Properties» Dynamic Properties» Power The MOSFET Transistor»

More information

CPE/EE 427, CPE 527 VLSI Design I L06: CMOS Inverter, CMOS Logic Gates. Course Administration. CMOS Inverter: A First Look

CPE/EE 427, CPE 527 VLSI Design I L06: CMOS Inverter, CMOS Logic Gates. Course Administration. CMOS Inverter: A First Look CPE/EE 47, CPE 57 VLSI esign I L6: CMOS Inverter, CMOS Logic Gates epartment of Electrical and Computer Engineering University of labama in Huntsville leksandar Milenkovic ( www.ece.uah.edu/~milenka )

More information

Practice 3: Semiconductors

Practice 3: Semiconductors Practice 3: Semiconductors Digital Electronic Circuits Semester A 2012 VLSI Fabrication Process VLSI Very Large Scale Integration The ability to fabricate many devices on a single substrate within a given

More information

MOS Transistor I-V Characteristics and Parasitics

MOS Transistor I-V Characteristics and Parasitics ECEN454 Digital Integrated Circuit Design MOS Transistor I-V Characteristics and Parasitics ECEN 454 Facts about Transistors So far, we have treated transistors as ideal switches An ON transistor passes

More information

EE 330 Lecture 37. Digital Circuits. Other Logic Families. Propagation Delay basic characterization Device Sizing (Inverter and multiple-input gates)

EE 330 Lecture 37. Digital Circuits. Other Logic Families. Propagation Delay basic characterization Device Sizing (Inverter and multiple-input gates) EE 330 Lecture 37 Digital Circuits Other Logic Families Static Power Dissipation Propagation Delay basic characterization Device Sizing (Inverter and multiple-input gates) Review from Last Time Inverter

More information

5. CMOS Gate Characteristics CS755

5. CMOS Gate Characteristics CS755 5. CMOS Gate Characteristics Last module: CMOS Transistor theory This module: DC Response Logic Levels and Noise Margins Transient Response Delay Estimation Transistor ehavior 1) If the width of a transistor

More information

EE 230 Lecture 31. THE MOS TRANSISTOR Model Simplifcations THE Bipolar Junction TRANSISTOR

EE 230 Lecture 31. THE MOS TRANSISTOR Model Simplifcations THE Bipolar Junction TRANSISTOR EE 23 Lecture 3 THE MOS TRANSISTOR Model Simplifcations THE Bipolar Junction TRANSISTOR Quiz 3 Determine I X. Assume W=u, L=2u, V T =V, uc OX = - 4 A/V 2, λ= And the number is? 3 8 5 2? 6 4 9 7 Quiz 3

More information

Lecture 4: CMOS Transistor Theory

Lecture 4: CMOS Transistor Theory Introduction to CMOS VLSI Design Lecture 4: CMOS Transistor Theory David Harris, Harvey Mudd College Kartik Mohanram and Steven Levitan University of Pittsburgh Outline q Introduction q MOS Capacitor q

More information

Integrated Circuits & Systems

Integrated Circuits & Systems Federal University of Santa Catarina Center for Technology Computer Science & Electronics Engineering Integrated Circuits & Systems INE 5442 Lecture 16 CMOS Combinational Circuits - 2 guntzel@inf.ufsc.br

More information

EEC 118 Lecture #2: MOSFET Structure and Basic Operation. Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation

EEC 118 Lecture #2: MOSFET Structure and Basic Operation. Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation EEC 118 Lecture #2: MOSFET Structure and Basic Operation Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation Announcements Lab 1 this week, report due next week Bring

More information

Digital Integrated Circuits A Design Perspective

Digital Integrated Circuits A Design Perspective igital Integrated Circuits esign Perspective esigning Combinational Logic Circuits 1 Combinational vs. Sequential Logic In Combinational Logic Circuit Out In Combinational Logic Circuit Out State Combinational

More information

ESE 570: Digital Integrated Circuits and VLSI Fundamentals

ESE 570: Digital Integrated Circuits and VLSI Fundamentals ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 15: March 15, 2018 Euler Paths, Energy Basics and Optimization Midterm! Midterm " Mean: 89.7 " Standard Dev: 8.12 2 Lecture Outline! Euler

More information

EE 230 Lecture 33. Nonlinear Circuits and Nonlinear Devices. Diode BJT MOSFET

EE 230 Lecture 33. Nonlinear Circuits and Nonlinear Devices. Diode BJT MOSFET EE 230 Lecture 33 Nonlinear Circuits and Nonlinear Devices Diode BJT MOSFET Review from Last Time: n-channel MOSFET Source Gate L Drain W L EFF Poly Gate oxide n-active p-sub depletion region (electrically

More information

Lecture 3: CMOS Transistor Theory

Lecture 3: CMOS Transistor Theory Lecture 3: CMOS Transistor Theory Outline Introduction MOS Capacitor nmos I-V Characteristics pmos I-V Characteristics Gate and Diffusion Capacitance 2 Introduction So far, we have treated transistors

More information

CMOS Inverter: CPE/EE 427, CPE 527 VLSI Design I L06: CMOS Inverter, CMOS Logic Gates. Course Administration. CMOS Properties.

CMOS Inverter: CPE/EE 427, CPE 527 VLSI Design I L06: CMOS Inverter, CMOS Logic Gates. Course Administration. CMOS Properties. CMOS Inverter: Steady State Response CPE/EE 47, CPE 57 VLSI esign I L6: CMOS Inverter, CMOS Logic Gates R p V OL = V OH = V M = f(r n, R p ) epartment of Electrical and Computer Engineering University

More information

EE105 - Fall 2005 Microelectronic Devices and Circuits

EE105 - Fall 2005 Microelectronic Devices and Circuits EE105 - Fall 005 Microelectronic Devices and Circuits ecture 7 MOS Transistor Announcements Homework 3, due today Homework 4 due next week ab this week Reading: Chapter 4 1 ecture Material ast lecture

More information

Lecture 11 VTCs and Delay. No lab today, Mon., Tues. Labs restart next week. Midterm #1 Tues. Oct. 7 th, 6:30-8:00pm in 105 Northgate

Lecture 11 VTCs and Delay. No lab today, Mon., Tues. Labs restart next week. Midterm #1 Tues. Oct. 7 th, 6:30-8:00pm in 105 Northgate EE4-Fall 2008 Digital Integrated Circuits Lecture VTCs and Delay Lecture # Announcements No lab today, Mon., Tues. Labs restart next week Midterm # Tues. Oct. 7 th, 6:30-8:00pm in 05 Northgate Exam is

More information

The Devices: MOS Transistors

The Devices: MOS Transistors The Devices: MOS Transistors References: Semiconductor Device Fundamentals, R. F. Pierret, Addison-Wesley Digital Integrated Circuits: A Design Perspective, J. Rabaey et.al. Prentice Hall NMOS Transistor

More information

Chapter 4 Field-Effect Transistors

Chapter 4 Field-Effect Transistors Chapter 4 Field-Effect Transistors Microelectronic Circuit Design Richard C. Jaeger Travis N. Blalock 5/5/11 Chap 4-1 Chapter Goals Describe operation of MOSFETs. Define FET characteristics in operation

More information

Review of Band Energy Diagrams MIS & MOS Capacitor MOS TRANSISTORS MOSFET Capacitances MOSFET Static Model

Review of Band Energy Diagrams MIS & MOS Capacitor MOS TRANSISTORS MOSFET Capacitances MOSFET Static Model Content- MOS Devices and Switching Circuits Review of Band Energy Diagrams MIS & MOS Capacitor MOS TRANSISTORS MOSFET Capacitances MOSFET Static Model A Cantoni 2009-2013 Digital Switching 1 Content- MOS

More information

and V DS V GS V T (the saturation region) I DS = k 2 (V GS V T )2 (1+ V DS )

and V DS V GS V T (the saturation region) I DS = k 2 (V GS V T )2 (1+ V DS ) ECE 4420 Spring 2005 Page 1 FINAL EXAMINATION NAME SCORE /100 Problem 1O 2 3 4 5 6 7 Sum Points INSTRUCTIONS: This exam is closed book. You are permitted four sheets of notes (three of which are your sheets

More information

L ECE 4211 UConn F. Jain Scaling Laws for NanoFETs Chapter 10 Logic Gate Scaling

L ECE 4211 UConn F. Jain Scaling Laws for NanoFETs Chapter 10 Logic Gate Scaling L13 04202017 ECE 4211 UConn F. Jain Scaling Laws for NanoFETs Chapter 10 Logic Gate Scaling Scaling laws: Generalized scaling (GS) p. 610 Design steps p.613 Nanotransistor issues (page 626) Degradation

More information

Chapter 2 MOS Transistor theory

Chapter 2 MOS Transistor theory Chapter MOS Transistor theory.1 Introduction An MOS transistor is a majority-carrier device, which the current a conductg channel between the source and the dra is modulated by a voltage applied to the

More information

Integrated Circuits & Systems

Integrated Circuits & Systems Federal University of Santa Catarina Center for Technology Computer Science & Electronics Engineering Integrated Circuits & Systems INE 5442 Lecture 10 MOSFET part 1 guntzel@inf.ufsc.br ual-well Trench-Isolated

More information

9/18/2008 GMU, ECE 680 Physical VLSI Design

9/18/2008 GMU, ECE 680 Physical VLSI Design ECE680: Physical VLSI Design Chapter III CMOS Device, Inverter, Combinational circuit Logic and Layout Part 3 Combinational Logic Gates (textbook chapter 6) 9/18/2008 GMU, ECE 680 Physical VLSI Design

More information

Integrated Circuits & Systems

Integrated Circuits & Systems Federal University of Santa Catarina Center for Technology Computer Science & Electronics Engineering Integrated Circuits & Systems INE 5442 Lecture 12 The CMOS Inverter: static behavior guntzel@inf.ufsc.br

More information

L2: Combinational Logic Design (Construction and Boolean Algebra)

L2: Combinational Logic Design (Construction and Boolean Algebra) L2: Combinational Logic Design (Construction and Boolean Algebra) Acknowledgements: Lecture material adapted from Chapter 2 of R. Katz, G. Borriello, Contemporary Logic Design (second edition), Pearson

More information

Device Models (PN Diode, MOSFET )

Device Models (PN Diode, MOSFET ) Device Models (PN Diode, MOSFET ) Instructor: Steven P. Levitan steve@ece.pitt.edu TA: Gayatri Mehta, José Martínez Book: Digital Integrated Circuits: A Design Perspective; Jan Rabaey Lab Notes: Handed

More information

VLSI Design and Simulation

VLSI Design and Simulation VLSI Design and Simulation CMOS Inverters Topics Inverter VTC Noise Margin Static Load Inverters CMOS Inverter First-Order DC Analysis R p V OL = 0 V OH = R n =0 = CMOS Inverter: Transient Response R p

More information

Midterm. ESE 570: Digital Integrated Circuits and VLSI Fundamentals. Lecture Outline. Pass Transistor Logic. Restore Output.

Midterm. ESE 570: Digital Integrated Circuits and VLSI Fundamentals. Lecture Outline. Pass Transistor Logic. Restore Output. ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 16: March 21, 2017 Transmission Gates, Euler Paths, Energy Basics Review Midterm! Midterm " Mean: 79.5 " Standard Dev: 14.5 2 Lecture Outline!

More information

CMOS Logic Gates. University of Connecticut 181

CMOS Logic Gates. University of Connecticut 181 CMOS Logic Gates University of Connecticut 181 Basic CMOS Inverter Operation V IN P O N O p-channel enhancementtype MOSFET; V T < 0 n-channel enhancementtype MOSFET; V T > 0 If V IN 0, N O is cut off and

More information

MOS Transistor Properties Review

MOS Transistor Properties Review MOS Transistor Properties Review 1 VLSI Chip Manufacturing Process Photolithography: transfer of mask patterns to the chip Diffusion or ion implantation: selective doping of Si substrate Oxidation: SiO

More information

Lecture 13 - Digital Circuits (II) MOS Inverter Circuits. March 20, 2003

Lecture 13 - Digital Circuits (II) MOS Inverter Circuits. March 20, 2003 6.012 Microelectronic Devices and Circuits Spring 2003 Lecture 131 Lecture 13 Digital Circuits (II) MOS Inverter Circuits March 20, 2003 Contents: 1. NMOS inverter with resistor pullup (cont.) 2. NMOS

More information

Step 1. Finding V M. Goal: Þnd V M = input voltage for the output = V M both transistors are saturated at V IN = V M since

Step 1. Finding V M. Goal: Þnd V M = input voltage for the output = V M both transistors are saturated at V IN = V M since Step 1. Finding V M Goal: Þnd V M = input voltage for the output = V M both transistors are saturated at V IN = V M since V DSn = V M - 0 > V M - V Tn V SDp = V DD - V M = (V DD - V M ) V Tp Equate drain

More information

EE5311- Digital IC Design

EE5311- Digital IC Design EE5311- Digital IC Design Module 3 - The Inverter Janakiraman V Assistant Professor Department of Electrical Engineering Indian Institute of Technology Madras Chennai September 3, 2018 Janakiraman, IITM

More information

ECE321 Electronics I

ECE321 Electronics I ECE31 Electronics Lecture 1: CMOS nverter: Noise Margin & Delay Model Payman Zarkesh-Ha Office: ECE Bldg. 30B Office hours: Tuesday :00-3:00PM or by appointment E-mail: payman@ece.unm.edu Slide: 1 CMOS

More information

Digital Integrated Circuits

Digital Integrated Circuits Chapter 6 The CMOS Inverter 1 Contents Introduction (MOST models) 0, 1 st, 2 nd order The CMOS inverter : The static behavior: o DC transfer characteristics, o Short-circuit current The CMOS inverter :

More information

Check course home page periodically for announcements. Homework 2 is due TODAY by 5pm In 240 Cory

Check course home page periodically for announcements. Homework 2 is due TODAY by 5pm In 240 Cory EE141 Fall 005 Lecture 6 MOS Capacitances, Propagation elay Important! Check course home page periodically for announcements Homework is due TOAY by 5pm In 40 Cory Homework 3 will be posted TOAY ue Thursday

More information

Lecture 12: MOS Capacitors, transistors. Context

Lecture 12: MOS Capacitors, transistors. Context Lecture 12: MOS Capacitors, transistors Context In the last lecture, we discussed PN diodes, and the depletion layer into semiconductor surfaces. Small signal models In this lecture, we will apply those

More information

CMPEN 411 VLSI Digital Circuits Spring 2011 Lecture 07: Pass Transistor Logic

CMPEN 411 VLSI Digital Circuits Spring 2011 Lecture 07: Pass Transistor Logic CMPEN 411 VLSI Digital Circuits Spring 2011 Lecture 07: Pass Transistor Logic [dapted from Rabaey s Digital Integrated Circuits, Second Edition, 2003 J. Rabaey,. Chandrakasan,. Nikolic] Sp11 CMPEN 411

More information

Device Models (PN Diode, MOSFET )

Device Models (PN Diode, MOSFET ) Device Models (PN Diode, MOSFET ) Instructor: Steven P. Levitan steve@ece.pitt.edu TA: Gayatri Mehta, José Martínez Book: Digital Integrated Circuits: A Design Perspective; Jan Rabaey Lab Notes: Handed

More information

ENEE 359a Digital VLSI Design

ENEE 359a Digital VLSI Design SLIDE 1 ENEE 359a Digital VLSI Design Prof. blj@eng.umd.edu Credit where credit is due: Slides contain original artwork ( Jacob 2004) as well as material taken liberally from Irwin & Vijay s CSE477 slides

More information

Field-Effect (FET) transistors

Field-Effect (FET) transistors Field-Effect (FET) transistors References: Barbow (Chapter 8), Rizzoni (chapters 8 & 9) In a field-effect transistor (FET), the width of a conducting channel in a semiconductor and, therefore, its current-carrying

More information

Electronic Devices and Circuits Lecture 15 - Digital Circuits: Inverter Basics - Outline Announcements. = total current; I D

Electronic Devices and Circuits Lecture 15 - Digital Circuits: Inverter Basics - Outline Announcements. = total current; I D 6.012 - Electronic Devices and Circuits Lecture 15 - Digital Circuits: Inverter asics - Outline Announcements Handout - Lecture Outline and Summary The MOSFET alpha factor - use definition in lecture,

More information

CMOS Technology for Computer Architects

CMOS Technology for Computer Architects CMOS Technology for Computer Architects Recap Technology Trends Lecture 2: Transistor Inverter Iakovos Mavroidis Giorgos Passas Manolis Katevenis FORTH-ICS (University of Crete) 1 2 Recap Threshold Voltage

More information

Announcements. EE141- Fall 2002 Lecture 7. MOS Capacitances Inverter Delay Power

Announcements. EE141- Fall 2002 Lecture 7. MOS Capacitances Inverter Delay Power - Fall 2002 Lecture 7 MOS Capacitances Inverter Delay Power Announcements Wednesday 12-3pm lab cancelled Lab 4 this week Homework 2 due today at 5pm Homework 3 posted tonight Today s lecture MOS capacitances

More information