Digital Integrated Circuits A Design Perspective. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic. The Devices. July 30, Devices.

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1 Digital Integrated Circuits A Design Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic The July 30,

2 Goal of this chapter Present intuitive understanding of device operation Introduction of basic device equations Introduction of models for manual analysis Introduction of models for SPICE simulation Analysis of secondary and deep-submicron effects Future trends 2

3 The Diode B Al A SiO 2 p n Cross-section of pn-junction in an IC process A p n B One-dimensional representation Al A B diode symbol Mostly occurring as parasitic element in Digital ICs 3

4 Depletion Region hole diffusion electron diffusion p n (a) Current flow. hole drift electron drift Charge Density - ρ + x Distance (b) Charge density. Electrical Field ξ x (c) Electric field. Potential V ψ 0 -W 1 W 2 x (d) Electrostatic potential. 4

5 Diode Current 5

6 Forward Bias p n (W 2 ) p n0 L p n p0 p-region -W 1 0 W 2 n-region x diffusion Typically avoided in Digital ICs 6

7 Reverse Bias p n0 n p0 p-region -W 1 0 W 2 n-region x diffusion The Dominant Operation Mode 7

8 Models for Manual Analysis V D + I D = I S (e V D/φT 1) V D + + I D V Don (a) Ideal diode model (b) First-order diode model 8

9 Junction Capacitance 9

10 Diffusion Capacitance 10

11 Secondary Effects 0.1 I D (A) V D (V) Avalanche Breakdown 11

12 Diode Model R S + V D - I D C D 12

13 SPICE Parameters 13

14 What is a Transistor? A Switch! An MOS Transistor V GS V T V GS S Ron D 14

15 The MOS Transistor Polysilicon Aluminum 15

16 MOS Transistors - Types and Symbols D D G G S NMOS Enhancement D NMOS S Depletion D G G B PMOS S Enhancement S NMOS with Bulk Contact 16

17 Threshold Voltage: Concept S - V GS + G D n+ n+ n-channel p-substrate Depletion Region B 17

18 The Threshold Voltage 18

19 The Body Effect V T (V) V BS (V) 19

20 Current-Voltage Relations A good ol transistor -4 x 10 6 VGS= 2.5 V 5 4 Resistive Saturation VGS= 2.0 V I D (A) 3 V DS = V GS -V T Quadratic Relationship 2 VGS= 1.5 V 1 VGS= 1.0 V V DS (V) 20

21 Transistor in Linear S V GS G V DS D I D n + V(x) + n + L x p-substrate B MOS transistor and its bias conditions 21

22 Transistor in Saturation V GS G V DS > V GS - V T S D n+ - V GS - V T + n+ Pinch-off 22

23 Current-Voltage Relations Long-Channel Device 23

24 A model for manual analysis 24

25 Current-Voltage Relations The Deep-Submicron Era 2.5 x Early Saturation VGS= 2.5 V 1.5 VGS= 2.0 V I D (A) 1 VGS= 1.5 V Linear Relationship 0.5 VGS= 1.0 V V DS (V) 25

26 Velocity Saturation υ n (m/s) υ sat = 10 5 Constant velocity Constant mobility (slope = µ) ξ c = 1.5 ξ (V/µm) 26

27 Perspective I D Long-channel device V GS = V DD Short-channel device V DSAT V GS -V T V DS 27

28 I D versus V GS 6 x x quadratic linear I D (A) 3 I D (A) V GS (V) Long Channel 0.5 quadratic V GS (V) Short Channel 28

29 I D versus V DS I D (A) 6 x VGS= 2.5 V Resistive Saturation VGS= 2.0 V V DS = V GS -V T VGS= 1.5 V I D (A) x 10 VGS= 2.5 V VGS= 2.0 V VGS= 1.5 V 1 VGS= 1.0 V 0.5 VGS= 1.0 V V DS (V) Long Channel V DS (V) Short Channel 29

30 unified model or r manual analysis G S D B 30

31 Simple Model versus SPICE 2.5 x 10-4 V DS =V DSAT Velocity Saturated I D (A) 1 Linear 0.5 V DSAT =V GT V DS =V GT Saturated V DS (V) 31

32 A PMOS Transistor Assume all variables negative! 0 x 10-4 VGS = -1.0V -0.2 VGS = -1.5V I D (A) VGS = -2.0V -0.8 VGS = -2.5V V DS (V) 32

33 Transistor Model for Manual Analysis 33

34 The Transistor as a Switch V GS V T S Ron I D D V GS = V DD R mid R 0 V DD /2 V DD V DS 34

35 The Transistor as a Switch 7 x R eq (Ohm) V DD (V) 35

36 The Transistor as a Switch 36

37 he Sub-Micron MOS Transistor Threshold Variations Subthreshold Conduction Parasitic Resistances 37

38 Threshold Variations V T V T Long-channel threshold Low V DS threshold Threshold as a function of the length (for low V DS ) L V DS Drain-induced barrier lowering (for low L) 38

39 Sub-Threshold Conduction Linear The Slope Factor I D ~ I 0 e qv nkt GS, n =1+ C C D ox I D (A) Quadratic S is V GS for I D2 /I D1 = Exponential V T V GS (V) Typical values for S: mv/decade 39

40 Sub-Threshold I D vs VGS qvgs nkt I D I0e 1 e qv = kt DS V DS from 0 to 0.5V 40

41 Sub-Threshold I D vs VDS I D qvgs qv = nkt kt I e 0 1 e DS ( 1+ λ V ) DS V GS from 0 to 0.3V 41

42 Summary of MOSFET Operating Regions Strong Inversion V GS >V T Linear (Resistive) V DS <V DSAT Saturated (Constant Current) V DS V DSAT Weak Inversion (Sub-Threshold) V GS V T Exponential in V GS with linear V DS dependence 42

43 Parasitic Resistances G Polysilicon gate L D Drain contact V GS,eff S D W R S R D Drain 43

44 Latch-up 44

45 Future Perspectives 25 nm FINFET MOS transistor 45