Nanoscale CMOS Design Issues

Transcription

1 Nanoscale CMOS Design Issues Jaydeep P. Kulkarni Assistant Professor, ECE Department The University of Texas at Austin Fall, 2017, VLSI-1 Class

2 Transistor I-V Review Agenda Non-ideal Transistor Behavior Velocity Saturation Channel Length Modulation Body Effect Leakage Temperature Sensitivity Process and Environmental Variations Process Corners 6T SRAM scaling challenges and design techniques Summary University of Texas, Austin Jaydeep P. Kulkarni 2

3 Ideal Transistor I-V 0 Vgs Vt cutoff V I ds ds Vgs V t V linear 2 ds Vds Vdsat V 2 gs Vt Vds Vdsat saturation 2 Shockley 1 st order transistor models 180 nm TSMC process Ideal Models β = 155(W/L) ma/v 2 V t = 0.4 V V DD = 1.8 V University of Texas, Austin Jaydeep P. Kulkarni 3

4 Simulated nmos I-V Plot 180 nm TSMC process BSIM 3v3 SPICE models What differs? Less ON current No square law Current increases in saturation I ds (A) 250 V gs = V gs = 1.5 V gs = V gs = V gs = V ds University of Texas, Austin Jaydeep P. Kulkarni 4

5 Velocity Saturation We assumed carrier velocity is proportional to E-field v = μe lat = μv ds /L At high fields, this ceases to be true Carriers scatter off atoms Velocity reaches v sat Electrons: 6-10 x 10 6 cm/s Holes: 4-8 x 10 6 cm/s Better model sat sat / 2 μe lat v vsat μesat Elat 1 E sat 0 0 slope = E sat E lat 2E sat 3E sat University of Texas, Austin Jaydeep P. Kulkarni 5

6 Velocity saturation I-V Effects Ideal transistor ON current increases with V DD 2 W V V I C V V L 2 2 gs t ds ox gs t Velocity-saturated ON current increases with V DD I C W V V v ds ox gs t Real transistors are partially velocity saturated Approximate with α -power law model I ds V DD α 1 < α < 2 determined empirically 2 max 2 University of Texas, Austin Jaydeep P. Kulkarni 6

7 a-power Model 0 Vgs Vt cutoff Vds Ids Idsat Vds Vdsat linear Vdsat Idsat Vds Vdsat saturation I P V V 2 dsat c gs t a /2 V P V V dsat v gs t a I ds (A) 400 Simulated a-law Shockley V gs = 1.8 V gs = 1.5 V gs = 1.2 V gs = 0.9 V gs = 0.6 V ds University of Texas, Austin Jaydeep P. Kulkarni 7

8 Channel Length Modulation Reverse-biased p-n junctions form a depletion region Region between n and p with no carriers Width of depletion L d region grows with reverse bias L eff = L L d Shorter L eff gives more current I ds increases with V ds Even in saturation GND Source V DD Gate V DD Drain Depletion Region Width: L d n+ L L eff n+ p GND bulk Si University of Texas, Austin Jaydeep P. Kulkarni 8

9 Channel Length Modulation I-V I ds (A) 400 I V V lv ds gs t ds l = channel length modulation coefficient not feature size Empirically fit to I-V characteristics V gs = 1.2 V gs = 1.8 V gs = 1.5 V gs = 0.9 V gs = V ds λ calculated by substituting I DS = 0, and finding the 1/V DS X- intercept University of Texas, Austin Jaydeep P. Kulkarni 9

10 Body Effect V t : gate voltage necessary to invert channel Increases if source voltage increases because source is connected to the channel Increase in V t with V s is called the body effect University of Texas, Austin Jaydeep P. Kulkarni 10

11 Body Effect Model V V g f V f t t0 s sb s f s = surface potential at threshold N A fs 2vT ln n i Depends on doping level N A And intrinsic carrier concentration n i g = body effect coefficient g t ox ox 2q N si A 2q N C si ox A University of Texas, Austin Jaydeep P. Kulkarni 11

12 OFF Transistor Behavior What about current in cutoff? Simulated results don t match measurements What differs? Current doesn t go to 0 in cutoff I ds 1 ma 100 A 10 A 1 A 100 na 10 na 1 na 100 pa 10 pa Subthreshold Region Subthreshold Slope V t Saturation Region V ds = 1.8 Sub-threshold region very attractive for low voltage operation but process variation sensitive V gs University of Texas, Austin Jaydeep P. Kulkarni 12

13 Leakage Sources Subthreshold conduction Transistors can t abruptly turn ON or OFF Junction leakage Reverse-biased PN junction diode current Gate leakage Tunneling through ultrathin gate dielectric Subthreshold leakage is the biggest source in modern transistors University of Texas, Austin Jaydeep P. Kulkarni 13

14 Subthreshold Leakage Subthreshold leakage exponential with V gs I ds I ds e nvt 1 e 0 V V V v gs t ds T ds0 vte η is process dependent, typically , increases with temp. Subthreshold Swing: inverse of sub-threshold slope MOSFETs: Minimum S.S. limit is 60mV/Decade I 1 ma 100 A 10 A 1 A 100 na 10 na 1 na 100 pa 10 pa I ds Subthreshold Region Subthreshold Slope V t Saturation Region V ds = Higher S.S. slope translates to higher OFF state leakage, lower I ON /I OFF Quest to develop Steep sub-threshold slope transistors (e.g. Tunnel FETs) V gs University of Texas, Austin Jaydeep P. Kulkarni 14

15 DIBL (Drain Induced Barrier Lowering) Drain-Induced Barrier Lowering Drain voltage lowers V t V t Vt V ds High drain voltage causes subthreshold leakage to increase. DIBL due to increase in depletion region width near the drain junction with drain voltage increase DIBL is quantified in terms of mv of change in V T for 1V change in V DS. Although unitless, it is typically measured as mv/v University of Texas, Austin Jaydeep P. Kulkarni 15

16 Junction Leakage Reverse-biased p-n junctions have some leakage VD T I e v D I S 1 I s depends on doping levels And area and perimeter of diffusion regions Typically < 1 fa/m 2 p+ n+ n+ p+ p+ n+ p substrate n well University of Texas, Austin Jaydeep P. Kulkarni 16

17 Gate Leakage Carriers may tunnel thorough very thin gate oxides Predicted tunneling current (from [Song01]) Negligible for older processes Critically important for advanced process nodes 10 9 t ox JG (A/cm 2 ) V DD trend 0.6 nm 0.8 nm 1.0 nm 1.2 nm 1.5 nm 1.9 nm V DD Source: Intel University of Texas, Austin Jaydeep P. Kulkarni 17

18 Temperature Dependence Linear region current ZTC Saturation region current ITD Effect of temperature on mobility and threshold voltage Ring oscillator frequency variation Ref: M. Cho, CICC, 2012 Elevated temperature reduces both mobility and threshold voltage At high Vcc, Vt change has less impact on gate overdrive, so mobility degradation dominates lower current with temperature increase (in relatively old technology) At lower Vcc, Vt reduction increases (Vgs-Vt) term more than the mobility degradation higher current with temperature increase (known as Inverse Temperature Dependence) University of Texas, Austin Jaydeep P. Kulkarni 18

19 pmos slow fast Process Variations Transistors have uncertainty in parameters Process: L eff, V t, t ox of nmos and pmos Vary around typical (T) values Fast (F) L eff : short V t : low t ox : thin SF SS TT FF FS Slow (S): opposite Not all parameters are independent slow nmos fast for nmos and pmos University of Texas, Austin Jaydeep P. Kulkarni 19

20 Environmental Variation V DD and T also vary in time and space Fast: V DD : high T: low Corner Voltage Temperature F C T C S C University of Texas, Austin Jaydeep P. Kulkarni 20

21 Important Corners Some critical simulation corners include Purpose nmos pmos V DD Temp Cycle time S S S S Power F F F F Subthrehold leakage F F F S University of Texas, Austin Jaydeep P. Kulkarni 21

22 What is the effect of non-ideal transistor behavior in real life designs? University of Texas, Austin Jaydeep P. Kulkarni 22

23 A case study: Advanced SRAM 75% of the die area occupied by SRAMs Key enabler for logic technology scaling Ref: Springer Book on Nanometer Variation Tolerant SRAM Intel EX Xeon server processor (E7 V3): 18 Cores in 22nm technology 5.6 Billion transistors 45 Mega Bytes of L3 cache 45*8*6*1024*1024 = 2.26 Billion transistors to realize 6T SRAM bitcells Ref: ~40% total transistors in just L3 bit cells University of Texas, Austin Jaydeep P. Kulkarni 23

24 6T SRAM bitcell scaling Innovation in both process technology and circuit techniques University of Texas, Austin Jaydeep P. Kulkarni 24

25 6T SRAM density scaling 1.8X every process generation including assist circuits for Vmin and leakage reduction University of Texas, Austin Jaydeep P. Kulkarni 25

26 6T SRAM V T variation and Vmin window Conflicting read vs. write design requirements in 6T SRAM Shrinking VT optimization window with process scaling University of Texas, Austin Jaydeep P. Kulkarni 26

27 Source of variations University of Texas, Austin Jaydeep P. Kulkarni 27

28 Random process variations University of Texas, Austin Jaydeep P. Kulkarni 28

29 6T SRAM Vmin SRAM Vmin distribution affected by global systematic and local random variations. University of Texas, Austin Jaydeep P. Kulkarni 29

30 6T SRAM design trade-offs University of Texas, Austin Jaydeep P. Kulkarni 30

31 6T SRAM read and write margin University of Texas, Austin Jaydeep P. Kulkarni 31

32 Read vs. write stability University of Texas, Austin Jaydeep P. Kulkarni 32

33 Restricted design rules University of Texas, Austin Jaydeep P. Kulkarni 33

34 Read stability assist techniques University of Texas, Austin Jaydeep P. Kulkarni 34

35 Read stability bitline voltage tuning University of Texas, Austin Jaydeep P. Kulkarni 35

36 Strong PMOS affects write-ability University of Texas, Austin Jaydeep P. Kulkarni 36

37 Write-assist techniques Effectiveness of circuit write assist technique depends on transistor technology and SRAM application University of Texas, Austin Jaydeep P. Kulkarni 37

38 Write assist lowering the supply voltage University of Texas, Austin Jaydeep P. Kulkarni 38

39 Transient Voltage Collapse University of Texas, Austin Jaydeep P. Kulkarni 39

40 Other considerations in advanced SRAMs University of Texas, Austin Jaydeep P. Kulkarni 40

41 Summary: Nano-scale CMOS design issues Non-ideal Transistor Behavior Velocity saturation: alpha power model Channel length modulation : I DS increases with V DS in saturation Body Effect: V t increases with body bias DIBL: V t lowers due to V DS increase Leakage: Subthreshold current dominates, 60mV/decade Gate leakage: High-K gate dielectrics Temperature sensitivity: depends on Vcc, μ, and Vt dependance Case study: Advanced nano-scale SRAMs Impact of process variations Vmin read/write failure mechanisms Overview of read and write assist techniques Considerations for energy efficient memory designs University of Texas, Austin Jaydeep P. Kulkarni 41