CMOS INVERTER. Last Lecture. Metrics for qualifying digital circuits. »Cost» Reliability» Speed (delay)»performance


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1 CMOS INVERTER Last Lecture Metrics for qualifying digital circuits»cost» Reliability» Speed (delay)»performance 1
2 Today s lecture The CMOS inverter at a glance An MOS transistor model for manual analysis The VTC of the CMOS inverter The CMOS Inverter: A First Glance V DD V in V out C L 2
3 CMOS Inverters PMOS V DD In Out 2λ Metal1 Polysilicon NMOS GND Switch Model of CMOS Transistor V GS R on V GS < V T V GS > V T 3
4 CMOS Inverter: Steady State Response V DD V DD R on V OH =V DD V out V out V OL =0 R on V M = f(r onn, R onp ) V in =V DD V in =0 CMOS Inverter: Transient Response V DD t phl = f(r on.c L ) =0.69R on C L V out V out ln(0.5) R on C L 1 V DD V in =V DD R on C L t 4
5 CMOS Properties Full railtorail swing Symmetrical VTC Propagation delay function of load capacitance and resistance of transistors No static power dissipation Direct path current during switching The MOS Transistor Polysilicon Aluminum 5
6 MOS Transistors  Types and Symbols D D G G S NMOS Enhancement D S NMOS Depletion D G G B PMOS Enhancement S S NMOS with Bulk Contact Threshold Voltage: Concept S + V GS  G D n+ n+ nchannel psubstrate Depletion Region B 6
7 The Threshold Voltage The Body Effect V T (V) V (V) BS 7
8 CurrentVoltage Relations A good ol transistor 6 x 104 VGS= 2.5 V I D (A) Resistive Saturation VGS= 2.0 V V DS =V GS V T VGS= 1.5 V Quadratic Relationship 1 VGS= 1.0 V V DS (V) Transistor in Linear S V GS G V DS D I D n + V(x) + n + L x psubstrate B MOS transistor and its bias conditions 8
9 Transistor in Saturation V GS G V DS >V GS V T S D n+  V GS V T + n+ Pinchoff CurrentVoltage Relations LongChannel Device 9
10 A model for manual analysis CurrentVoltage Relations The DeepSubmicron Era x 10 2 Early Saturation VGS= 2.5 V I D (A) VGS= 2.0 V VGS= 1.5 V Linear Relationship 0.5 VGS= 1.0 V V DS (V) 10
11 Velocity Saturation υ n (m/s) υ sat = 10 5 Constant velocity Constant mobility (slope = µ) ξ c = 1.5 ξ (V/µm) Perspective I D Longchannel device V GS = V DD Shortchannel device V DSAT V GS V T V DS 11
12 I D versus V GS 6 x x quadratic linear ID (A) 3 I D (A) V GS (V) Long Channel 0.5 quadratic V GS (V) Short Channel A unified model for manual analysis G S D B 12
13 Simple Model versus SPICE 4 x V DS =V DSAT I D (A) Linear Velocity Saturated 0.5 V DSAT =V GT V DS =V GT Saturated V DS (V) APMOSTransistor 0 x 104 VGS = 1.0V 0.2 VGS = 1.5V 0.4 I D (A) 0.6 VGS = 2.0V Assume all variables negative! 0.8 VGS = 2.5V V DS (V) 13
14 Transistor Model for Manual Analysis The Transistor as a Switch V GS V T S Ron I D D V GS =V DD R mid R 0 V DD /2 V DD V DS 14
15 The Transistor as a Switch 7 x R eq (Ohm) V (V) DD The Transistor as a Switch 15
16 The SubMicron MOS Transistor Threshold Variations Subthreshold Conduction Parasitic Resistances Latchup Threshold Variations V T V T Longchannel threshold Low V DS threshold Threshold as a function of the length (for low V DS ) L V DS Draininduced barrier lowering (for low L) 16
17 SubThreshold Conduction Linear I D (A) Quadratic The Slope Factor Exponential Typical values for S: mv/decade V T V GS (V) Parasitic Resistances G Polysilicon gate L D Drain contact V GS,eff S D W R S R D Drain 17
18 Future Perspectives 25 nm MOS transistor (Folded Channel) Voltage Transfer Characteristic 18
19 PMOS Load Lines V in =V DD V GSp I Dn =I Dp V out =V DD V DSp I Dn V out I Dp V in =0 I Dn I Dn V in =0 V in =3 V in =3 V GSp =2 V DSp V DSp V out V GSp =5 V in =V DD V GSp I Dn =I Dp V out =V DD V DSp CMOS Inverter Load Characteristics PMOS I n,p V V in =5 in =0 NMOS V in =4 V in =1 V in =4 V in =3 V in =2 V in =3 V in =2 V in =4 V in =5 V in =3 V in =2 V in =1 V in =0 19
20 CMOS Inverter VTC V out NMOS off PMOS lin NMOS sat PMOS lin NMOS sat PMOS sat NMOS lin PMOS sat NMOS lin PMOS off V in Simulated VTC 4.0 V out (V) V in (V) 20
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