Digital Integrated Circuits


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1 Chapter 6 The CMOS Inverter 1
2 Contents Introduction (MOST models) 0, 1 st, 2 nd order The CMOS inverter : The static behavior: o DC transfer characteristics, o Shortcircuit current The CMOS inverter : The dynamic behavior Energy, power, and energy delay 2
3 Introduction  1 Zeroorder model (ideal switch) of n and pchannel MOSFETs What for a signal between 0 and 1? Inverter Source: Weste & Harris 3
4 Introduction  2 Firstorder model of a MOSFET Non ideal switch An MOS Transistor V GS V T S Ron D V GS What s the value of R on? Abrupt transition from on to off? 4
5 Introduction  3 The MOS Transistor Polysilicon Aluminum 5
6 Introduction  4 MOS Transistors n and pchannel D D G G B In general connected to GND S NMOS S Enhancement D G G B In general connected to S PMOS Enhancement 6
7 Introduction  5 IV Relations Longchannel nmost 6 x 104 VGS= 2.5 V G D I D I D (A) Resistive Saturation VGS= 2.0 V V DS = V GS V T S 2 VGS= 1.5 V 1 VGS= 1.0 V VGS< 0.5 V V DS (V) 7
8 Introduction  6 IV Relations Longchannel pmost 6 x VGS= 2.5 V S 4 Resistive Saturation VGS= 2.0 V G I D (A) 3 I D V DS = V GS V T D 2 VGS= 1.5 V 1 VGS= 1.0 V VGS> 0.5 V V DS (V) 8
9 Introduction  7 9
10 Introduction  8 I D versus V GS Saturation mode: V DS >V GS V T 6 x V DS =2.5 V V T = 0.5 V constant I D (A) 4 3 quadratic V GS (V) 10
11 Introduction 9 Experimental setup  V GS S G 2 B I D 1  V DS VDD = 3.3 V [0,3.3] step 0,5 V  D 3 + [0,3.3] step 0,050 V  11
12 Introduction 9 An experiment Circuit description (SPICE) ment/pmosa.cir Steps ment/roteiro.txt 12
13 Introduction 10 Simulation 6.1a lambda = 0.1 V GS =3.3 V V GS =2.8 V V GS =2.3 V V GS =1.8 V V GS =1.3 V 13
14 Introduction  12 The Transistor as a Switch I D V GS = V GS V T S Ron D I DSAT R mid R 0 1 Req R0 + R 2 ( ) mid /2 V DS KP W I V V 2 L ( ) 2 DSAT DD T 14
15 Introduction  13 CMOS static logic the beginning 15
16 Introduction  14 CMOS static logic the beginning 16
17 Introduction  15 CMOS device structure from Frank Wanlass's patent drawing. U. S. Patent Office. 17
18 Introduction  16 Schematic and layout 1 N Well PMOS 2λ PMOS Contacts In Out In Out Metal 1 NMOS Polysilicon NMOS GND 18
19 Introduction  17 Schematic and layout 2 19
20 Static characteristics  1 R p V in C L R n V in NMOS PMOS 0 OFF ON ON OFF V in = V in = 0 VGSn = VDD > VTn VGSn = 0 < VTn V = 0 > V V = V < V GSp Tp GSp DD Tp 0 20
21 Static characteristics  1 R p V in C L R n V in NMOS PMOS 0 OFF ON ON OFF V in = V in = 0 VGSn = VDD > VTn VGSn = 0 < VTn V = 0 > V V = V < V GSp Tp GSp DD Tp 0 21
22 Static characteristics  1 R p V in C L R n V in NMOS PMOS 0 OFF ON ON OFF V in = V in = 0 VGSn = VDD > VTn VGSn = 0 < VTn V = 0 > V V = V < V GSp Tp GSp DD Tp 0 22
23 Static characteristics  2 V in C L Voltage swing is equal to the supply voltage; Logic levels are not dependent upon the relative device sizes; In steady state there always exists a path with finite resistance between the output and either or ground; The input resistance ; No direct path exists between supply and ground rails under steadystate operating conditions (this is first order approx. and is far from reality in more advanced technologies) static power 0 23
24 Static characteristics PMOS Load Line I Dn V GSp +  V DSp V in = +V GSp I Dn =  I Dp V in I Dp + = +V DSp I Dn CL I Dp =2.5 V V in =0 I Dn I Dn V in =0 V in =1.5 V in =1.5 V GSp =1 V DSp V DSp 2.5 V GSp =2.5 V in = +V GSp I Dn =  I Dp = +V DSp 24
25 Static characteristics  4 VTC V in  V GSp + I Dp I Dn  V DSp + IDn Vin= 1.5 Vin= 2 Vin= 2.5 Vin= PMOS NMOS Vin= Vin= 1 Vin= 0.5 Vin= NMOS off PMOS res NMOS sat PMOS res NMOS sat PMOS sat NMOS res PMOS sat Vout NMOS res PMOS off V in 25
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