Lecture 4: DC & Transient Response

Size: px
Start display at page:

Download "Lecture 4: DC & Transient Response"

Transcription

1 Introduction to CMOS VLSI Design Lecture 4: DC & Transient Response David Harris Harvey Mudd College Spring 004

2 Outline DC Response Logic Levels and Noise Margins Transient Response Delay Estimation Slide

3 Activity 1) If the width of a transistor increases, the current will increase decrease not change ) If the length of a transistor increases, the current will increase decrease not change 3) If the supply voltage of a chip increases, the maximum transistor current will increase decrease not change 4) If the width of a transistor increases, its gate capacitance will increase decrease not change 5) If the length of a transistor increases, its gate capacitance will increase decrease not change 6) If the supply voltage of a chip increases, the gate capacitance of each transistor will increase decrease not change Slide 3

4 Activity 1) If the width of a transistor increases, the current will increase decrease not change ) If the length of a transistor increases, the current will increase decrease not change 3) If the supply voltage of a chip increases, the maximum transistor current will increase decrease not change 4) If the width of a transistor increases, its gate capacitance will increase decrease not change 5) If the length of a transistor increases, its gate capacitance will increase decrease not change 6) If the supply voltage of a chip increases, the gate capacitance of each transistor will increase decrease not change Slide 4

5 DC Response DC Response: vs. V in for a gate Ex: Inverter When V in = 0 -> = When V in = -> = 0 In between, depends on transistor size and current By KCL, must settle such that I dsn = I dsp We could solve equations V in But graphical solution gives more insight I dsp I dsn Slide 5

6 Transistor Operation Current depends on region of transistor behavior For what V in and are nmos and pmos in Cutoff? Linear? Saturation? Slide 6

7 nmos Operation Cutoff V gsn < Linear V gsn > V dsn < Saturated V gsn > V dsn > V in I dsp I dsn Slide 7

8 nmos Operation Cutoff V gsn < V tn Linear V gsn > V tn Saturated V gsn > V tn V dsn < V gsn V tn V dsn > V gsn V tn V in I dsp I dsn Slide 8

9 nmos Operation Cutoff V gsn < V tn Linear V gsn > V tn Saturated V gsn > V tn V dsn < V gsn V tn V dsn > V gsn V tn V gsn = V in V dsn = V in I dsp I dsn Slide 9

10 nmos Operation Cutoff V gsn < V tn V in < V tn Linear V gsn > V tn V in > V tn V dsn < V gsn V tn < V in - V tn Saturated V gsn > V tn V in > V tn V dsn > V gsn V tn > V in - V tn V gsn = V in V dsn = V in I dsp I dsn Slide 10

11 pmos Operation Cutoff V gsp > Linear V gsp < V dsp > Saturated V gsp < V dsp < V in I dsp I dsn Slide 11

12 pmos Operation Cutoff V gsp > V tp Linear V gsp < V tp Saturated V gsp < V tp V dsp > V gsp V tp V dsp < V gsp V tp V in I dsp I dsn Slide 1

13 pmos Operation Cutoff V gsp > V tp Linear V gsp < V tp Saturated V gsp < V tp V dsp > V gsp V tp V dsp < V gsp V tp V gsp = V in - V dsp = - V tp < 0 V in I dsp I dsn Slide 13

14 pmos Operation Cutoff V gsp > V tp V in > + V tp Linear V gsp < V tp V in < + V tp V dsp > V gsp V tp > V in - V tp Saturated V gsp < V tp V in < + V tp V dsp < V gsp V tp < V in - V tp V gsp = V in - V dsp = - V tp < 0 V in I dsp I dsn Slide 14

15 I-V Characteristics Make pmos is wider than nmos such that β n = β p V gsn5 I dsn V gsn4 V gsn3 -V dsp V gsp1 V gsp - 0 V gsn V gsn1 V gsp3 V dsn V gsp4 -I dsp V gsp5 Slide 15

16 Current vs., V in V in0 V in5 I dsn, I dsp V in1 V in4 V in V in3 V in3 V in4 V in V in1 Slide 16

17 Load Line Analysis For a given V in : Plot I dsn, I dsp vs. must be where currents are equal in V in0 V in5 I dsn, I dsp V in1 V in4 V in V in3 I dsp V in3 V in4 V in V in1 V in I dsn Slide 17

18 Load Line Analysis V in = 0 V in0 I dsn, I dsp V in0 Slide 18

19 Load Line Analysis V in = 0. I dsn, I dsp V in1 V in1 Slide 19

20 Load Line Analysis V in = 0.4 I dsn, I dsp V in V in Slide 0

21 Load Line Analysis V in = 0.6 I dsn, I dsp V in3 V in3 Slide 1

22 Load Line Analysis V in = 0.8 I dsn, I dsp V in4 V in4 Slide

23 Load Line Analysis V in = V in0 V in5 I dsn, I dsp V in1 V in V in3 V in4 Slide 3

24 Load Line Summary V in0 V in5 I dsn, I dsp V in1 V in4 V in V in3 V in3 V in4 V in V in1 Slide 4

25 DC Transfer Curve Transcribe points onto V in vs. plot A B V in0 V in5 V in1 V in4 C V in V in3 V in3 V in4 V in V in1 0 D E V tn / +V tp V in Slide 5

26 Operating Regions Revisit transistor operating regions Region nmos pmos A B A B C C D E 0 D E V tn / +V tp V in Slide 6

27 Operating Regions Revisit transistor operating regions Region nmos pmos A B A Cutoff Linear B C Saturation Saturation Linear Saturation C D E Linear Linear Saturation Cutoff 0 D E V tn / +V tp V in Slide 7

28 Beta Ratio If β p / β n 1, switching point will move from / Called skewed gate Other gates: collapse into equivalent inverter β p 0.1 β = n β p 10 β = n V in Slide 8

29 Noise Margins How much noise can a gate input see before it does not recognize the input? Logical High Output Range Output Characteristics V OH NM H Input Characteristics Logical High Input Range V IH V IL Indeterminate Region Logical Low Output Range V OL NM L GND Logical Low Input Range Slide 9

30 Logic Levels To maximize noise margins, select logic levels at β p /β n > 1 V in 0 V in Slide 30

31 Logic Levels To maximize noise margins, select logic levels at unity gain point of DC transfer characteristic Unity Gain Points Slope = -1 V OH β p /β n > 1 V in V OL 0 V tn V IL V IH - V tp V in Slide 31

32 Transient Response DC analysis tells us if V in is constant Transient analysis tells us (t) if V in (t) changes Requires solving differential equations Input is usually considered to be a step or ramp From 0 to or vice versa Slide 3

33 Inverter Step Response Ex: find step response of inverter driving load cap V in ( t) V ( t < t ) = out dv out dt = ( t) 0 = V in (t) I dsn (t) (t) C load Slide 33

34 Inverter Step Response Ex: find step response of inverter driving load cap V V in out dv () t ( t< t ) out dt = () t ut ( t ) V 0 = = 0 DD V in (t) I dsn (t) (t) C load Slide 34

35 Inverter Step Response Ex: find step response of inverter driving load cap V V in out dv ( t) ( t ot u dt = ut ( t ) V < ( t) t 0 ) = 0 = V DD DD V in (t) I dsn (t) (t) C load Slide 35

36 Inverter Step Response Ex: find step response of inverter driving load cap V V in out dv () t = ut ( ( t< t ) out dt ( t) 0 = t ) V 0 = V I DD dsn C DD () t load V in (t) I dsn (t) (t) C load t t I t V V V < V V 0 dsn () = Vout > DD t out DD t Slide 36

37 Inverter Step Response I Ex: find step response of inverter driving load cap V V in out dv () t = ut ( ( t< t ) out dt ( t) 0 = t ) V 0 = V I DD dsn C 0 DD () t load ( ) β dsn ( t) = VDD V Vout > VDD Vt Vout ( t) β VDD V t V () t V < V D V out out D t t t 0 V in (t) I dsn (t) (t) C load Slide 37

38 Inverter Step Response I Ex: find step response of inverter driving load cap V V in out dv () t = ut ( ( t< t ) out dt ( t) 0 = t ) V 0 = V I DD dsn C 0 DD () t load ( ) β dsn ( t) = VDD V Vout > VDD Vt Vout ( t) β VDD V t V () t V < V D V out out D t t t 0 V in (t) t 0 I dsn (t) V in (t) (t) (t) C load t Slide 38

39 Delay Definitions t pdr : t pdf : t pd : t r : t f : fall time Slide 39

40 Delay Definitions t pdr : rising propagation delay From input to rising output crossing / t pdf : falling propagation delay From input to falling output crossing / t pd : average propagation delay t pd = (t pdr + t pdf )/ t r : rise time From output crossing 0. to 0.8 t f : fall time From output crossing 0.8 to 0. Slide 40

41 Delay Definitions t cdr : rising contamination delay From input to rising output crossing / t cdf : falling contamination delay From input to falling output crossing / t cd : average contamination delay t pd = (t cdr + t cdf )/ Slide 41

42 Simulated Inverter Delay Solving differential equations by hand is too hard SPICE simulator solves the equations numerically Uses more accurate I-V models too! But simulations take time to write (V) V in t pdf = 66ps t pdr = 83ps p 400p 600p 800p 1n t(s) Slide 4

43 Delay Estimation We would like to be able to easily estimate delay Not as accurate as simulation But easier to ask What if? The step response usually looks like a 1 st order RC response with a decaying exponential. Use RC delay models to estimate delay C = total capacitance on output node Use effective resistance R So that t pd = RC Characterize transistors by finding their effective R Depends on average current as gate switches Slide 43

44 RC Delay Models Use equivalent circuits for MOS transistors Ideal switch + capacitance and ON resistance Unit nmos has resistance R, capacitance C Unit pmos has resistance R, capacitance C Capacitance proportional to width Resistance inversely proportional to width g d k s g R/k kc d s kc kc Slide 44 g d k s g kc s d R/k kc kc

45 Example: 3-input NAND Sketch a 3-input NAND with transistor widths chosen to achieve effective rise and fall resistances equal to a unit inverter (R). Slide 45

46 Example: 3-input NAND Sketch a 3-input NAND with transistor widths chosen to achieve effective rise and fall resistances equal to a unit inverter (R). Slide 46

47 Example: 3-input NAND Sketch a 3-input NAND with transistor widths chosen to achieve effective rise and fall resistances equal to a unit inverter (R) Slide 47

48 3-input NAND Caps Annotate the 3-input NAND gate with gate and diffusion capacitance Slide 48

49 3-input NAND Caps Annotate the 3-input NAND gate with gate and diffusion capacitance. C C C C C C C C C 3C 3C 3C C 3C 3C 3C Slide 49

50 3-input NAND Caps Annotate the 3-input NAND gate with gate and diffusion capacitance. 5C 5C 5C C 3C 3C Slide 50

51 Elmore Delay ON transistors look like resistors Pullup or pulldown network modeled as RC ladder Elmore delay of RC ladder t R C pd i to source i nodes i = RC + R + R C R + R R C ( ) ( ) R 1 R R 3 R N N N C 1 C C 3 C N Slide 51

52 Example: -input NAND Estimate worst-case rising and falling delay of - input NAND driving h identical gates. A B x Y h copies Slide 5

53 Example: -input NAND Estimate rising and falling propagation delays of a - input NAND driving h identical gates. A B x 6C C Y 4hC h copies Slide 53

54 Example: -input NAND Estimate rising and falling propagation delays of a - input NAND driving h identical gates. A B x 6C C Y 4hC h copies R Y (6+4h)C t pdr = Slide 54

55 Example: -input NAND Estimate rising and falling propagation delays of a - input NAND driving h identical gates. A B x 6C C Y 4hC h copies R Y ( ) (6+4h)C t pdr = 6+ 4h RC Slide 55

56 Example: -input NAND Estimate rising and falling propagation delays of a - input NAND driving h identical gates. A B x 6C C Y 4hC h copies Slide 56

57 Example: -input NAND Estimate rising and falling propagation delays of a - input NAND driving h identical gates. A B x 6C C Y 4hC h copies R/ x R/ C Y (6+4h)C t pdf = Slide 57

58 Example: -input NAND Estimate rising and falling propagation delays of a - input NAND driving h identical gates. A B x 6C C Y 4hC h copies R/ x R/ C Y (6+4h)C tpdf = C + + h C + = 7+ 4h RC ( )( R ) ( 6 4 ) ( R R ) ( ) Slide 58

59 Delay Components Delay has two parts Parasitic delay 6 or 7 RC Independent of load Effort delay 4h RC Proportional to load capacitance Slide 59

60 Contamination Delay Best-case (contamination) delay can be substantially less than propagation delay. Ex: If both inputs fall simultaneously A B x 6C C Y 4hC R R Y (6+4h)C tcdr = 3+ h RC ( ) Slide 60

61 Diffusion Capacitance we assumed contacted diffusion on every s / d. Good layout minimizes diffusion area Ex: NAND3 layout shares one diffusion contact Reduces output capacitance by C Merged uncontacted diffusion might help too Shared Contacted Diffusion Merged Uncontacted Diffusion C C Isolated Contacted Diffusion 3 3 7C 3C 3C 3C 3C 3 3C Slide 61

62 Layout Comparison Which layout is better? A B A B Y Y GND GND Slide 6

Lecture 5: DC & Transient Response

Lecture 5: DC & Transient Response Lecture 5: DC & Transient Response Outline q Pass Transistors q DC Response q Logic Levels and Noise Margins q Transient Response q RC Delay Models q Delay Estimation 2 Activity 1) If the width of a transistor

More information

Lecture 6: DC & Transient Response

Lecture 6: DC & Transient Response Lecture 6: DC & Transient Response Slides courtesy of Deming Chen Slides based on the initial set from David Harris CMOS VLSI Design Outline Pass Transistors DC Response Logic Levels and Noise Margins

More information

EE5780 Advanced VLSI CAD

EE5780 Advanced VLSI CAD EE5780 Advanced VLSI CAD Lecture 4 DC and Transient Responses, Circuit Delays Zhuo Feng 4.1 Outline Pass Transistors DC Response Logic Levels and Noise Margins Transient Response RC Delay Models Delay

More information

Lecture 5: DC & Transient Response

Lecture 5: DC & Transient Response Lecture 5: DC & Transient Response Outline Pass Transistors DC Response Logic Levels and Noise Margins Transient Response RC Delay Models Delay Estimation 2 Pass Transistors We have assumed source is grounded

More information

5. CMOS Gate Characteristics CS755

5. CMOS Gate Characteristics CS755 5. CMOS Gate Characteristics Last module: CMOS Transistor theory This module: DC Response Logic Levels and Noise Margins Transient Response Delay Estimation Transistor ehavior 1) If the width of a transistor

More information

DC and Transient. Courtesy of Dr. Daehyun Dr. Dr. Shmuel and Dr.

DC and Transient. Courtesy of Dr. Daehyun Dr. Dr. Shmuel and Dr. DC and Transient Courtesy of Dr. Daehyun Lim@WSU, Dr. Harris@HMC, Dr. Shmuel Wimer@BIU and Dr. Choi@PSU http://csce.uark.edu +1 (479) 575-604 yrpeng@uark.edu Pass Transistors We have assumed source is

More information

EEE 421 VLSI Circuits

EEE 421 VLSI Circuits EEE 421 CMOS Properties Full rail-to-rail swing high noise margins» Logic levels not dependent upon the relative device sizes transistors can be minimum size ratioless Always a path to V dd or GND in steady

More information

DC & Transient Responses

DC & Transient Responses ECEN454 Digital Integrated Circuit Design DC & Transient Responses ECEN 454 DC Response DC Response: vs. for a gate Ex: Inverter When = -> = When = -> = In between, depends on transistor size and current

More information

CPE/EE 427, CPE 527 VLSI Design I Delay Estimation. Department of Electrical and Computer Engineering University of Alabama in Huntsville

CPE/EE 427, CPE 527 VLSI Design I Delay Estimation. Department of Electrical and Computer Engineering University of Alabama in Huntsville CPE/EE 47, CPE 57 VLSI Design I Delay Estimation Department of Electrical and Computer Engineering University of labama in Huntsville leksandar Milenkovic ( www.ece.uah.edu/~milenka ) Review: CMOS Circuit

More information

DC and Transient Responses (i.e. delay) (some comments on power too!)

DC and Transient Responses (i.e. delay) (some comments on power too!) DC and Transient Responses (i.e. delay) (some comments on power too!) Michael Niemier (Some slides based on lecture notes by David Harris) 1 Lecture 02 - CMOS Transistor Theory & the Effects of Scaling

More information

Lecture 12 CMOS Delay & Transient Response

Lecture 12 CMOS Delay & Transient Response EE 471: Transport Phenomena in Solid State Devices Spring 2018 Lecture 12 CMOS Delay & Transient Response Bryan Ackland Department of Electrical and Computer Engineering Stevens Institute of Technology

More information

MOS Transistor Theory

MOS Transistor Theory MOS Transistor Theory So far, we have viewed a MOS transistor as an ideal switch (digital operation) Reality: less than ideal EE 261 Krish Chakrabarty 1 Introduction So far, we have treated transistors

More information

Outline. Chapter 2: DC & Transient Response. Introduction to CMOS VLSI. DC Response. Transient Response Delay Estimation

Outline. Chapter 2: DC & Transient Response. Introduction to CMOS VLSI. DC Response. Transient Response Delay Estimation Inroducion o CMOS VLSI Design Chaper : DC & Transien Response David Harris, 004 Updaed by Li Chen, 010 Ouline DC Response Logic Levels and Noise Margins Transien Response Delay Esimaion Slide 1 Aciviy

More information

Topic 4. The CMOS Inverter

Topic 4. The CMOS Inverter Topic 4 The CMOS Inverter Peter Cheung Department of Electrical & Electronic Engineering Imperial College London URL: www.ee.ic.ac.uk/pcheung/ E-mail: p.cheung@ic.ac.uk Topic 4-1 Noise in Digital Integrated

More information

MOS Transistor Theory

MOS Transistor Theory CHAPTER 3 MOS Transistor Theory Outline 2 1. Introduction 2. Ideal I-V Characteristics 3. Nonideal I-V Effects 4. C-V Characteristics 5. DC Transfer Characteristics 6. Switch-level RC Delay Models MOS

More information

CMPEN 411 VLSI Digital Circuits. Lecture 04: CMOS Inverter (static view)

CMPEN 411 VLSI Digital Circuits. Lecture 04: CMOS Inverter (static view) CMPEN 411 VLSI Digital Circuits Lecture 04: CMOS Inverter (static view) Kyusun Choi [Adapted from Rabaey s Digital Integrated Circuits, Second Edition, 2003 J. Rabaey, A. Chandrakasan, B. Nikolic] CMPEN

More information

Based on slides/material by. Topic 3-4. Combinational Logic. Outline. The CMOS Inverter: A First Glance

Based on slides/material by. Topic 3-4. Combinational Logic. Outline. The CMOS Inverter: A First Glance ased on slides/material by Topic 3 J. Rabaey http://bwrc.eecs.berkeley.edu/lasses/icook/instructors.html Digital Integrated ircuits: Design Perspective, Prentice Hall D. Harris http://www.cmosvlsi.com/coursematerials.html

More information

Very Large Scale Integration (VLSI)

Very Large Scale Integration (VLSI) Very Large Scale Integration (VLSI) Lecture 4 Dr. Ahmed H. Madian Ah_madian@hotmail.com Dr. Ahmed H. Madian-VLSI Contents Delay estimation Simple RC model Penfield-Rubenstein Model Logical effort Delay

More information

ENGR890 Digital VLSI Design Fall Lecture 4: CMOS Inverter (static view)

ENGR890 Digital VLSI Design Fall Lecture 4: CMOS Inverter (static view) ENGR89 Digital VLSI Design Fall 5 Lecture 4: CMOS Inverter (static view) [Adapted from Chapter 5 of Digital Integrated Circuits, 3, J. Rabaey et al.] [Also borrowed from Vijay Narayanan and Mary Jane Irwin]

More information

Delay and Power Estimation

Delay and Power Estimation EEN454 Digital Integrated ircuit Design Delay and Power Estimation EEN 454 Delay Estimation We would like to be able to easily estimate delay Not as accurate as simulation But make it easier to ask What

More information

ECE 342 Solid State Devices & Circuits 4. CMOS

ECE 342 Solid State Devices & Circuits 4. CMOS ECE 34 Solid State Devices & Circuits 4. CMOS Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jschutt@emlab.uiuc.edu ECE 34 Jose Schutt Aine 1 Digital Circuits V IH : Input

More information

Lecture 11 VTCs and Delay. No lab today, Mon., Tues. Labs restart next week. Midterm #1 Tues. Oct. 7 th, 6:30-8:00pm in 105 Northgate

Lecture 11 VTCs and Delay. No lab today, Mon., Tues. Labs restart next week. Midterm #1 Tues. Oct. 7 th, 6:30-8:00pm in 105 Northgate EE4-Fall 2008 Digital Integrated Circuits Lecture VTCs and Delay Lecture # Announcements No lab today, Mon., Tues. Labs restart next week Midterm # Tues. Oct. 7 th, 6:30-8:00pm in 05 Northgate Exam is

More information

EEC 118 Lecture #6: CMOS Logic. Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation

EEC 118 Lecture #6: CMOS Logic. Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation EEC 118 Lecture #6: CMOS Logic Rajeevan mirtharajah University of California, Davis Jeff Parkhurst Intel Corporation nnouncements Quiz 1 today! Lab 2 reports due this week Lab 3 this week HW 3 due this

More information

EEC 116 Lecture #5: CMOS Logic. Rajeevan Amirtharajah Bevan Baas University of California, Davis Jeff Parkhurst Intel Corporation

EEC 116 Lecture #5: CMOS Logic. Rajeevan Amirtharajah Bevan Baas University of California, Davis Jeff Parkhurst Intel Corporation EEC 116 Lecture #5: CMOS Logic Rajeevan mirtharajah Bevan Baas University of California, Davis Jeff Parkhurst Intel Corporation nnouncements Quiz 1 today! Lab 2 reports due this week Lab 3 this week HW

More information

Lecture 8: Combinational Circuits

Lecture 8: Combinational Circuits Introduction to CMOS VLSI Design Lecture 8: Combinational Circuits David Harris Harvey Mudd College Spring 004 Outline ubble Pushing Compound Gates Logical Effort Example Input Ordering symmetric Gates

More information

ECE 546 Lecture 10 MOS Transistors

ECE 546 Lecture 10 MOS Transistors ECE 546 Lecture 10 MOS Transistors Spring 2018 Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jesa@illinois.edu NMOS Transistor NMOS Transistor N-Channel MOSFET Built on p-type

More information

4.10 The CMOS Digital Logic Inverter

4.10 The CMOS Digital Logic Inverter 11/11/2004 section 4_10 The CMOS Digital Inverter blank.doc 1/1 4.10 The CMOS Digital Logic Inverter Reading Assignment: pp. 336346 Complementary MOSFET (CMOS) is the predominant technology for constructing

More information

THE INVERTER. Inverter

THE INVERTER. Inverter THE INVERTER DIGITAL GATES Fundamental Parameters Functionality Reliability, Robustness Area Performance» Speed (delay)» Power Consumption» Energy Noise in Digital Integrated Circuits v(t) V DD i(t) (a)

More information

Lecture 13 - Digital Circuits (II) MOS Inverter Circuits. March 20, 2003

Lecture 13 - Digital Circuits (II) MOS Inverter Circuits. March 20, 2003 6.012 Microelectronic Devices and Circuits Spring 2003 Lecture 131 Lecture 13 Digital Circuits (II) MOS Inverter Circuits March 20, 2003 Contents: 1. NMOS inverter with resistor pullup (cont.) 2. NMOS

More information

Integrated Circuits & Systems

Integrated Circuits & Systems Federal University of Santa Catarina Center for Technology Computer Science & Electronics Engineering Integrated Circuits & Systems INE 5442 Lecture 12 The CMOS Inverter: static behavior guntzel@inf.ufsc.br

More information

ECE321 Electronics I

ECE321 Electronics I ECE31 Electronics Lecture 1: CMOS nverter: Noise Margin & Delay Model Payman Zarkesh-Ha Office: ECE Bldg. 30B Office hours: Tuesday :00-3:00PM or by appointment E-mail: payman@ece.unm.edu Slide: 1 CMOS

More information

Lecture 12 Digital Circuits (II) MOS INVERTER CIRCUITS

Lecture 12 Digital Circuits (II) MOS INVERTER CIRCUITS Lecture 12 Digital Circuits (II) MOS INVERTER CIRCUITS Outline NMOS inverter with resistor pull-up The inverter NMOS inverter with current-source pull-up Complementary MOS (CMOS) inverter Static analysis

More information

Midterm. ESE 570: Digital Integrated Circuits and VLSI Fundamentals. Lecture Outline. Pass Transistor Logic. Restore Output.

Midterm. ESE 570: Digital Integrated Circuits and VLSI Fundamentals. Lecture Outline. Pass Transistor Logic. Restore Output. ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 16: March 21, 2017 Transmission Gates, Euler Paths, Energy Basics Review Midterm! Midterm " Mean: 79.5 " Standard Dev: 14.5 2 Lecture Outline!

More information

Lecture 12 Circuits numériques (II)

Lecture 12 Circuits numériques (II) Lecture 12 Circuits numériques (II) Circuits inverseurs MOS Outline NMOS inverter with resistor pull-up The inverter NMOS inverter with current-source pull-up Complementary MOS (CMOS) inverter Static analysis

More information

ESE 570: Digital Integrated Circuits and VLSI Fundamentals

ESE 570: Digital Integrated Circuits and VLSI Fundamentals ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 15: March 15, 2018 Euler Paths, Energy Basics and Optimization Midterm! Midterm " Mean: 89.7 " Standard Dev: 8.12 2 Lecture Outline! Euler

More information

Lecture Outline. ESE 570: Digital Integrated Circuits and VLSI Fundamentals. Review: 1st Order RC Delay Models. Review: Two-Input NOR Gate (NOR2)

Lecture Outline. ESE 570: Digital Integrated Circuits and VLSI Fundamentals. Review: 1st Order RC Delay Models. Review: Two-Input NOR Gate (NOR2) ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 14: March 1, 2016 Combination Logic: Ratioed and Pass Logic Lecture Outline! CMOS Gates Review " CMOS Worst Case Analysis! Ratioed Logic Gates!

More information

Lecture 14 - Digital Circuits (III) CMOS. April 1, 2003

Lecture 14 - Digital Circuits (III) CMOS. April 1, 2003 6.12 - Microelectronic Devices and Circuits - Spring 23 Lecture 14-1 Lecture 14 - Digital Circuits (III) CMOS April 1, 23 Contents: 1. Complementary MOS (CMOS) inverter: introduction 2. CMOS inverter:

More information

Digital Integrated Circuits

Digital Integrated Circuits Chapter 6 The CMOS Inverter 1 Contents Introduction (MOST models) 0, 1 st, 2 nd order The CMOS inverter : The static behavior: o DC transfer characteristics, o Short-circuit current The CMOS inverter :

More information

ESE 570: Digital Integrated Circuits and VLSI Fundamentals

ESE 570: Digital Integrated Circuits and VLSI Fundamentals ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 15: March 3, 2016 Combination Logic: Ratioed & Pass Logic, and Performance Lecture Outline! CMOS NOR2 Worst Case Analysis! Pass Transistor

More information

MOSFET and CMOS Gate. Copy Right by Wentai Liu

MOSFET and CMOS Gate. Copy Right by Wentai Liu MOSFET and CMOS Gate CMOS Inverter DC Analysis - Voltage Transfer Curve (VTC) Find (1) (2) (3) (4) (5) (6) V OH min, V V OL min, V V IH min, V V IL min, V OHmax OLmax IHmax ILmax NM L = V ILmax V OL max

More information

CMOS Inverter (static view)

CMOS Inverter (static view) Review: Design Abstraction Levels SYSTEM CMOS Inverter (static view) + MODULE GATE [Adapted from Chapter 5. 5.3 CIRCUIT of G DEVICE Rabaey s Digital Integrated Circuits,, J. Rabaey et al.] S D Review:

More information

Lecture 8: Combinational Circuits

Lecture 8: Combinational Circuits Introduction to CMOS VLSI Design Lecture 8: Combinational Circuits David Harris Harvey Mudd College Spring 00 Outline ubble Pushing Compound Gates Logical Effort Example Input Ordering symmetric Gates

More information

CHAPTER 15 CMOS DIGITAL LOGIC CIRCUITS

CHAPTER 15 CMOS DIGITAL LOGIC CIRCUITS CHAPTER 5 CMOS DIGITAL LOGIC CIRCUITS Chapter Outline 5. CMOS Logic Gate Circuits 5. Digital Logic Inverters 5.3 The CMOS Inverter 5.4 Dynamic Operation of the CMOS Inverter 5.5 Transistor Sizing 5.6 Power

More information

Static CMOS Circuits. Example 1

Static CMOS Circuits. Example 1 Static CMOS Circuits Conventional (ratio-less) static CMOS Covered so far Ratio-ed logic (depletion load, pseudo nmos) Pass transistor logic ECE 261 Krish Chakrabarty 1 Example 1 module mux(input s, d0,

More information

Lecture 7 Circuit Delay, Area and Power

Lecture 7 Circuit Delay, Area and Power Lecture 7 Circuit Delay, Area and Power lecture notes from S. Mitra Intro VLSI System course (EE271) Introduction to VLSI Systems 1 Circuits and Delay Introduction to VLSI Systems 2 Power, Delay and Area:

More information

VLSI Design and Simulation

VLSI Design and Simulation VLSI Design and Simulation CMOS Inverters Topics Inverter VTC Noise Margin Static Load Inverters CMOS Inverter First-Order DC Analysis R p V OL = 0 V OH = R n =0 = CMOS Inverter: Transient Response R p

More information

EE5311- Digital IC Design

EE5311- Digital IC Design EE5311- Digital IC Design Module 3 - The Inverter Janakiraman V Assistant Professor Department of Electrical Engineering Indian Institute of Technology Madras Chennai September 6, 2017 Janakiraman, IITM

More information

Lecture 4: CMOS Transistor Theory

Lecture 4: CMOS Transistor Theory Introduction to CMOS VLSI Design Lecture 4: CMOS Transistor Theory David Harris, Harvey Mudd College Kartik Mohanram and Steven Levitan University of Pittsburgh Outline q Introduction q MOS Capacitor q

More information

Fig. 1 CMOS Transistor Circuits (a) Inverter Out = NOT In, (b) NOR-gate C = NOT (A or B)

Fig. 1 CMOS Transistor Circuits (a) Inverter Out = NOT In, (b) NOR-gate C = NOT (A or B) 1 Introduction to Transistor-Level Logic Circuits 1 By Prawat Nagvajara At the transistor level of logic circuits, transistors operate as switches with the logic variables controlling the open or closed

More information

Integrated Circuits & Systems

Integrated Circuits & Systems Federal University of Santa Catarina Center for Technology Computer Science & Electronics Engineering Integrated Circuits & Systems INE 5442 Lecture 16 CMOS Combinational Circuits - 2 guntzel@inf.ufsc.br

More information

5.0 CMOS Inverter. W.Kucewicz VLSICirciuit Design 1

5.0 CMOS Inverter. W.Kucewicz VLSICirciuit Design 1 5.0 CMOS Inverter W.Kucewicz VLSICirciuit Design 1 Properties Switching Threshold Dynamic Behaviour Capacitance Propagation Delay nmos/pmos Ratio Power Consumption Contents W.Kucewicz VLSICirciuit Design

More information

9/18/2008 GMU, ECE 680 Physical VLSI Design

9/18/2008 GMU, ECE 680 Physical VLSI Design ECE680: Physical VLSI Design Chapter III CMOS Device, Inverter, Combinational circuit Logic and Layout Part 3 Combinational Logic Gates (textbook chapter 6) 9/18/2008 GMU, ECE 680 Physical VLSI Design

More information

Digital Microelectronic Circuits ( ) The CMOS Inverter. Lecture 4: Presented by: Adam Teman

Digital Microelectronic Circuits ( ) The CMOS Inverter. Lecture 4: Presented by: Adam Teman Digital Microelectronic Circuits (361-1-301 ) Presented by: Adam Teman Lecture 4: The CMOS Inverter 1 Last Lectures Moore s Law Terminology» Static Properties» Dynamic Properties» Power The MOSFET Transistor»

More information

Name: Answers. Grade: Q1 Q2 Q3 Q4 Q5 Total. ESE370 Fall 2015

Name: Answers. Grade: Q1 Q2 Q3 Q4 Q5 Total. ESE370 Fall 2015 University of Pennsylvania Department of Electrical and System Engineering Circuit-Level Modeling, Design, and Optimization for Digital Systems ESE370, Fall 2015 Midterm 1 Monday, September 28 5 problems

More information

Chapter 9. Estimating circuit speed. 9.1 Counting gate delays

Chapter 9. Estimating circuit speed. 9.1 Counting gate delays Chapter 9 Estimating circuit speed 9.1 Counting gate delays The simplest method for estimating the speed of a VLSI circuit is to count the number of VLSI logic gates that the input signals must propagate

More information

Lecture 9: Combinational Circuits

Lecture 9: Combinational Circuits Introduction to CMOS VLSI Design Lecture 9: Combinational Circuits David Harris, Harvey Mudd College Kartik Mohanram and Steven Levitan University of Pittsburgh Outline q ubble Pushing q Compound Gates

More information

The CMOS Inverter: A First Glance

The CMOS Inverter: A First Glance The CMOS Inverter: A First Glance V DD S D V in V out C L D S CMOS Inverter N Well V DD V DD PMOS 2λ PMOS Contacts In Out In Out Metal 1 NMOS Polysilicon NMOS GND CMOS Inverter: Steady State Response V

More information

CPE/EE 427, CPE 527 VLSI Design I L06: CMOS Inverter, CMOS Logic Gates. Course Administration. CMOS Inverter: A First Look

CPE/EE 427, CPE 527 VLSI Design I L06: CMOS Inverter, CMOS Logic Gates. Course Administration. CMOS Inverter: A First Look CPE/EE 47, CPE 57 VLSI esign I L6: CMOS Inverter, CMOS Logic Gates epartment of Electrical and Computer Engineering University of labama in Huntsville leksandar Milenkovic ( www.ece.uah.edu/~milenka )

More information

Lecture 14: Circuit Families

Lecture 14: Circuit Families Introduction to CMOS VLSI Design Lecture 4: Circuit Families David Harris, Harvey Mudd College Kartik Mohanram and Steven Levitan University of Pittsburgh Outline q Pseudo-nMOS Logic q Dynamic Logic q

More information

CMOS Inverter: CPE/EE 427, CPE 527 VLSI Design I L06: CMOS Inverter, CMOS Logic Gates. Course Administration. CMOS Properties.

CMOS Inverter: CPE/EE 427, CPE 527 VLSI Design I L06: CMOS Inverter, CMOS Logic Gates. Course Administration. CMOS Properties. CMOS Inverter: Steady State Response CPE/EE 47, CPE 57 VLSI esign I L6: CMOS Inverter, CMOS Logic Gates R p V OL = V OH = V M = f(r n, R p ) epartment of Electrical and Computer Engineering University

More information

EE5311- Digital IC Design

EE5311- Digital IC Design EE5311- Digital IC Design Module 3 - The Inverter Janakiraman V Assistant Professor Department of Electrical Engineering Indian Institute of Technology Madras Chennai September 3, 2018 Janakiraman, IITM

More information

CMOS Logic Gates. University of Connecticut 172

CMOS Logic Gates. University of Connecticut 172 CMOS Logic Gates University of Connecticut 172 Basic CMOS Inverter Operation V IN P O N O p-channel enhancementtype MOSFET; V T < 0 n-channel enhancementtype MOSFET; V T > 0 If V IN 0, N O is cut off and

More information

EEC 118 Lecture #5: CMOS Inverter AC Characteristics. Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation

EEC 118 Lecture #5: CMOS Inverter AC Characteristics. Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation EEC 8 Lecture #5: CMOS Inverter AC Characteristics Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation Acknowledgments Slides due to Rajit Manohar from ECE 547 Advanced

More information

E40M Capacitors. M. Horowitz, J. Plummer, R. Howe

E40M Capacitors. M. Horowitz, J. Plummer, R. Howe E40M Capacitors 1 Reading Reader: Chapter 6 Capacitance A & L: 9.1.1, 9.2.1 2 Why Are Capacitors Useful/Important? How do we design circuits that respond to certain frequencies? What determines how fast

More information

ECE 425 Midterm Overview. Fall 2017

ECE 425 Midterm Overview. Fall 2017 ECE 425 Midterm Overview Fall 2017 Overview q Midterm (20% of total grade) Oct 24 th 3:30-5:00pm in class q Materials Lecture 1 through 11 MP0, MP1 HW1, HW2 Practice exam q Rules 1 page of cheat sheet,

More information

Homework Assignment #3 EE 477 Spring 2017 Professor Parker , -.. = 1.8 -, 345 = 0 -

Homework Assignment #3 EE 477 Spring 2017 Professor Parker , -.. = 1.8 -, 345 = 0 - Homework Assignment #3 EE 477 Spring 2017 Professor Parker Note:! " = $ " % &' ( ) * ),! + = $ + % &' (, *,, -.. = 1.8 -, 345 = 0 - Question 1: a) (8%) Define the terms V OHmin, V IHmin, V ILmax and V

More information

Digital Integrated Circuits A Design Perspective

Digital Integrated Circuits A Design Perspective igital Integrated Circuits esign Perspective esigning Combinational Logic Circuits 1 Combinational vs. Sequential Logic In Combinational Logic Circuit Out In Combinational Logic Circuit Out State Combinational

More information

2007 Fall: Electronic Circuits 2 CHAPTER 10. Deog-Kyoon Jeong School of Electrical Engineering

2007 Fall: Electronic Circuits 2 CHAPTER 10. Deog-Kyoon Jeong School of Electrical Engineering 007 Fall: Electronic Circuits CHAPTER 10 Digital CMOS Logic Circuits Deog-Kyoon Jeong dkjeong@snu.ac.kr k School of Electrical Engineering Seoul lnational luniversity it Introduction In this chapter, we

More information

EE115C Digital Electronic Circuits Homework #4

EE115C Digital Electronic Circuits Homework #4 EE115 Digital Electronic ircuits Homework #4 Problem 1 Power Dissipation Solution Vdd =1.0V onsider the source follower circuit used to drive a load L =20fF shown above. M1 and M2 are both NMOS transistors

More information

UNIVERSITY OF CALIFORNIA, BERKELEY College of Engineering Department of Electrical Engineering and Computer Sciences

UNIVERSITY OF CALIFORNIA, BERKELEY College of Engineering Department of Electrical Engineering and Computer Sciences UNIVERSITY OF CALIFORNIA, BERKELEY College of Engineering Department of Electrical Engineering and Computer Sciences Elad Alon Homework #2 EECS141 Due Thursday, September 9, 5pm, box in 240 Cory PROBLEM

More information

CARNEGIE MELLON UNIVERSITY DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING DIGITAL INTEGRATED CIRCUITS FALL 2002

CARNEGIE MELLON UNIVERSITY DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING DIGITAL INTEGRATED CIRCUITS FALL 2002 CARNEGIE MELLON UNIVERSITY DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING 18-322 DIGITAL INTEGRATED CIRCUITS FALL 2002 Final Examination, Monday Dec. 16, 2002 NAME: SECTION: Time: 180 minutes Closed

More information

CMOS Logic Gates. University of Connecticut 181

CMOS Logic Gates. University of Connecticut 181 CMOS Logic Gates University of Connecticut 181 Basic CMOS Inverter Operation V IN P O N O p-channel enhancementtype MOSFET; V T < 0 n-channel enhancementtype MOSFET; V T > 0 If V IN 0, N O is cut off and

More information

ECE 438: Digital Integrated Circuits Assignment #4 Solution The Inverter

ECE 438: Digital Integrated Circuits Assignment #4 Solution The Inverter ECE 438: Digital Integrated Circuits Assignment #4 The Inverter Text: Chapter 5, Digital Integrated Circuits 2 nd Ed, Rabaey 1) Consider the CMOS inverter circuit in Figure P1 with the following parameters.

More information

The CMOS Inverter: A First Glance

The CMOS Inverter: A First Glance The CMOS Inverter: A First Glance V DD V in V out C L CMOS Properties Full rail-to-rail swing Symmetrical VTC Propagation delay function of load capacitance and resistance of transistors No static power

More information

CMOS INVERTER. Last Lecture. Metrics for qualifying digital circuits. »Cost» Reliability» Speed (delay)»performance

CMOS INVERTER. Last Lecture. Metrics for qualifying digital circuits. »Cost» Reliability» Speed (delay)»performance CMOS INVERTER Last Lecture Metrics for qualifying digital circuits»cost» Reliability» Speed (delay)»performance 1 Today s lecture The CMOS inverter at a glance An MOS transistor model for manual analysis

More information

ECE 342 Electronic Circuits. Lecture 35 CMOS Delay Model

ECE 342 Electronic Circuits. Lecture 35 CMOS Delay Model ECE 34 Electronic Circuits Lecture 35 CMOS Delay Model Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jesa@illinois.edu ECE 34 Jose Schutt Aine 1 Digital Circuits V IH : Input

More information

Miscellaneous Lecture topics. Mary Jane Irwin [Adapted from Rabaey s Digital Integrated Circuits, 2002, J. Rabaey et al.]

Miscellaneous Lecture topics. Mary Jane Irwin [Adapted from Rabaey s Digital Integrated Circuits, 2002, J. Rabaey et al.] Miscellaneous Lecture topics Mary Jane Irwin [dapted from Rabaey s Digital Integrated Circuits, 2002, J. Rabaey et al.] MOS Switches MOS transistors can be viewed as simple switches. In an N-Switch, the

More information

Digital Integrated Circuits A Design Perspective

Digital Integrated Circuits A Design Perspective Digital Integrated Circuits Design Perspective Designing Combinational Logic Circuits Fuyuzhuo School of Microelectronics,SJTU Introduction Digital IC Dynamic Logic Introduction Digital IC 2 EE141 Dynamic

More information

The Physical Structure (NMOS)

The Physical Structure (NMOS) The Physical Structure (NMOS) Al SiO2 Field Oxide Gate oxide S n+ Polysilicon Gate Al SiO2 SiO2 D n+ L channel P Substrate Field Oxide contact Metal (S) n+ (G) L W n+ (D) Poly 1 Transistor Resistance Two

More information

Designing Information Devices and Systems II Fall 2017 Miki Lustig and Michel Maharbiz Homework 1. This homework is due September 5, 2017, at 11:59AM.

Designing Information Devices and Systems II Fall 2017 Miki Lustig and Michel Maharbiz Homework 1. This homework is due September 5, 2017, at 11:59AM. EECS 16 Designing Information Devices and Systems II Fall 017 Miki Lustig and Michel Maharbiz Homework 1 This homework is due September 5, 017, at 11:59M. 1. Fundamental Theorem of Solutions to Differential

More information

EE115C Digital Electronic Circuits Homework #3

EE115C Digital Electronic Circuits Homework #3 Electrical Engineering Department Spring 1 EE115C Digital Electronic Circuits Homework #3 Due Thursday, April, 6pm @ 56-147E EIV Solution Problem 1 VTC and Inverter Analysis Figure 1a shows a standard

More information

VLSI Design, Fall Logical Effort. Jacob Abraham

VLSI Design, Fall Logical Effort. Jacob Abraham 6. Logical Effort 6. Logical Effort Jacob Abraham Department of Electrical and Computer Engineering The University of Texas at Austin VLSI Design Fall 207 September 20, 207 ECE Department, University of

More information

Properties of CMOS Gates Snapshot

Properties of CMOS Gates Snapshot MOS logic 1 Properties of MOS Gates Snapshot High noise margins: V OH and V OL are at V DD and GND, respectively. No static power consumption: There never exists a direct path between V DD and V SS (GND)

More information

EE 434 Lecture 33. Logic Design

EE 434 Lecture 33. Logic Design EE 434 Lecture 33 Logic Design Review from last time: Ask the inverter how it will interpret logic levels V IN V OUT V H =? V L =? V LARGE V H V L V H Review from last time: The two-inverter loop X Y X

More information

CMOS logic gates. João Canas Ferreira. March University of Porto Faculty of Engineering

CMOS logic gates. João Canas Ferreira. March University of Porto Faculty of Engineering CMOS logic gates João Canas Ferreira University of Porto Faculty of Engineering March 2016 Topics 1 General structure 2 General properties 3 Cell layout João Canas Ferreira (FEUP) CMOS logic gates March

More information

Digital Integrated Circuits A Design Perspective

Digital Integrated Circuits A Design Perspective Digital Integrated Circuits Design Perspective Jan M. Rabaey nantha Chandrakasan orivoje Nikolić Designing Combinational Logic Circuits November 2002. 1 Combinational vs. Sequential Logic In Combinational

More information

EE 466/586 VLSI Design. Partha Pande School of EECS Washington State University

EE 466/586 VLSI Design. Partha Pande School of EECS Washington State University EE 466/586 VLSI Design Partha Pande School of EECS Washington State University pande@eecs.wsu.edu Lecture 9 Propagation delay Power and delay Tradeoffs Follow board notes Propagation Delay Switching Time

More information

Lecture 8: Logic Effort and Combinational Circuit Design

Lecture 8: Logic Effort and Combinational Circuit Design Lecture 8: Logic Effort and Combinational Circuit Design Slides courtesy of Deming Chen Slides based on the initial set from David Harris CMOS VLSI Design Outline q Logical Effort q Delay in a Logic Gate

More information

and V DS V GS V T (the saturation region) I DS = k 2 (V GS V T )2 (1+ V DS )

and V DS V GS V T (the saturation region) I DS = k 2 (V GS V T )2 (1+ V DS ) ECE 4420 Spring 2005 Page 1 FINAL EXAMINATION NAME SCORE /100 Problem 1O 2 3 4 5 6 7 Sum Points INSTRUCTIONS: This exam is closed book. You are permitted four sheets of notes (three of which are your sheets

More information

VLSI Design I; A. Milenkovic 1

VLSI Design I; A. Milenkovic 1 ourse dministration PE/EE 47, PE 57 VLI esign I L6: omplementary MO Logic Gates epartment of Electrical and omputer Engineering University of labama in Huntsville leksandar Milenkovic ( www.ece.uah.edu/~milenka

More information

CMOS Technology for Computer Architects

CMOS Technology for Computer Architects CMOS Technology for Computer Architects Recap Technology Trends Lecture 2: Transistor Inverter Iakovos Mavroidis Giorgos Passas Manolis Katevenis FORTH-ICS (University of Crete) 1 2 Recap Threshold Voltage

More information

VLSI GATE LEVEL DESIGN UNIT - III P.VIDYA SAGAR ( ASSOCIATE PROFESSOR) Department of Electronics and Communication Engineering, VBIT

VLSI GATE LEVEL DESIGN UNIT - III P.VIDYA SAGAR ( ASSOCIATE PROFESSOR) Department of Electronics and Communication Engineering, VBIT VLSI UNIT - III GATE LEVEL DESIGN P.VIDYA SAGAR ( ASSOCIATE PROFESSOR) contents GATE LEVEL DESIGN : Logic Gates and Other complex gates, Switch logic, Alternate gate circuits, Time Delays, Driving large

More information

VLSI Design Issues. ECE 410, Prof. F. Salem/Prof. A. Mason notes update

VLSI Design Issues. ECE 410, Prof. F. Salem/Prof. A. Mason notes update VLSI Design Issues Scaling/Moore s Law has limits due to the hysics of material. Now L (L=20nm??) affects tx delays (seed), noise, heat (ower consumtion) Scaling increases density of txs and requires more

More information

Lecture 9: Combinational Circuit Design

Lecture 9: Combinational Circuit Design Lecture 9: Combinational Circuit Design Outline Bubble Pushing Compound Gates Logical Effort Example Input Ordering symmetric Gates Skewed Gates Best P/N ratio 0: Combinational Circuits CMOS VLSI Design

More information

Step 1. Finding V M. Goal: Þnd V M = input voltage for the output = V M both transistors are saturated at V IN = V M since

Step 1. Finding V M. Goal: Þnd V M = input voltage for the output = V M both transistors are saturated at V IN = V M since Step 1. Finding V M Goal: Þnd V M = input voltage for the output = V M both transistors are saturated at V IN = V M since V DSn = V M - 0 > V M - V Tn V SDp = V DD - V M = (V DD - V M ) V Tp Equate drain

More information

COMBINATIONAL LOGIC. Combinational Logic

COMBINATIONAL LOGIC. Combinational Logic COMINTIONL LOGIC Overview Static CMOS Conventional Static CMOS Logic Ratioed Logic Pass Transistor/Transmission Gate Logic Dynamic CMOS Logic Domino np-cmos Combinational vs. Sequential Logic In Logic

More information

Integrated Circuits & Systems

Integrated Circuits & Systems Federal University of Santa Catarina Center for Technology Computer Science & Electronics Engineering Integrated Circuits & Systems INE 5442 Lecture 13 The CMOS Inverter: dynamic behavior (delay) guntzel@inf.ufsc.br

More information

EE141Microelettronica. CMOS Logic

EE141Microelettronica. CMOS Logic Microelettronica CMOS Logic CMOS logic Power consumption in CMOS logic gates Where Does Power Go in CMOS? Dynamic Power Consumption Charging and Discharging Capacitors Short Circuit Currents Short Circuit

More information

Lecture 16: Circuit Pitfalls

Lecture 16: Circuit Pitfalls Introduction to CMOS VLSI Design Lecture 16: Circuit Pitfalls David Harris Harvey Mudd College Spring 2004 Outline Pitfalls Detective puzzle Given circuit and symptom, diagnose cause and recommend solution

More information

ESE 570: Digital Integrated Circuits and VLSI Fundamentals

ESE 570: Digital Integrated Circuits and VLSI Fundamentals ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 8: February 9, 016 MOS Inverter: Static Characteristics Lecture Outline! Voltage Transfer Characteristic (VTC) " Static Discipline Noise Margins!

More information