CMPEN 411 VLSI Digital Circuits Spring 2011 Lecture 07: Pass Transistor Logic


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1 CMPEN 411 VLSI Digital Circuits Spring 2011 Lecture 07: Pass Transistor Logic [dapted from Rabaey s Digital Integrated Circuits, Second Edition, 2003 J. Rabaey,. Chandrakasan,. Nikolic] Sp11 CMPEN 411 L07 S.1
2 Heads up This lecture Pass transistor logic  Reading assignment Rabaey, et al, Next lecture MOS transistor dynamic behavior  Reading assignment Rabaey, et al, & Wiring capacitance  Reading assignment Rabaey, et al, Sp11 CMPEN 411 L07 S.2
3 Review: Static Complementary CMOS In1 In2 InN In1 In2 InN V DD PUN PDN F(In1,In2, InN) PUN and PDN are dual logic networks High noise margins V OH and V OL are at V DD and GND, respectively Low output impedance, high input impedance No static power consumption Never a direct path between V DD and GND in steady state Delay a function of load capacitance and transistor on resistance Comparable rise and fall times (under the appropriate relative transistor sizing conditions) Sp11 CMPEN 411 L07 S.3
4 Review: Static Complementary CMOS Question: In1 In2 InN In1 In2 InN V DD PUN PDN F(In1,In2, InN) Why PUN use only PMOS and PDN use only NMOS? NSWER: NMOS transistors pass a 0 but a 1 PUN and PDN are dual logic networks PMOS transistors pass a 1 but a 0 Sp11 CMPEN 411 L07 S.4
5 NMOS Transistors in Series/Parallel Primary inputs drive both gate and source/drain terminals NMOS switch closes when the gate input is X Y X = Y if X Y X = Y if Remember  NMOS transistors pass a 0 but a 1 Sp11 CMPEN 411 L07 S.5
6 PMOS Transistors in Series/Parallel Primary inputs drive both gate and source/drain terminals PMOS switch closes when the gate input is low X Y X = Y if X Y X = Y if Remember  PMOS transistors pass a 1 but a 0 Sp11 CMPEN 411 L07 S.6
7 Pass Transistor (PT) Logic 0 F = 0 F = Gate is a path exists to both supply rails under all circumstances transistors instead of 2N (for CMOS) No static power consumption Ratioless idirectional (versus undirectional) Sp11 CMPEN 411 L07 S.7
8 VTC of PT ND Gate 1.5/ / / /0.25 F= V out, V 1 0 =V DD, =0 V DD =V DD, =0 V DD ==0 V DD Pure PT logic is not regenerative  the signal gradually degrades after passing through a number of PTs (can fix with static CMOS inverter insertion) Sp11 CMPEN 411 L07 S.8
9 Differential PT Logic (DPL/CPL) PT Network F F Inverse PT Network F F F= F=+ F= ND/NND Sp11 CMPEN 411 L07 S.9 F= OR/NOR Why NFET? F=+ XOR/XNOR F=
10 CPL Properties Differential so complementary data inputs and outputs are always available (so don t need extra inverters) Still static, since the output defining nodes are always tied to V DD or GND through a low resistance path Design is ; all gates use the same topology, only the inputs are permuted. Simple XOR makes it attractive for structures like Fast (assuming number of transistors in series is small) dditional routing overhead for complementary signals Sp11 CMPEN 411 L07 S.10
11 CPL Full dder C in C in!sum Sum C in C in!c out C in C out C in Sp11 CMPEN 411 L07 S.11
12 CPL Full dder C in C in!sum Sum C in C in!c out C in C out C in Sp11 CMPEN 411 L07 S.12
13 NMOS Only PT Driving an Inverter In = V DD V x = V GS M 2 = V DD D S M 1 V x does not pull up to V DD, but Threshold voltage drop causes static power consumption (M 2 may be weakly conducting forming a path from V DD to GND) Notice V Tn increases for pass transistor due to body effect (V S ) Sp11 CMPEN 411 L07 S.13
14 Voltage Swing of PT Driving an Inverter 3 In V DD In = 0 V DD D 0.5/0.25 S x 1.5/ /0.25 Out Voltage, V 2 1 x = 1.8V Out Time, ns ody effect large V S at x  when pulling high ( is tied to GND and S charged up close to V DD ) So the voltage drop is even worse V x = V DD  (V Tn0 + γ( ( 2φ f + V x )  2φ f )) Sp11 CMPEN 411 L07 S.14
15 Cascaded NMOS Only PTs = V DD = V DD M 1 G C = V DD S M 2 x = V DD  V Tn1 G S y = V DD Out = V DD M 1 x C = V DD M 2 y Out Swing on y = V DD  V Tn1  V Tn2 Swing on y = V DD  V Tn1 Pass transistor gates should never be cascaded as on the left Logic on the right suffers from static power dissipation and reduced noise margins Sp11 CMPEN 411 L07 S.15
16 Solution 1: Level Restorer Level Restorer on =1 M 2 Out=0 =0 M n M r off x= 0 1 M 1 Out =1 Full swing on x (due to Level Restorer) so no static power consumption by inverter No static backward current path through Level Restorer and PT since Restorer is only active when is high For correct operation M r must be sized correctly (ratioed) Sp11 CMPEN 411 L07 S.16
17 Transient Level Restorer Circuit Response 3 W/L 2 =1.50/0.25 W/L n =0.50/0.25 W/L 1 =0.50/0.25 Volta age, V 2 1 W/L r =1.75/0.25 W/L r =1.50/0.25 node x never goes below V M of inverter so output never switches Sp11 CMPEN 411 L07 S.17 W/L r =1.0/0.25 Time, ps W/L r =1.25/0.25 Restorer has speed and power impacts: increases the capacitance at x, slowing down the gate; increases t r (but decreases t f )
18 Solution 2: Multiple V T Transistors Technology solution: Use (near) zero V T devices for the NMOS PTs to eliminate most of the threshold drop (body effect still in force preventing full swing to V DD ) In 2 = 0V = 2.5V on low V T transistors Out In 1 = 2.5V = 0V sneak path off but leaking Impacts static power consumption due to subthreshold currents flowing through the PTs (even if V GS is below V T ) Sp11 CMPEN 411 L07 S.18
19 Solution 3: Transmission Gates (TGs) Most widely used solution C C C C C = GND C = GND = V DD = GND C = V DD C = V DD Full swing bidirectional switch controlled by the gate signal C, = if C = 1 Sp11 CMPEN 411 L07 S.19
20 Solution 3: Transmission Gates (TGs) Most widely used solution C C C C C = GND C = GND = V DD = GND C = V DD C = V DD Full swing bidirectional switch controlled by the gate signal C, = if C = 1, minimum size (ratioless) Sp11 CMPEN 411 L07 S.20
21 TG Multiplexer S S S F V DD In 2 S F In 1 S F =!(In 1 S + In 2 S) GND In 1 S S In 2 Sp11 CMPEN 411 L07 S.21
22 Transmission Gate XOR How many FETs for CMOS implementation? Sp11 CMPEN 411 L07 S.22
23 Transmission Gate XOR off on! off on! 0 1 an inverter Sp11 CMPEN 411 L07 S.23
24 TG Full dder C in Sum C out How many transistors? Sp11 CMPEN 411 L07 S.24
25 Differential TG Logic (DPL) GND F= F= GND V DD F= F= V DD ND/NND XOR/XNOR Sp11 CMPEN 411 L07 S.25
26 6transistor SRM Storage Cell WL M5!Q M2 M4 Q M6 M1 M3!L L Will cover how the cell works in detail later Sp11 CMPEN 411 L07 S.26
27 MOS OR ROM Cell rray L(0) L(1) L(2) L(3) 0 WL(0) 0 1 WL(1) on on V DD 0 WL(2) V DD 0 WL(3) predischarge 1 0 Sp11 CMPEN 411 L07 S.27
28 Next Lecture and Reminders Next lecture MOS transistor dynamic behavior  Reading assignment Rabaey, et al, & Wiring capacitance  Reading assignment Rabaey, et al, Sp11 CMPEN 411 L07 S.28
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