Lecture 11 VTCs and Delay. No lab today, Mon., Tues. Labs restart next week. Midterm #1 Tues. Oct. 7 th, 6:308:00pm in 105 Northgate


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1 EE4Fall 2008 Digital Integrated Circuits Lecture VTCs and Delay Lecture # Announcements No lab today, Mon., Tues. Labs restart next week Midterm # Tues. Oct. 7 th, 6:308:00pm in 05 Northgate Exam is open notes, book, calculators, etc. Midterm review session: Monday am 2pm, Kroeber 55 2 Lecture # 2
2 Class Material Last lecture MOS capacitance Today s lecture Using the MOS models: VTCs and Delay Reading (5.5.3, 5.4.2) 3 Lecture # 3 CMOS Inverter VTC 4 Lecture # 4
3 The CMOS Inverter V DD W p = βw n V in W n 5 Lecture # 5 PMOS Load Lines For DC VTC, I Dn = I Dp Graphically, looking for intersections of NMOS and PMOS IV characteristics To put IV curves on the same plot, PMOS IV is flipped since V DSp = V DD Also, V GSp = V dd V in I I Dn V in = 2.5 V in =.5 V in = 0 V in =.5 I Dp I Dn V in= 0 V in =.5 (=V DSn ) V DSp 6 Lecture # 6
4 CMOS Inverter Load Characteristics I Dn V in = 0 V in = 2.5 PMOS V in = 0.5 V in = 2 NMOS V in =.5 V in = V in =.5 V in = V in = 2 V in =.5 V in = V in = 0.5 V in = 2.5 V in = 0 7 Lecture # 7 CMOS Inverter VTC NMOS off PMOS res NMOS sat PMOS res NMOS sat PMOS sat NMOS res PMOS sat NMOS res PMOS off V in 8 Lecture # 8
5 CMOS Inverter VTC NMOS off PMOS res NMOS sat PMOS res NMOS sat PMOS sat NMOS res PMOS sat NMOS res PMOS off V in 9 Lecture # 9 Switching Threshold as a Function of Transistor Ratio I ( V ) = I ( V ) dn M dp M V (V) M W /W p n 0 0 Lecture #
6 Switching Threshold as a Function of Transistor Ratio V (V) M * * ( ) ( ) k V V V = k V V V V n D, VSATn M Tn p D, VSATp DD M Tp Solving for V V M M yields: ( Tp ) V + r V V k V W = with r = = + r k V Wυ * * Tn DD p VSATp pυsatp n VSATn n satn W /W p n Lecture # Determining V IH and V IL V OH V M V in V OL V IL V IH A simplified approach 2 2 Lecture #
7 Gain as a function of VDD (V).5 (V) V (V) in 0.05 Gain= V (V) in 3 3 Lecture # Impact of Sizing 2.5 (V) 2.5 Wider NMOS Wider PMOS Symmetrical V in (V) 4 4 Lecture #
8 Impact of Process Variations 2.5 (V) 2.5 Fast NMOS Slow PMOS Nominal Fast PMOS Slow NMOS V in (V) 5 5 Lecture # CMOS Switching Delay 6 6 Lecture #
9 MOS Transistor as a Switch Discharging a capacitor We modeled this with: R C i i = i D D = D ( v ) DS dv C dt DS C t p = ln (2) RC 7 7 Lecture # MOS Transistor as a Switch Saw that real transistors aren t exactly resistors Look more like current sources in saturation Two questions: Which region of IV curve determines delay? How can that match up with the RC model? 8 8 Lecture #
10 Transistor Driving a Capacitor With a step input: V DD V DD/2 I D V GS = V DD V VSAT V DD /2 V DD V DS Transistor is in (velocity) saturation during entire transition from V DD to V DD /2 9 9 Lecture # Switching Delay In saturation, transistor basically acts like a current source: V OUT V OUT I DSAT C V DD V DD /2 t p t V OUT = V DD (I DSAT /C)t t p = C(V DD /2)/I DSAT Lecture #
11 Switching Delay (with Output Conductance) Including output conductance: V OUT I DSAT /(λi DSAT ) C OUT t ( C λi DSAT ) ( DD + ) e V = V λ  λ For small λ: t p + CV ( DD 2) ( λv ) I DD DSAT 2 2 Lecture # RC Model Transistor current not linear on V OUT how is the RC model going to work? Look at waveforms: Voltage looks like a ramp for RC too V OUT NMOS.3. RC t/τ Lecture #
12 Finding Req Match the delay of the RC model with the actual delay: p CV ( DD 2) ( + λv ) I DD t = t DSAT p, RC = ln( 2 ) ReqC ( VDD 2) Req = ln( 2)( + λv ) DD I DSAT Often just: R eq VDD 2ln2 I ( ) DSAT Note that the book uses a different method and gets 0.75 V DD /I DSAT instead of ~0.72 V DD /I DSAT. Why did we do it this way vs. the book s method? Lecture # The Book s s Method Lecture #
13 The Transistor as a Switch 7 x R eq (Ohm) V (V) DD Lecture # The Transistor as a Switch Lecture #
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