Lecture 3: CMOS Transistor Theory


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1 Lecture 3: CMOS Transistor Theory
2 Outline Introduction MOS Capacitor nmos IV Characteristics pmos IV Characteristics Gate and Diffusion Capacitance 2
3 Introduction So far, we have treated transistors as ideal switches An ON transistor passes a finite amount of current Depends on terminal voltages Derive currentvoltage (IV) relationships Transistor gate, source, drain all have capacitance I = C (V/t) > t = (C/I) V Capacitance and current determine speed 3
4 MOS Capacitor Gate and body form MOS capacitor Operating modes Accumulation Depletion Inversion (a) V g < polysilicon gate silicon dioxide insulator ptype body 4
5 Terminal Voltages Mode of operation depends on V g, V d, V s = V g V s V gd = V g V d  + V g + V gd  V ds = V d V s = V gd Source and drain are symmetric diffusion terminals By convention, source is terminal at lower voltage Hence V ds 0 nmos body is grounded. First assume source is 0 too. Three regions of operation Cutoff Linear Saturation V s  V + ds V d 5
6 nmos Cutoff No channel I ds 0 = g +  V gd s d n+ n+ ptype body b 6
7 nmos Linear Channel forms Current flows from d to s e  from s to d I ds increases with V ds Similar to linear resistor > V t +  s g +  V gd = n+ n+ V ds = 0 ptype body b d > V t +  g +  > V gd > V t s d I ds n+ n+ ptype body b 0 < V ds < V t 7
8 nmos Saturation Channel pinches off I ds independent of V ds We say current saturates Similar to current source > V t +  g +  V gd < V t s d I ds n+ n+ V ds > V t ptype body b 8
9 IV Characteristics In Linear region, I ds depends on How much charge is in the channel? How fast is the charge moving? 9
10 Channel Charge MOS structure looks like parallel plate capacitor while operating in inversions Gate oxide channel Q channel = CV C = C g = ox WL/t ox = C ox WL C ox = ox / t ox V = V gc V t = ( V ds /2) V t gate t ox L n+ n+ ptype body polysilicon gate W SiO2 gate oxide (good insulator, ox = 3.9) V g + + source C g V gd drain   channel n+  + n+ V s V ds ptype body V d 10
11 Carrier velocity Charge is carried by e Electrons are propelled by the lateral electric field between source and drain E = V ds /L Carrier velocity v proportional to lateral Efield v = E called mobility Time for carrier to cross channel: t = L / v 11
12 nmos Linear IV Now we know How much charge Q channel is in the channel How much time t each carrier takes to cross I ds Qchannel t W V C V V V L V V ds gs V t V 2 ds ds ox gs t 2 ds W = Cox L 12
13 nmos Saturation IV If V gd < V t, channel pinches off near drain When V ds > V dsat = V t Now drain voltage no longer increases current V I V V dsat V 2 V 2 gs Vt 2 ds gs t dsat 13
14 nmos IV Summary Shockley 1 st order transistor models 0 Vgs V V I V V ds V V V 2 V V 2 V V 2 ds gs t ds ds dsat gs t ds dsat t cutoff linear saturation 14
15 Example We will be using a 0.6 m process for your project From AMI Semiconductor t ox = 100 Å 2.5 = 350 cm 2 = 5 /V*s 2 V t = 0.7 V 1.5 = 4 Plot I ds vs. V ds 1 V = 0, 1, 2, 3, 4, 5 gs = Use W/L = 4/2 14 W W W Cox μa/v L L L I ds (ma) = 2 = 1 V ds 15
16 pmos IV All dopings and voltages are inverted for pmos Source is the more positive terminal Mobility p is determined by holes Typically 23x lower than that of electrons n 120 cm 2 /V s in AMI 0.6 m process 0 Thus pmos must be wider to = V provide same current gs = In this class, assume = n / p = 2 I ds (ma) = V ds = 1 16
17 Capacitance Any two conductors separated by an insulator have capacitance Gate to channel capacitor is very important Creates channel charge necessary for operation Source and drain have capacitance to body Across reversebiased diodes Called diffusion capacitance because it is associated with source/drain diffusion These are parasitic capacitances 17
18 Gate Capacitance Approximate channel as connected to source C gs = ox WL/t ox = C ox WL = C permicron W C permicron is typically about 2 ff/m polysilicon gate W t ox L n+ n+ ptype body SiO2 gate oxide (good insulator, ox = ) 18
19 Diffusion Capacitance C sb, C db Undesirable, called parasitic capacitance Capacitance depends on area and perimeter Use small diffusion nodes Comparable to C g for contacted diff ½ C g for uncontacted Varies with process 19
20 MOS Capacitance Model The intrinsic capacitance has 3 components: Cgb, Cgs, and Cgd Cutoff: Accumulation(Vgs<0) :Cgb=Co Depletion (Vgs<Vt): 1/Cgb=1/Co+1/Cdep (series cap) Linear (Inversion Vgs>Vt): channel is connected to S and DCgb=0 For Vds=0 Cgs=Cds=Co/2  For Vds>0: drain becomes less inverted and Cds decreases Saturation (Vds>Vsat): channel pinches off and all capacitance is to the source. For ideal transistor Cgs=2/3Co 20
21 MOS Diffusion Capacitance The p n junction between the source diffusion and the body contributes parasitic capacitance across the depletion region The capacitance depends on both the area AS and sidewall perimeter PS of the source diffusion region Parasitic capacitance also depends on the bias conditions and the fabrication technology parameters A MOS transistor can be viewed as a fourterminal device with capacitances between each terminal pair 21
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