FIELD-EFFECT TRANSISTORS

Transcription

1 FIEL-EFFECT TRANSISTORS 1 Semiconductor review 2 The MOS capacitor 2 The enhancement-type N-MOS transistor 3 I-V characteristics of enhancement MOSFETS 4 The output characteristic of the MOSFET in saturation 5 The PMOS transistor 6 Real MOSFET characteristics 7 CMOS design rules 1

2 Semiconductors Four types of charge are present inside a semiconductor: the fixed positive charge of ionized donors, the fixed negative charge of ionized acceptors, the positive mobile charge of holes, and the negative mobile charge of electrons. We consider all donors and acceptors ionized N = N and N = N + A A On this basis, the net positive charge density ρ is ρ = q( N N + p n) A 2

3 Boltzmann s Law (1) In equilibrium electrons and holes follow Boltzmann s law and their concentrations (number per unit volume) are proportional to k=1.38x10-23 J/K - Boltzmann constant T - absolute temperature (K). electron and hole densities in equilibrium are related to electrostatic potential φ by n( φ1) n( φ ) q=1.6x10-19 C 2 = e q( φ φ ) 1 2 kt -( Energy / kt ) e p( φ1) p( φ ) q( φ φ ) 3 2 = e 1 2 kt

4 n 0 and p 0 - equilibrium electron and hole concentrations in the neutral bulk (φ=0 ) u Boltzmann s Law (2) qφ qφ kt u kt = 0 = = 0 0 = 0 p p e p e = φ φ / t φ = kt / q t - normalized electrostatic potential - thermal voltage the mass-action law is n i - concentration of electrons (and holes) in the intrinsic semiconductor n n e n e 2 np = n i 4 u

5 Example: Calculate the built-in potential for a Si p-n junction with N A = atoms/cm 3 and N = atoms/cm 3,T=300K In equilibrium, if we choose the potential origin φ = 0 where the semiconductor is intrinsic (i.e., where p 0 =n 0 =n i ), then p 0 = / t nie φ φ Far from the junction in the n-side 0 n 0 = / t nie φ φ n region t n N n e φ = φ i / Far from the junction in the p-side The built-in potential is given by p region t p N n e φ = φ 0 A i / N N A NN A φbi = φn region φp region = φt ln φt ln = φt ln 2 n i n i ni 15 ( ) φ 26 ln mv bi 5

6 The two-terminal MOS structure 6

7 The ideal two-terminal MOS structure (V FB =0) V G C ox = Aε t ox ox V Q G G φ = s Q C + Q = C G ox + φ s _ 0 Q G Q C M O S A - capacitor area, t ox - oxide thickness ε ox - permittivity of oxide Q C ε Q G = ; C ox = = A A t V G G ox ox φ Q C = s Cox ox 7

8 Example: oxide capacitance (a) Calculate the oxide capacitance per unit area for t ox = 5 and 20 nm assuming ε ox = 3.9ε 0, where ε 0 = F/cm is the permittivity of free space. (b) etermine the area of a 1pF metal-oxide-metal capacitor for the two oxide thicknesses given in (a). Answer: (a) =690 nf/cm 2 = 6.9 ff/µm 2 for t ox =5 nm and = 172 nf/cm 2 = 1.7 ff/µm 2 for t ox = 20 nm. The capacitor areas are 145 and 580 µm 2 for oxide thicknesses of 5 and 20 nm, respectively. 8

9 The flat-band voltage In equilibrium (with the two terminals shortened/open), the contact potential between the gate and the semiconductor substrate of the MOS induces charges in the gate and the semiconductor for V GB =0. Charges inside the insulator and at the semiconductor-insulator interface also induce a semiconductor charge at zero bias. The effect of the contact potential and oxide charges can be counterbalanced by applying a gate-bulk voltage called the flat-band voltage V FB. V Q V = φ C G FB s C ox 9

10 Example: flat-band voltage (a) etermine the expression for the flat-band voltage of n + polysilicon-gate on p-type silicon (b) Calculate the flat-band voltage for an n + polysilicon-gate on p-type silicon structure with N A = atoms/cm 3. Answer: (a) In equilibrium, by analogy with an n + p junction, the potential of the n + -region is positive with respect to that of the p- region. The flat-band condition is obtained by applying a negative potential to the n + gate with respect to the p-type semiconductor of value (b) V V N A _ + = φ _ + = 0.56 V φ ln ni 7 = 0.56 V φ ln 10 = 980 mv FB n p bi n p t FB t ( ) 10

11 Regions of operation of the MOSFET: Accumulation (p-substrate) V GB Q G G Q o Q C V Q φ G B s < V > 0 C < 0 F B Holes + accumulate in the p-type semiconductor surface B 11

12 Regions of operation of the MOSFET: epletion (p-substrate) Q G G V Q 0 > V < 0 G B C < φ < s F B φ F V GB Q o Q - - C Holes evacuate from the P semiconductor surface and acceptor ion charges become uncovered - B φ F = Fermi potential ( to be defined) 12

13 Regions of operation of the MOSFET: Inversion (p-substrate) V GB Q G G Q o Q C V Q φ G B s < C > > φ V 0 F F B electrons approach the surface! B 13

14 Inversion for p-type substrate Volume charge density inside the semiconductor: ρ = q( p e n e + n p ) u u epletion of holes prevails over electron charge when p e > n e u 0 0 u or, equivalently φ < φ t 2 p 0 ln( ) n 0 mass-action law φt p p = ln( ) = ln( ) = φf 2 n φ 2 t i ni For φ >φ F the concentration of minority carriers (n) becomes higher than that of majority carriers (p); the semiconductor operates in the inversion region 14

15 Strong Inversion for p-type substrate Volume charge density inside the semiconductor: ρ = q( p e n e + n p ) u u Electron (minority carrier) density equals the hole ( majority carrier) deep in the bulk n e > p u 0 0 φ > φ p 0 t ln( ) n0 mass-action law φ p φ p = = = φ t ln( ) 2 ln( ) 2 2 t F ni ni For φ >2φ F the concentration of minority carriers (n) becomes higher than that of majority carriers (p) deep in the bulk; the semiconductor operates in the strong inversion region 15

16 Threshold voltage ( for strong inversion) Gate voltage for which φ s = 2φ At threshold we can neglect the inversion charge Q I compared with the depletion charge Q B F Recalling that V Q Q V = φ φ C C G FB s s Cox B ox Q qn x = 2 qε N φ B A d s A s it follows that V V + 2φ + γ 2 φ T FB F F γ = 2 qε N / C s A ox 16

17 Example: threshold voltage Estimate V T for an n-channel transistor with n + polysilicon gate, N A =10 17 atoms/cm 3 and t ox =5 nm. Answer: The flat-band voltage (slide 10) is V; φ F =0.419; C ox = 690 nf/cm 2. The body-effect factor is γ = 2 qε N / C = V s A ox V V + 2φ + γ 2 φ = = 0.1V T FB F F For this low value of the threshold voltage, the off-current (for V GS =0) is too high for digital circuits. Solution to control the magnitude of the threshold voltage without an exaggerated increase in the slope factor a non-uniform high-low channel doping. 17

18 5.3 The Enhancement-Type NMOS Transistor n + Source Region W S Channel Region B L G n n+ + rain Region Metal Silicon ioxide ( SiO ) 2 P-Type Substrate (Body) 0.8 µ CMOS technology L min = 0.8 µm metal width 1.4 µm Wmin = 2.0 µm t ox = 160 Å X j = 0.40 µm Source (S) v S i i G i S Gate (G) n + Channel Region n + L v G P-Type Substrate Body (B) v rain () x j ( a ) NMOS transistor structure ( b ) cross section and ( c ) circuit symbol 18 G i i G i B i S S B i B v B i G = 0 i B = 0 i = i S

19 MOSFET in subthreshold (weak inversion) V GS <V T 19

20 MOSFET for V GS >V T in the linear region 20

21 MOSFET for V GS >V T in the triode region 21

22 MOSFET for V GS >V T in the saturation region 22

23 (a) n + S Immobile Acceptor Ion p V << V GS TN n + epletion Region ( a ) No ( electron ) channel between source and drain. B (b) (c) S S p p V < V GS TN n + n + V > V GS TN n + n + B n-type Inversion Layer B epletion Region epletion Region ( b ) No ( electron ) channel between source and drain. In fact, a weakly inverted layer can be induced in the substrate ( weak inversion ). ( c ) The electric field induces an electron channel that connects the source and drain islands. ( a ) V GS << V TN ( b ) V GS < V TN ( c ) V GS > V TN 23

24 V S V G 2V N + N + V V S V G V 1V 2V 1V N + N + P B P B V G = 2V V S = V = 0V ions ( a ) electrons V G = 2V V S = V = 1V ( b ) V G N + N + P B 1V ( a ) MOSFET in the linear region for V = V S = 0V ( b ) MOSFET in the linear region for V = V S = 1V ( c ) MOSFET in the linear region for V = 1V, V S = 0V V G = 2V V S = 0V V = 1V ( c ) 24

25 S n + G v > V GS TN n + v Small S Waterfalls analogy Water epletion Region p Acceptor Ion B S G v > V GS TN v = v - V S GS TN n + n + epletion Region p B S G v > V GS TN v > v - V S GS TN epletion Region n + p n + Pinch-off Point B ( a ) MOSFET in the linear region ( b ) MOSFET with channel just pinched off at the drain. ( c ) Channel pinch off for V S > V GS - V TN 25

26 MOSFET model: drift current y A z V X dx For low electric fields: v x = µ 7 vx vsat 10 cm/s n ε For high electric fields: ε x ε dq q n A dx Ix = = = q n A v x dt dt or J = q n x v x :electric field µ n : electron mobility µ n = µ n ( doping, T, electric field ) q: electronic charge =1.6 x10-19 C 26

27 rift current density J = J n + J p = ( q n µ n + q p µ p ) ε electron current hole current σ At T = 300 K and doping concentrations cm -3 µ n (Si) 1400 cm 2 /Vs, µ p (Si) 500 cm 2 /Vs µ depends on doping level, temperature and electric field. 27

28 5.4 I-V Characteristics of the Enhancement MOSFET Simplified Analysis z x y V S Substrate is grounded φ V G SiO2 Channel length: L Channel width: W I V Q gate = - Q semi -Q I ( Q depletion is negligible ) Q I - C OX ( V G V T0 - φ ) ( inversion layer is very thin ) Q I : inversion charge/area (inversion charge density) ε OX C OX = : oxide capacitance / area TOX 28

29 Strong inversion (linear ) charge model 29

30 For small V S : I K n ( V GS V T ) V S = K ( V V ) 8.00e-4 and di dv V = 5 V GS S n GS T rain-source Current (A) 6.00e e e-4 V GS = 4 V V GS = 3 V V = 2 V GS 0.00e rain-source Voltage (V) 0.8 NMOS i-v characteristics in the linear region (VSB = 0) 30

31 rain-source Current (A) 2.20e e e e e e e e e e e e+0 0 Linear Region 2 V = 5 V GS Pinchoff Locus Saturation Region V GS= 4 V V = 3 V GS V Š 1 V V = 2 V GS GS rain-source Voltage (V) 12 I I 0 for V GS V T W S ( ) V + V I = µ C V V V L 2 n OX G T S = V GS V T V S V SSAT K 2 n ( V V ) 2 GS V GS V T V S V SSAT T Output characteristics for an NMOS transistor with V TN = 1 V and K n = 25 x 10-6 A / V 2 I G B V V S 31 S

32 The PMOS Transistor Source v v < 0 S G v < 0 i i S G Gate i rain p + Channel Region p + L N-Type Substrate Body i B v > 0 B Cross section of an enhancement-mode PMOS transistor S S B I I G G 32

33 Source-rain Current (A) 2.50e e e e e e+0 V = 5 V (V = -5 V) SG GS V = 4 V (V = -4 V) SG GS V = 3 V (V = -3 V) SG GS V = 2 V (V = -2 V) SG GS V Š 1 V (V -1 V) SG GS I 0 for V GS V T S ( ) V + V I = K V V V 2 P G T S I = V GS V T V S V SSAT K 2 p ( V V ) 2 GS T -5.00e Source-rain Voltage (V) V GS V T V S V SSAT Output characteristics for a PMOS transistor with V TP = -1 V and K P = 25 x 10-6 A / V 2 G S B 33 I

34 The CMOS Technology V (0 V) SS v I V (5 V) B S v o S B p+ Ohmic contact n+ n+ p+ p+ n-well NMOS transistor PMOS transistor p-type substrate n+ Ohmic contact N-well CMOS structure for forming both NMOS & PMOS transistors in a single silicon substrate 34

35 Summary of C equations for the enhancement-mode MOSFET G S n-channel I B G G or V T > 0 V S 0 S K = µc S p-channel B G V T < 0 V S 0 ( a ) v GS < V T Cutoff region, i 0 v GS V T OX W L or S I ( b ) v GS V T Triode region v GS V T S ( v V ) v v V i = K ( vg VT ) vs v v V ( v V ) G T S GS T v + v 2 S GS T G T ( b ) v GS V T Saturation region v GS V T K 2 ( vg V T ) vs vgs VT i ( ) 2 = vgs VT v v V ( v V ) S GS T G T i ( b ) ( c ) V GS2 V GS2 ( c ) ( b ) i V GS1 V GS1 V ( a ) V S S ( a ) 35

36 I (A) E-03 Common-source characteristic of an channel MOSFET I ,00E-02 ( A ) 1.00E E-05 V B = V GB ,50E-02 V SB = V E ,00E-02 V B = V GB E E E-09 V SB = V V GB (V) ,00E ,00E V GB (V) V GB V SB 36

37 Subthreshold (weak inversion) model V GS <V T VG VT 0 VS / t n φ VS / φt 0 1 I = I e e C 2qε sn b A n=1+ = 1+ C 2 C 2 φ ox ox F 37 n:

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47 References EEL 7061 Eletrônica Básica Reid R. Harrison, Analog Integrated Circuit esign ECE/CS 5720/6720 epartment of Electrical and Computer Engineering University of Utah. Márcio Cherem Schneider and Carlos Galup-Montoro, CMOS Analog esign Using All-Region MOSFET Modeling, Cambridge University Press, J. M. Rabaey, igital integrated Circuits, Prentice Hall,