Student Number: CARLETON UNIVERSITY SELECTED FINAL EXAMINATION QUESTIONS
|
|
- Lambert Harrison
- 5 years ago
- Views:
Transcription
1 Name: CARLETON UNIVERSITY SELECTE FINAL EXAMINATION QUESTIONS URATION: 6 HOURS epartment Name & Course Number: ELEC 3908 Course Instructors: S. P. McGarry Authorized Memoranda: Non-programmable calculators NO BOOKS OR NOTES Students MUST count the number of pages in this examination question paper before beginning to write, and report any discrepancy immediately to a proctor. This question paper has twenty (0) pages. This examination question paper may not be taken from the examination room. ANSWER ALL QUESTIONS ALL ANSWERS MUST BE WRITTEN ON THE EXAM PAPER (If necessary, continue answers on the back of pages) SEE EN OF EXAM FOR FORMULA & ATA SHEETS WRITE YOUR NAME AN STUENT NUMBER ON EACH PAGE
2 ELEC 3908 SELECTE FINAL EXAMINATION QUESTIONS Page 1. Consider a structure fabricated in silicon with the cross-section shown below. A B C p + p + n + n + n p n S S a) The starting substrate has a doping of n s = x10 14 cm -3, the implant to form the p-region is N A = 8x10 14 cm -3, for the n-region it is N = 5x10 15 cm -3, the n + -region is N + =10 18 cm -3 and the p + -region is N A + =5x10 17 cm -3. Calculate the carrier densities p, n, p + and n +. b) Assuming all the PN junctions act as isolated diodes and ignoring parasitic resistances, draw the equivalent circuit for this structure in terms of the contacts A, B, C, and the substrate S. (i.e. draw how the diodes are connected to each other and A, B, C, and S.) c) Would it be possible to use this structure as a bipolar junction transistor (BJT)? If so, what type of transistor and which contacts would you choose to be the collector, base and emitter and why?
3 ELEC 3908 SELECTE FINAL EXAMINATION QUESTIONS Page 3. Consider a structure fabricated in silicon with the cross-section shown below. A B C a) What type of device does this structure define? S b) What is the purpose of the niso regions in this structure? c) How many mask levels (i.e. patterning steps) are required to form this structure and what regions do they define? d) The starting substrate has a doping of n sub = x10 14 cm -3, the buried layer doping is p bur + = 5x10 18 cm -3 and the epitaxial layer is grown with p epi = 5x10 16 cm -3. The implant used for the n iso -region it is N = x10 17 cm -3, the n + - region is N + = x10 18 cm -3 and the p + -region is N A + = 5x10 17 cm -3. Calculate the carrier densities n iso, n + and p +. e) Assuming all the PN junctions act as isolated diodes and ignoring parasitic resistances, draw the equivalent circuit for this structure in terms of the contacts A, B, C, and the substrate S. (i.e. draw how the diodes are connected to each other and A, B, C, and S.)
4 ELEC 3908 SELECTE FINAL EXAMINATION QUESTIONS Page 4 3. The Shockley-Read-Hall model uses the equation below to calculate the net recombination rate in a semiconductor. U = τ 0 n( x) p( x) ni ( n( x) + p( x) + n ) a) What is meant by low-level injection? i b) Under the conditions of low-level injection in a p-type material the above expression can be solved to give t τ 0 t τ 0 n np0 = ( n0 np0 ) e = Δn0e. If a p-type material is initially raised by Δn 0 under low-injection conditions how long will it take the excess carrier concentration to fall to Δn 0 /3 if the minority carrier lifetime is τ 0 = x10-6 sec? How far, on average, will the carriers diffuse in this time? c) What do the following imply with regards to the generation or recombination of carriers: U = 0? U > 0? U < 0?
5 ELEC 3908 SELECTE FINAL EXAMINATION QUESTIONS Page 5 p = x10 17 cm A deep-diffused junction substrate diode is formed as shown below with the starting substrate doping sub and an implant of N = 5x10 17 cm -3 to form the n -region. The n -region extends for 100 µm into the page (to give an n- region area of 50 µm x 100 µm). 50 µm 0 µm 30 µm a) Assuming that the uniform doping approximation can be used and there is no current spreading, calculate the total series resistance, R s, of the diode shown above. b) If the process being used allows a maximum current density of J max = 10 3 A/cm what is the maximum current, I max, that this diode can carry? c) Using the results from (a) and (b), calculate the forward voltage, V x, of this diode structure at the maximum current, I max. (Assume L p >> 0µm and L n >> 30µm.)
6 ELEC 3908 SELECTE FINAL EXAMINATION QUESTIONS Page 6 5. A epitaxial diode ln(i ) vs V x characteristic is measured at T = 300 K and plotted as shown below. The slope in the linear portion of the curve at V x > 3kT/q is found to be Δln( I ) 1 ΔV = 3.0 V measured at high current and found to be I = 75 ma at V x = 1.0 V. ln(i ) x with an intercept of I S = 10-1 A. A point is I = 75 ma I S = 10-1 A V x = 0.0 V V x = 1.0 V V x 40 µm a) Extract the values of the series resistance, R s, and ideality factor, n, for this diode from the ln(i ) vs V x characteristic. b) The n+ buried layer is µm thick, the contacts are 40 µm apart and 00 µm wide (into the page). Assume that the buried layer dominates the series resistance and that its n + -doping is N = x10 18 cm -3. Using these values calculate the approximate value of R s. (1 µm = 10-4 cm)
7 ELEC 3908 SELECTE FINAL EXAMINATION QUESTIONS Page 7 6. The structure of a bipolar junction transistor (BJT) is illustrated below. a) What are the four regions of operation for a bipolar junction transistor (BJT)? b) What is "transistor action" in a BJT? c) Why the forward current gain, β F, is larger than the reverse current gain, β R, in a well-designed BJT. d) What is the main physical cause of the Early effect in a BJT? e) Why do we call a BJT a "minority carrier" device?
8 ELEC 3908 SELECTE FINAL EXAMINATION QUESTIONS Page 8 7. A bipolar junction transistor (BJT) has the parameters and biases shown in the diagram below. (T = 300 K) N C =10 16 /cm 3 N AB =10 17 /cm 3 N E =10 19 /cm 3 4 V a) The neutral region widths are W C = µm, W B = 1µm and W E = 0.5µm. If the emitter area of the BJT above is µm by 10µm, what are the values of the base and collector currents? (You may use whatever approximations that are appropriate.) b) What is the maximum field, ε deplmax, in the base-collector junction of the BJT above?
9 ELEC 3908 SELECTE FINAL EXAMINATION QUESTIONS Page 9 8. A bipolar junction transistor (BJT) has the parameters and currents shown in the diagram below. (T = 300 K) N C =10 16 /cm 3 N AB =10 17 /cm 3 N E =10 19 /cm 3 I BE = 1 ma V CE = 3 V I CE = 100 ma a) If the neutral region width of the emitter is W E = 0.5µm, what is the neutral region width of the base, W B? (You must use the appropriate approximations.) b) What is the collector-base breakdown voltage with the emitter open, BV CBO, for the BJT shown above if it has a critical field of ε crit = 3x10 5 V/cm?
10 ELEC 3908 SELECTE FINAL EXAMINATION QUESTIONS Page The small-signal hybrid-pi model for the bipolar transistor is shown below. a) In what transistor operating range is this model normally used and what restrictions apply to the use of this model? b) If the transistor collector current, I C is 0 ma, what is the value of the transconductance, g m, for this model? (V BE >> 3kT, T = 300 K) c) If the transistor collector current, I C is 0 ma, what is the value of the output impedance, r 0, for this model (ignoring the Early effect)? (V BE >> 3kT, T = 300 K) d) If the transistor collector current I C = 0 ma and the forward beta β F = 100, what is the value of r π for this model? (V BE >> 3kT, T = 300 K)
11 ELEC 3908 SELECTE FINAL EXAMINATION QUESTIONS Page The maximum low-frequency voltage gain achievable using a FET is given by G max = g m /g o. a) Show that, in saturated mode, G max is only dependent on the channel-shortening parameter, λ, and the biasing conditions (V GS -V T and V S ) of the device. b) What is G max for V GS -V T = 1V and V S = V if λ = 0.05 V -1? c) Find an expression for G max if the FET is biased in triode mode. d) What is G max for V GS -V T = V and V S = 1V if λ = 0.05 V -1?
12 ELEC 3908 SELECTE FINAL EXAMINATION QUESTIONS Page The cross section of a simple substrate n-channel MOSFET biased above threshold is illustrated below. a) What is meant by "pinch-off" in a MOSFET and what happens to the channel when pinch-off occurs? b) How do we add the effect of channel shortening to the MOSFET square law model when V S > V Ssat? c) A gate bias of V GS =.5 V is applied to a MOSFET with a threshold voltage of V T = 0.4 V and substrate doping of N A = 5 x cm -3. The gate oxide thickness is t ox = 0 nm and the device has an effective channel length of µm and width of 10 µm. If channel shortening can be ignored, what is the channel current, I, for V S = 1.5V?
13 ELEC 3908 SELECTE FINAL EXAMINATION QUESTIONS Page The cross section of a simple substrate MOSFET structure is illustrated below. a) How many patterning steps are required to make the structure above and what features does each step define? (In the order in which they are processed.) b) Why do we say that the source and drain implants are "self-aligned" to the gate in a MOSFET process? c) We use the structure above to fabricate a MOSFET with a substrate doping of N A = cm -3 and a heavily doped p + - polysilicon gate. Calculate the threshold voltage, V T, if t ox = 5 nm and V SB = 0V. (T = 300K)
14 ELEC 3908 SELECTE FINAL EXAMINATION QUESTIONS Page The cross section of a simple substrate MOSFET structure is illustrated below. a) Explain briefly the difference between "drawn channel length" and "effective channel length". b) What is the "short channel effect" on threshold voltage? What are the two main techniques used to mitigate this effect? c) What is drift conduction in a semiconductor? How does drift conduction in a semiconductor change at high electric fields?
15 ELEC 3908 SELECTE FINAL EXAMINATION QUESTIONS Page There are three voltage components in the equation used to calculate the basic threshold voltage, V T0, for a MOSFET. V Qˆ dep T 0 = VFB + φ B = VFB + φ B + Cox qε SiN C ox A ( φ ) B a) A simple n-mosfet process starts with a substrate doping of p sub = 5x10 16 cm -3 uses a gate oxide (SiO ) with a thickness of 30 nm and a heavily doped p + polysilicon gate. Calculate the basic threshold voltage, V T0, for an n-channel MOSFET in this process. (T = 300K) b) Briefly describe how the threshold voltage is changed if a voltage is applied between the source of the MOSFET and the substrate (bulk).
16 ELEC 3908 SELECTE FINAL EXAMINATION QUESTIONS Page A MOSFET has a layout as illustrated in the diagram below. There is 0.5 µm of lateral diffusion under the gate from the source and drain implants and the oxide thickness is t ox = 0 nm. The source and drain are implanted at N = cm -3 into the substrate having an initial doping of N A = 5x10 16 cm µm/division (a) Calculate the intrinsic gate-source capacitance, mode. C int GS, for this MOSFET structure assuming it is operating in saturated (b) Calculate the depletion source-bulk capacitance, C dep SB, for this device assuming that the bottom depletion capacitance dominants (i.e. all other non-intrinsic capacitances can be neglected) and V SB = 0V, z SB = ½. g m! tot (c) The transit frequency for a FET is given by f!! "C GS g m int "C GS ignore, what is the transit frequency for this device? (Using the result from (a).). If V GS -V T = 1V and channel shortening can be
17 ELEC 3908 SELECTE FINAL EXAMINATION QUESTIONS Page A MOSFET has a layout as illustrated in the diagram below. There is 0.5 µm of lateral diffusion under the gate from the source and drain implants. 1 µm/division (a) The source and drain are implanted at N = cm -3 into the substrate having an initial doping of N A = 5x10 16 cm -3. Assuming that the sidewall capacitances can be ignored relative to the bottoms, calculate the depletion capacitance of the source and drain if V S = 5V, V SB = 0V, z SB = z B = 1/? (b) Under the same doping and biasing conditions as in (a), how far under the gate will the sidewall depletion regions of the source and drain extend?
18 ELEC 3908 SELECTE FINAL EXAMINATION QUESTIONS Page 18 Equations Ideal iode qv kt I = IS ( e 1) with depletion region GR: ( qv nkt = 1 ) I IS e with series resistance & GR: ( V I R ) nkt I ( q IS e ) x s = 1 where Vx = V + IRs Shockley-Reed-Hall: n( x) p( x) ni U = τ ( n( x) + p( x) + n ) Einstein Relations: iffusion Length: Saturation Current ensity: 0 kt kt n µ n, p µ p q q L n τ, L τ n 0 J S = J Sh + J Se = q p p n0 w n p i p 0 + q n n p0, for thin n and thin p w p Gaussian Integral: Resistivity: J S = J Sh + J Se = q p p n0 L p 0 e x σ = π σ + q nn p0, for thick n and thick p L n = ( σ n + σ p ) = ( qnµ n + qpµ p ) n ρ p ρ ρ d ψ x de x ρ x = = dx dx ε Si ρ x = q p x n x + N N A kt N AN V = ln bi q ni Poisson's Equation: ( ) ( ) ( ) Excess Charge ensity in a iode: ( ) [ ( ) ( ) ] Built-In Voltage: epletion Width: Maximum Electric Field: Avalanche Multiplication Factor: Impact Ionization Probability: iode Junction Conductance: iode Junction Capacitance (per area): W = Charge Control Equation: ( ) Charge Storage Time: Heat Flow: BJT Injection Model Currents: ε Si q N A N q N AN E depl max = ε Si N A + N 1 M = 1 p ii ν, ρ l R = A A ( V ) = = + bi V, xn W, xp W N A N N A + N ( V V ) E depl max p ii =, 3 < ν < 6 E crit di q qv nkt q g = = I Se I dv nkt nkt dqˆ depl dqˆ depl dw N AN Cˆ depl ( V ) = = = q dv dw dv N A + N dqp t Qp( t) = i( t) dt τ 0 I V τ 0 τ V V V dt Φ = κ, Trise = P RTH dx I = I + I, I = I + I, I = I + I F F t s = ln 1 F R >> I 0 ln 1 R V for, R C pc nb B pc I C = qa E pc p C0 W C e qv BC kt 1 I B = qa E pc p C0 W C e qv BC kt 1 bi pe E nb N ε Si N A + N Wq N AN ( ) + qa E nb n B0 ( ) pe W B e qv BE kt e qv BC kt ( ) + qa E pe p E 0 ( ) W E e qv BE kt 1 ( ) + qa E pe p E 0 ( ) I E = qa E nb n B0 W B e qv BE kt e qv BC kt W E e qv BE kt 1 N ε Si = W V ( )
19 ELEC 3908 SELECTE FINAL EXAMINATION QUESTIONS Page 19 BJT Ebbers-Moll Model: I ES qa E nb n B0 W B + qa E pe p E 0 W E I CS qa E nb n B0 W B + qa E pc p C0 W C BJT Base iffusion Capacitance: BJT Transit Frequency: MOSFET Gate Capacitance: (per unit area) rift Conduction: Carrier ensity Relative to E F qa α F E nb n B0 W B qa α R E nb n B0 W B qa E nb n B0 W B + qa E pe p E 0 W E qa E nb n B0 W B + qa E pc p C0 W C ( ) α R I CS e qv BC ( kt 1) ( ) + ( 1 α R )I CS e qv BC ( kt 1) ( ) I CS e qv BC ( kt 1) I E = I ES e qv BE kt 1 I B = ( 1 α F )I ES e qv BE kt 1 I C = α F I ES e qv BE kt 1 B W Cπ = τ Bgm, τ B = nb 1 f τ = π " C depbc + C depbe Ĉ ox = ε ox t ox! ( ) g m +τ B J = qnv n + qpv p = qnµ n + qpµ p # $ ( )ε = σε n = N C e ( E C E F ) kt, p = N V e ( E F E V ) kt Flat Band Voltage: V FB = Φ MS q = Φ M Φ S Bulk Potential (p-type): φ B = kt q ln! N $ A # & " % MOSFET Threshold Voltage (V SB =0): MOSFET Threshold Modulation: MOSFET Square Law Model: Channel shortening depletion charge: n i ( ) q ( ) V T 0 = V FB + ϕ B ˆQ dep = V FB + ϕ B + qε SiN A ϕ B C ox V T = V T 0 +γ ( φ B +V SB φ B ), γ = qε SiN A Ĉ ox W " I = µ n Ĉ ox ( L V GS V T )V S V % S $ '( 1+ λv S ), V GS V T,V S V S,sat # & W "( V = µ n Ĉ GS V T ) % ox L $ # '( 1+ λv S ), V GS V T,V S V S,sat & Qdep ˆ! = ˆQ ) dep 1 x # J 1+ W S + 1+ W &, + L % $ x J x (. * + J '-. C ox MOSFET Transconductance: MOSFET Output Conductance: W S ε Si ( φ B +V SB ), W ε Si φ B +V B qn A qn A g m = di dv GS VS g o = di W = µ n Ĉ ox dv S VGS L ( ) W = µ n Ĉ ox ( L V V GS T )( 1+ λv S ), V GS V T,V S V S,sat ( V GS V T ) λ, V GS V T,V S V S,sat MOSFET epletion Capacitances: MOSFET Overlap Capacitances: MOSFET Intrinsic Capacitances: MOSFET Velocity Saturation Model: MOSFET Current with Vel. Sat. : C! C SB = depsw P S 1+V SB V bisb ( ) z SB C GS,ovl = C G,ovl = ε ox x ovl W t ox C GS = ( 3 C " * V ox 1 GS V T * $ # V GS V ) T µ v = 0 ε 1+ε ε crit W I = µ n Ĉ ox L 1+V S Ĉ + depbot A S 1+V SB V bisb ( ) z SB ( ) V S ( ) V S Lε crit ( ( )) C!, C B = depsw P 1+V B V bib ( ) z B % + - ' & -, C G = ( 3 C " * V ox 1 GS V T * $ V, # GS V ) T ( ) ( ) V S Ĉ + depbot A 1+V B V bib ( ) z B % + - ' & - for V S V S,sat, "( V GS V T ) % $ # '( 1+ λv S ), V GS V T,V S V S,sat &
20 ELEC 3908 SELECTE FINAL EXAMINATION QUESTIONS Page 0 Physical Constants and Material Properties Quantity Symbol Value Micron µm 10-4 cm = 10-6 m Angstrom Unit Å 10-8 cm = m Boltzmann s Constant k 8.6x10-5 ev/k 1.381x10-3 J/K Electronic Charge q 1.60x10-19 C Electron Volt ev 1.60x10-19 J Electron Rest Mass m o 9.11x10-31 kg Free Space Permittivity ε o 8.854x10-14 F/cm Plank s Constant h 6.66x J-s 4.14x10-15 ev-s Thermal Voltage at 300K 1kT/q V Properties of Silicon at 300K Quantity Symbol Value Intrinsic Carrier Concentration n i 1.45x10 10 cm -3 Effective ensities of States N v 1.08x10 19 cm -3 N c.8x10 19 cm -3 Electron Affinity χ Si 4.05 ev Energy Gap E g 1.08 ev Bulk Electron Mobility µ n 1350 cm /V-s Bulk Hole Mobility µ p 470 cm /V-s Surface Electron Mobility µ n 50 cm /V-s Permittivity ε Si 11.7ε o Properties of Silicon ioxide Quantity Symbol Value Permittivity ε ox 3.9ε o
Quiz #1 Practice Problem Set
Name: Student Number: ELEC 3908 Physical Electronics Quiz #1 Practice Problem Set? Minutes January 22, 2016 - No aids except a non-programmable calculator - All questions must be answered - All questions
More informationFIELD-EFFECT TRANSISTORS
FIEL-EFFECT TRANSISTORS 1 Semiconductor review 2 The MOS capacitor 2 The enhancement-type N-MOS transistor 3 I-V characteristics of enhancement MOSFETS 4 The output characteristic of the MOSFET in saturation
More informationSection 12: Intro to Devices
Section 12: Intro to Devices Extensive reading materials on reserve, including Robert F. Pierret, Semiconductor Device Fundamentals Bond Model of Electrons and Holes Si Si Si Si Si Si Si Si Si Silicon
More informationThe Devices. Digital Integrated Circuits A Design Perspective. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic. July 30, 2002
igital Integrated Circuits A esign Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic The evices July 30, 2002 Goal of this chapter Present intuitive understanding of device operation Introduction
More informationFinal Examination EE 130 December 16, 1997 Time allotted: 180 minutes
Final Examination EE 130 December 16, 1997 Time allotted: 180 minutes Problem 1: Semiconductor Fundamentals [30 points] A uniformly doped silicon sample of length 100µm and cross-sectional area 100µm 2
More informationSpring Semester 2012 Final Exam
Spring Semester 2012 Final Exam Note: Show your work, underline results, and always show units. Official exam time: 2.0 hours; an extension of at least 1.0 hour will be granted to anyone. Materials parameters
More informationELEC 3908, Physical Electronics, Lecture 26. MOSFET Small Signal Modelling
ELEC 3908, Physical Electronics, Lecture 26 MOSFET Small Signal Modelling Lecture Outline MOSFET small signal behavior will be considered in the same way as for the diode and BJT Capacitances will be considered
More informationAppendix 1: List of symbols
Appendix 1: List of symbols Symbol Description MKS Units a Acceleration m/s 2 a 0 Bohr radius m A Area m 2 A* Richardson constant m/s A C Collector area m 2 A E Emitter area m 2 b Bimolecular recombination
More informationThe Devices. Jan M. Rabaey
The Devices Jan M. Rabaey Goal of this chapter Present intuitive understanding of device operation Introduction of basic device equations Introduction of models for manual analysis Introduction of models
More informationELEC 3908, Physical Electronics, Lecture 19. BJT Base Resistance and Small Signal Modelling
ELEC 3908, Physical Electronics, Lecture 19 BJT Base Resistance and Small Signal Modelling Lecture Outline Lecture 17 derived static (dc) injection model to predict dc currents from terminal voltages This
More information6.012 Electronic Devices and Circuits
Page 1 of 12 YOUR NAME Department of Electrical Engineering and Computer Science Massachusetts Institute of Technology 6.012 Electronic Devices and Circuits FINAL EXAMINATION Open book. Notes: 1. Unless
More informationELEC 3908, Physical Electronics, Lecture 23. The MOSFET Square Law Model
ELEC 3908, Physical Electronics, Lecture 23 The MOSFET Square Law Model Lecture Outline As with the diode and bipolar, have looked at basic structure of the MOSFET and now turn to derivation of a current
More informationSemiconductor Physics Problems 2015
Semiconductor Physics Problems 2015 Page and figure numbers refer to Semiconductor Devices Physics and Technology, 3rd edition, by SM Sze and M-K Lee 1. The purest semiconductor crystals it is possible
More informationSection 12: Intro to Devices
Section 12: Intro to Devices Extensive reading materials on reserve, including Robert F. Pierret, Semiconductor Device Fundamentals EE143 Ali Javey Bond Model of Electrons and Holes Si Si Si Si Si Si Si
More informationSemiconductor Physics fall 2012 problems
Semiconductor Physics fall 2012 problems 1. An n-type sample of silicon has a uniform density N D = 10 16 atoms cm -3 of arsenic, and a p-type silicon sample has N A = 10 15 atoms cm -3 of boron. For each
More informationThe Devices. Digital Integrated Circuits A Design Perspective. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic. July 30, 2002
Digital Integrated Circuits A Design Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic The Devices July 30, 2002 Goal of this chapter Present intuitive understanding of device operation Introduction
More informationThe Devices: MOS Transistors
The Devices: MOS Transistors References: Semiconductor Device Fundamentals, R. F. Pierret, Addison-Wesley Digital Integrated Circuits: A Design Perspective, J. Rabaey et.al. Prentice Hall NMOS Transistor
More informationLecture 04 Review of MOSFET
ECE 541/ME 541 Microelectronic Fabrication Techniques Lecture 04 Review of MOSFET Zheng Yang (ERF 3017, email: yangzhen@uic.edu) What is a Transistor? A Switch! An MOS Transistor V GS V T V GS S Ron D
More informationDevice Models (PN Diode, MOSFET )
Device Models (PN Diode, MOSFET ) Instructor: Steven P. Levitan steve@ece.pitt.edu TA: Gayatri Mehta, José Martínez Book: Digital Integrated Circuits: A Design Perspective; Jan Rabaey Lab Notes: Handed
More informationUNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences. Professor Chenming Hu.
UNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences EECS 130 Spring 2009 Professor Chenming Hu Midterm I Name: Closed book. One sheet of notes is
More informationECE-342 Test 2 Solutions, Nov 4, :00-8:00pm, Closed Book (one page of notes allowed)
ECE-342 Test 2 Solutions, Nov 4, 2008 6:00-8:00pm, Closed Book (one page of notes allowed) Please use the following physical constants in your calculations: Boltzmann s Constant: Electron Charge: Free
More informationMetal-oxide-semiconductor field effect transistors (2 lectures)
Metal-ide-semiconductor field effect transistors ( lectures) MOS physics (brief in book) Current-voltage characteristics - pinch-off / channel length modulation - weak inversion - velocity saturation -
More informationEECS130 Integrated Circuit Devices
EECS130 Integrated Circuit Devices Professor Ali Javey 9/18/2007 P Junctions Lecture 1 Reading: Chapter 5 Announcements For THIS WEEK OLY, Prof. Javey's office hours will be held on Tuesday, Sept 18 3:30-4:30
More information1. The MOS Transistor. Electrical Conduction in Solids
Electrical Conduction in Solids!The band diagram describes the energy levels for electron in solids.!the lower filled band is named Valence Band.!The upper vacant band is named conduction band.!the distance
More informationIntegrated Circuits & Systems
Federal University of Santa Catarina Center for Technology Computer Science & Electronics Engineering Integrated Circuits & Systems INE 5442 Lecture 10 MOSFET part 1 guntzel@inf.ufsc.br ual-well Trench-Isolated
More informationMOSFET: Introduction
E&CE 437 Integrated VLSI Systems MOS Transistor 1 of 30 MOSFET: Introduction Metal oxide semiconductor field effect transistor (MOSFET) or MOS is widely used for implementing digital designs Its major
More informationDevice Models (PN Diode, MOSFET )
Device Models (PN Diode, MOSFET ) Instructor: Steven P. Levitan steve@ece.pitt.edu TA: Gayatri Mehta, José Martínez Book: Digital Integrated Circuits: A Design Perspective; Jan Rabaey Lab Notes: Handed
More informationUNIVERSITY OF CALIFORNIA, BERKELEY College of Engineering Department of Electrical Engineering and Computer Sciences
UNIVERSITY OF CALIFORNIA, BERKELEY College of Engineering Department of Electrical Engineering and Computer Sciences EE 105: Microelectronic Devices and Circuits Spring 2008 MIDTERM EXAMINATION #1 Time
More informationLecture 12: MOS Capacitors, transistors. Context
Lecture 12: MOS Capacitors, transistors Context In the last lecture, we discussed PN diodes, and the depletion layer into semiconductor surfaces. Small signal models In this lecture, we will apply those
More informationLecture 12: MOSFET Devices
Lecture 12: MOSFET Devices Gu-Yeon Wei Division of Engineering and Applied Sciences Harvard University guyeon@eecs.harvard.edu Wei 1 Overview Reading S&S: Chapter 5.1~5.4 Supplemental Reading Background
More informationDigital Integrated Circuits A Design Perspective. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic. The Devices. July 30, Devices.
Digital Integrated Circuits A Design Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic The July 30, 2002 1 Goal of this chapter Present intuitive understanding of device operation Introduction
More informationThe Devices. Devices
The The MOS Transistor Gate Oxyde Gate Source n+ Polysilicon Drain n+ Field-Oxyde (SiO 2 ) p-substrate p+ stopper Bulk Contact CROSS-SECTION of NMOS Transistor Cross-Section of CMOS Technology MOS transistors
More informationELEC 3908, Physical Electronics, Lecture 13. Diode Small Signal Modeling
ELEC 3908, Physical Electronics, Lecture 13 iode Small Signal Modeling Lecture Outline Last few lectures have dealt exclusively with modeling and important effects in static (dc) operation ifferent modeling
More information1 Name: Student number: DEPARTMENT OF PHYSICS AND PHYSICAL OCEANOGRAPHY MEMORIAL UNIVERSITY OF NEWFOUNDLAND. Fall :00-11:00
1 Name: DEPARTMENT OF PHYSICS AND PHYSICAL OCEANOGRAPHY MEMORIAL UNIVERSITY OF NEWFOUNDLAND Final Exam Physics 3000 December 11, 2012 Fall 2012 9:00-11:00 INSTRUCTIONS: 1. Answer all seven (7) questions.
More informationChapter 7. The pn Junction
Chapter 7 The pn Junction Chapter 7 PN Junction PN junction can be fabricated by implanting or diffusing donors into a P-type substrate such that a layer of semiconductor is converted into N type. Converting
More informationQuiz #3 Practice Problem Set
Name: Studet Number: ELEC 3908 Physical Electroics Quiz #3 Practice Problem Set? Miutes March 11, 2016 - No aids excet a o-rogrammable calculator - ll questios must be aswered - ll questios have equal
More informationECEN 3320 Semiconductor Devices Final exam - Sunday December 17, 2000
Your Name: ECEN 3320 Semiconductor Devices Final exam - Sunday December 17, 2000 1. Review questions a) Illustrate the generation of a photocurrent in a p-n diode by drawing an energy band diagram. Indicate
More informationFor the following statements, mark ( ) for true statement and (X) for wrong statement and correct it.
Benha University Faculty of Engineering Shoubra Electrical Engineering Department First Year communications. Answer all the following questions Illustrate your answers with sketches when necessary. The
More informationElectrical Characteristics of MOS Devices
Electrical Characteristics of MOS Devices The MOS Capacitor Voltage components Accumulation, Depletion, Inversion Modes Effect of channel bias and substrate bias Effect of gate oide charges Threshold-voltage
More informationMOS Transistors. Prof. Krishna Saraswat. Department of Electrical Engineering Stanford University Stanford, CA
MOS Transistors Prof. Krishna Saraswat Department of Electrical Engineering S Stanford, CA 94305 saraswat@stanford.edu 1 1930: Patent on the Field-Effect Transistor! Julius Lilienfeld filed a patent describing
More informationECE 305 Fall Final Exam (Exam 5) Wednesday, December 13, 2017
NAME: PUID: ECE 305 Fall 017 Final Exam (Exam 5) Wednesday, December 13, 017 This is a closed book exam. You may use a calculator and the formula sheet at the end of this exam. Following the ECE policy,
More informationEE 560 MOS TRANSISTOR THEORY
1 EE 560 MOS TRANSISTOR THEORY PART 1 TWO TERMINAL MOS STRUCTURE V G (GATE VOLTAGE) 2 GATE OXIDE SiO 2 SUBSTRATE p-type doped Si (N A = 10 15 to 10 16 cm -3 ) t ox V B (SUBSTRATE VOLTAGE) EQUILIBRIUM:
More informationUNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences. EECS 130 Professor Ali Javey Fall 2006
UNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences EECS 130 Professor Ali Javey Fall 2006 Midterm 2 Name: SID: Closed book. Two sheets of notes are
More informationElectronic Circuits 1. Transistor Devices. Contents BJT and FET Characteristics Operations. Prof. C.K. Tse: Transistor devices
Electronic Circuits 1 Transistor Devices Contents BJT and FET Characteristics Operations 1 What is a transistor? Three-terminal device whose voltage-current relationship is controlled by a third voltage
More informationELEC 3908, Physical Electronics, Lecture 18. The Early Effect, Breakdown and Self-Heating
ELEC 3908, Physical Electronics, Lecture 18 The Early Effect, Breakdown and Self-Heating Lecture Outline Previous 2 lectures analyzed fundamental static (dc) carrier transport in the bipolar transistor
More informationExtensive reading materials on reserve, including
Section 12: Intro to Devices Extensive reading materials on reserve, including Robert F. Pierret, Semiconductor Device Fundamentals EE143 Ali Javey Bond Model of Electrons and Holes Si Si Si Si Si Si Si
More informationGEORGIA INSTITUTE OF TECHNOLOGY School of Electrical and Computer Engineering
NAME: GEORGIA INSTITUTE OF TECHNOLOGY School of Electrical and Computer Engineering ECE 4430 First Exam Closed Book and Notes Fall 2002 September 27, 2002 General Instructions: 1. Write on one side of
More information6.012 Electronic Devices and Circuits Spring 2005
6.012 Electronic Devices and Circuits Spring 2005 May 16, 2005 Final Exam (200 points) -OPEN BOOK- Problem NAME RECITATION TIME 1 2 3 4 5 Total General guidelines (please read carefully before starting):
More informationInstitute of Solid State Physics. Technische Universität Graz. Exam. Feb 2, 10:00-11:00 P2
Technische Universität Graz nstitute of Solid State Physics Exam Feb 2, 10:00-11:00 P2 Exam Four questions, two from the online list. Calculator is ok. No notes. Explain some concept: (tunnel contact,
More informationFundamentals of the Metal Oxide Semiconductor Field-Effect Transistor
Triode Working FET Fundamentals of the Metal Oxide Semiconductor Field-Effect Transistor The characteristics of energy bands as a function of applied voltage. Surface inversion. The expression for the
More informationSchottky Rectifiers Zheng Yang (ERF 3017,
ECE442 Power Semiconductor Devices and Integrated Circuits Schottky Rectifiers Zheng Yang (ERF 3017, email: yangzhen@uic.edu) Power Schottky Rectifier Structure 2 Metal-Semiconductor Contact The work function
More informationDevices. chapter Introduction. 1.2 Silicon Conductivity
chapter 1 Devices 1.1 Introduction The properties and performance of analog bicmos integrated circuits are dependent on the devices used to construct them. This chapter is a review of the operation of
More informationEE5311- Digital IC Design
EE5311- Digital IC Design Module 1 - The Transistor Janakiraman V Assistant Professor Department of Electrical Engineering Indian Institute of Technology Madras Chennai October 28, 2017 Janakiraman, IITM
More informationCMPEN 411 VLSI Digital Circuits. Lecture 03: MOS Transistor
CMPEN 411 VLSI Digital Circuits Lecture 03: MOS Transistor Kyusun Choi [Adapted from Rabaey s Digital Integrated Circuits, Second Edition, 2003 J. Rabaey, A. Chandrakasan, B. Nikolic] CMPEN 411 L03 S.1
More informationLecture 15 OUTLINE. MOSFET structure & operation (qualitative) Review of electrostatics The (N)MOS capacitor
Lecture 15 OUTLINE MOSFET structure & operation (qualitative) Review of electrostatics The (N)MOS capacitor Electrostatics Charge vs. voltage characteristic Reading: Chapter 6.1 6.2.1 EE15 Spring 28 Lecture
More informationIntroduction to Power Semiconductor Devices
ECE442 Power Semiconductor Devices and Integrated Circuits Introduction to Power Semiconductor Devices Zheng Yang (ERF 3017, email: yangzhen@uic.edu) Power Semiconductor Devices Applications System Ratings
More informationClass 05: Device Physics II
Topics: 1. Introduction 2. NFET Model and Cross Section with Parasitics 3. NFET as a Capacitor 4. Capacitance vs. Voltage Curves 5. NFET as a Capacitor - Band Diagrams at V=0 6. NFET as a Capacitor - Accumulation
More informationDevice Physics: The Bipolar Transistor
Monolithic Amplifier Circuits: Device Physics: The Bipolar Transistor Chapter 4 Jón Tómas Guðmundsson tumi@hi.is 2. Week Fall 2010 1 Introduction In analog design the transistors are not simply switches
More informationMOS Transistor I-V Characteristics and Parasitics
ECEN454 Digital Integrated Circuit Design MOS Transistor I-V Characteristics and Parasitics ECEN 454 Facts about Transistors So far, we have treated transistors as ideal switches An ON transistor passes
More informationLecture 15 OUTLINE. MOSFET structure & operation (qualitative) Review of electrostatics The (N)MOS capacitor
Lecture 15 OUTLINE MOSFET structure & operation (qualitative) Review of electrostatics The (N)MOS capacitor Electrostatics t ti Charge vs. voltage characteristic Reading: Chapter 6.1 6.2.1 EE105 Fall 2007
More information6.012 Electronic Devices and Circuits
Page 1 of 10 YOUR NAME Department of Electrical Engineering and Computer Science Massachusetts Institute of Technology 6.012 Electronic Devices and Circuits Exam No. 2 Thursday, November 5, 2009 7:30 to
More informationMOS CAPACITOR AND MOSFET
EE336 Semiconductor Devices 1 MOS CAPACITOR AND MOSFET Dr. Mohammed M. Farag Ideal MOS Capacitor Semiconductor Devices Physics and Technology Chapter 5 EE336 Semiconductor Devices 2 MOS Capacitor Structure
More informationLecture 16 The pn Junction Diode (III)
Lecture 16 The pn Junction iode (III) Outline I V Characteristics (Review) Small signal equivalent circuit model Carrier charge storage iffusion capacitance Reading Assignment: Howe and Sodini; Chapter
More informationCourse Administration. CPE/EE 427, CPE 527 VLSI Design I L04: MOS Transistors. Review: CMOS Process at a Glance
Course Administration CPE/EE 7, CPE 7 VLI esign I L: MO Transistors epartment of Electrical and Computer Engineering University of Alabama in Huntsville Aleksandar Milenkovic ( www.ece.uah.edu/~milenka
More informationMemories Bipolar Transistors
Technische Universität Graz nstitute of Solid State Physics Memories Bipolar Transistors Technische Universität Graz nstitute of Solid State Physics Exams February 5 March 7 April 18 June 27 Exam Four
More informationLecture 15: MOS Transistor models: Body effects, SPICE models. Context. In the last lecture, we discussed the modes of operation of a MOS FET:
Lecture 15: MOS Transistor models: Body effects, SPICE models Context In the last lecture, we discussed the modes of operation of a MOS FET: oltage controlled resistor model I- curve (Square-Law Model)
More informationMidterm I - Solutions
UNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences EECS 130 Spring 2008 Professor Chenming Hu Midterm I - Solutions Name: SID: Grad/Undergrad: Closed
More informationSample Exam # 2 ECEN 3320 Fall 2013 Semiconductor Devices October 28, 2013 Due November 4, 2013
Sample Exam # 2 ECEN 3320 Fall 203 Semiconductor Devices October 28, 203 Due November 4, 203. Below is the capacitance-voltage curve measured from a Schottky contact made on GaAs at T 300 K. Figure : Capacitance
More informationGATE SOLVED PAPER - EC
03 ONE MARK Q. In a forward biased pn junction diode, the sequence of events that best describes the mechanism of current flow is (A) injection, and subsequent diffusion and recombination of minority carriers
More informationLecture 210 Physical Aspects of ICs (12/15/01) Page 210-1
Lecture 210 Physical Aspects of ICs (12/15/01) Page 210-1 LECTURE 210 PHYSICAL ASPECTS OF ICs (READING: Text-Sec. 2.5, 2.6, 2.8) INTRODUCTION Objective Illustrate the physical aspects of integrated circuits
More information6.012 Electronic Devices and Circuits
Page 1 of 1 YOUR NAME Department of Electrical Engineering and Computer Science Massachusetts Institute of Technology 6.12 Electronic Devices and Circuits Exam No. 1 Wednesday, October 7, 29 7:3 to 9:3
More informationChapter 4 Field-Effect Transistors
Chapter 4 Field-Effect Transistors Microelectronic Circuit Design Richard C. Jaeger Travis N. Blalock 5/5/11 Chap 4-1 Chapter Goals Describe operation of MOSFETs. Define FET characteristics in operation
More informationThe Intrinsic Silicon
The Intrinsic ilicon Thermally generated electrons and holes Carrier concentration p i =n i ni=1.45x10 10 cm-3 @ room temp Generally: n i = 3.1X10 16 T 3/2 e -1.21/2KT cm -3 T= temperature in K o (egrees
More informationVLSI Design I; A. Milenkovic 1
Review: implified CMO Inverter Process CPE/EE 7, CPE 7 VLI esign I L: MO Transistor cut line epartment of Electrical and Computer Engineering University of Alabama in Huntsville Aleksandar Milenkovic (
More informationLECTURE 3 MOSFETS II. MOS SCALING What is Scaling?
LECTURE 3 MOSFETS II Lecture 3 Goals* * Understand constant field and constant voltage scaling and their effects. Understand small geometry effects for MOS transistors and their implications modeling and
More informationIntroduction and Background
Analog CMOS Integrated Circuit Design Introduction and Background Dr. Jawdat Abu-Taha Department of Electrical and Computer Engineering Islamic University of Gaza jtaha@iugaza.edu.ps 1 Marking Assignments
More informationECE321 Electronics I
ECE321 Electronics I Lecture 4: Physics of Semiconductor iodes Payman Zarkesh-Ha Office: ECE Bldg. 230B Office hours: Tuesday 2:00-3:00PM or by appointment E-mail: pzarkesh.unm.edu Slide: 1 Review of Last
More informationan introduction to Semiconductor Devices
an introduction to Semiconductor Devices Donald A. Neamen Chapter 6 Fundamentals of the Metal-Oxide-Semiconductor Field-Effect Transistor Introduction: Chapter 6 1. MOSFET Structure 2. MOS Capacitor -
More informationECE-305: Spring 2018 Final Exam Review
C-305: Spring 2018 Final xam Review Pierret, Semiconductor Device Fundamentals (SDF) Chapters 10 and 11 (pp. 371-385, 389-403) Professor Peter Bermel lectrical and Computer ngineering Purdue University,
More informationCharge-Storage Elements: Base-Charging Capacitance C b
Charge-Storage Elements: Base-Charging Capacitance C b * Minority electrons are stored in the base -- this charge q NB is a function of the base-emitter voltage * base is still neutral... majority carriers
More informationSemiconductor Junctions
8 Semiconductor Junctions Almost all solar cells contain junctions between different materials of different doping. Since these junctions are crucial to the operation of the solar cell, we will discuss
More informationn N D n p = n i p N A
Summary of electron and hole concentration in semiconductors Intrinsic semiconductor: E G n kt i = pi = N e 2 0 Donor-doped semiconductor: n N D where N D is the concentration of donor impurity Acceptor-doped
More informationBJT - Mode of Operations
JT - Mode of Operations JTs can be modeled by two back-to-back diodes. N+ P N- N+ JTs are operated in four modes. HO #6: LN 251 - JT M Models Page 1 1) Forward active / normal junction forward biased junction
More informationPeak Electric Field. Junction breakdown occurs when the peak electric field in the PN junction reaches a critical value. For the N + P junction,
Peak Electric Field Junction breakdown occurs when the peak electric field in the P junction reaches a critical value. For the + P junction, qa E ( x) ( xp x), s W dep 2 s ( bi Vr ) 2 s potential barrier
More informationMetal Semiconductor Contacts
Metal Semiconductor Contacts The investigation of rectification in metal-semiconductor contacts was first described by Braun [33-35], who discovered in 1874 the asymmetric nature of electrical conduction
More informationSECTION: Circle one: Alam Lundstrom. ECE 305 Exam 5 SOLUTIONS: Spring 2016 April 18, 2016 M. A. Alam and M.S. Lundstrom Purdue University
NAME: PUID: SECTION: Circle one: Alam Lundstrom ECE 305 Exam 5 SOLUTIONS: April 18, 2016 M A Alam and MS Lundstrom Purdue University This is a closed book exam You may use a calculator and the formula
More informationECE 342 Electronic Circuits. Lecture 6 MOS Transistors
ECE 342 Electronic Circuits Lecture 6 MOS Transistors Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jesa@illinois.edu 1 NMOS Transistor Typically L = 0.1 to 3 m, W = 0.2
More informationLecture-4 Junction Diode Characteristics
1 Lecture-4 Junction Diode Characteristics Part-II Q: Aluminum is alloyed into n-type Si sample (N D = 10 16 cm 3 ) forming an abrupt junction of circular cross-section, with an diameter of 0.02 in. Assume
More informationESE 570: Digital Integrated Circuits and VLSI Fundamentals
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 4: January 23, 2018 MOS Transistor Theory, MOS Model Penn ESE 570 Spring 2018 Khanna Lecture Outline! CMOS Process Enhancements! Semiconductor
More informationMOSFET Physics: The Long Channel Approximation
MOSFET Physics: The ong Channel Approximation A basic n-channel MOSFET (Figure 1) consists of two heavily-doped n-type regions, the Source and Drain, that comprise the main terminals of the device. The
More informationLong Channel MOS Transistors
Long Channel MOS Transistors The theory developed for MOS capacitor (HO #2) can be directly extended to Metal-Oxide-Semiconductor Field-Effect transistors (MOSFET) by considering the following structure:
More informationMOS Transistor Properties Review
MOS Transistor Properties Review 1 VLSI Chip Manufacturing Process Photolithography: transfer of mask patterns to the chip Diffusion or ion implantation: selective doping of Si substrate Oxidation: SiO
More informationSemiconductor Devices. C. Hu: Modern Semiconductor Devices for Integrated Circuits Chapter 5
Semiconductor Devices C. Hu: Modern Semiconductor Devices for Integrated Circuits Chapter 5 Global leader in environmental and industrial measurement Wednesday 3.2. afternoon Tour around facilities & lecture
More informationLecture 6 PN Junction and MOS Electrostatics(III) Metal-Oxide-Semiconductor Structure
Lecture 6 PN Junction and MOS Electrostatics(III) Metal-Oxide-Semiconductor Structure Outline 1. Introduction to MOS structure 2. Electrostatics of MOS in thermal equilibrium 3. Electrostatics of MOS with
More informationLecture 11: MOS Transistor
Lecture 11: MOS Transistor Prof. Niknejad Lecture Outline Review: MOS Capacitors Regions MOS Capacitors (3.8 3.9) CV Curve Threshold Voltage MOS Transistors (4.1 4.3): Overview Cross-section and layout
More information12. Memories / Bipolar transistors
Technische Universität Graz Institute of Solid State Physics 12. Memories / Bipolar transistors Jan. 9, 2019 Technische Universität Graz Institute of Solid State Physics Exams January 31 March 8 May 17
More informationEE105 - Fall 2006 Microelectronic Devices and Circuits
EE105 - Fall 2006 Microelectronic Devices and Circuits Prof. Jan M. Rabaey (jan@eecs) Lecture 7: MOS Transistor Some Administrative Issues Lab 2 this week Hw 2 due on We Hw 3 will be posted same day MIDTERM
More informationSolid State Electronics. Final Examination
The University of Toledo EECS:4400/5400/7400 Solid State Electronic Section elssf08fs.fm - 1 Solid State Electronics Final Examination Problems Points 1. 1. 14 3. 14 Total 40 Was the exam fair? yes no
More informationProblem 9.20 Threshold bias for an n-channel MOSFET: In the text we used a criterion that the inversion of the MOSFET channel occurs when V s = ;2 F w
Prof. Jasprit Singh Fall 2001 EECS 320 Homework 11 The nals for this course are set for Friday December 14, 6:30 8:30 pm and Friday Dec. 21, 10:30 am 12:30 pm. Please choose one of these times and inform
More informationcollisions of electrons. In semiconductor, in certain temperature ranges the conductivity increases rapidly by increasing temperature
1.9. Temperature Dependence of Semiconductor Conductivity Such dependence is one most important in semiconductor. In metals, Conductivity decreases by increasing temperature due to greater frequency of
More information