ELEC 3908, Physical Electronics, Lecture 13. Diode Small Signal Modeling

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1 ELEC 3908, Physical Electronics, Lecture 13 iode Small Signal Modeling

2 Lecture Outline Last few lectures have dealt exclusively with modeling and important effects in static (dc) operation ifferent modeling strategy required for small signal operation linearized perturbation on dc operating point Two important parameters considered Conductance derivative of current with respect to potential Capacitance derivative of stored charge with respect to potential iode Small Signal Modeling Page 13-2

3 Review of Small Signal Operation Small signal operation refers to the analysis of the response of a network to a small perturbation superimposed on a dc bias condition Basic assumption about small signal operation is that signal levels are low enough that the operating point is not affected, e.g. a 50mV sinusoid on top of a 1V bias point input small signal perturbation source dc bias source t iode Small Signal Modeling Page 13-3

4 Review of Small Signal Response If the perturbation is small, the response of the network will be approximately linear even if the dependence on operating point is nonlinear (analogous to retaining only the linear term of a Taylor series) The nature of the response will in general be a function of operating point in the example shown to the right, the response (in red) at operating point 1 is different than at point 2 larger signal swing, for which the bias point changes, is a switching, or transient analysis will consider this in lecture 14 output 1 2 input iode Small Signal Modeling Page 13-4

5 Small Signal Conductance The rate of change of diode current with respect to junction potential is the conductance g qv nkt ( ) I = I e 1 S di q g dv nkt Ie qv nkt = = S q ( ) nkt I mhos I is a strong (exponential) function of V, so the slope of the I vs V relationship changes with V Conductance is therefore a function of operating point iode Small Signal Modeling Page 13-5

6 Example 13.1: Conductance What potential is required across a diode with I S = 5x10-11 and n=1.3 to give a conductance of 10 mmhos? Ignore parasitic (substrate) resistance. iode Small Signal Modeling Page 13-6

7 Example 13.1: Solution The current corresponding to this conductance is x10 = I I = 336. x The junction voltage is therefore V nkt = ln 1+ q I I V = ln 1+ S x10 11 = 053. V 510 x iode Small Signal Modeling Page 13-7

8 General Interpretation of Capacitance Capacitance is given (equivalently) as either the rate of change of charge with voltage, or the proportionality constant between current and the time rate of change of voltage C dq () t it C dv () =, ( ) = t dv() t dt The general meaning of capacitance is the requirement to supply or sink charge to change potential n ideal resistor has no capacitance - no q required for ΔV parallel plate structure stores charge, and hence requires addition or removal of q for ΔV, hence it has a non-zero C iode Small Signal Modeling Page 13-8

9 Capacitance Measurement In practice, capacitance is measured by applying a sinusoidal signal and measuring v(t)-i(t) phase difference For illustrative purposes in devices, view capacitance measurement as the characterisation of the q(t) required to support a small potential perturbation v(t) The constant potential V sets the operating point, and allows measurement as a function of operating point iode Small Signal Modeling Page 13-9

10 Physical Origin of epletion Capacitance The depletion width W is a function of the applied bias V W 2ε Si 1 1 = + q ( V V ) Changing V requires a change in W, and hence ρ capacitive effect is therefore present - the change in ρ must be supplied in order to change V Since the capacitive effect arises from the change in depletion width, it is termed depletion capacitance bi iode Small Signal Modeling Page 13-10

11 nalytic Model for epletion Capacitance etermine depletion capacitance using the chain rule ( V ) dqˆ ˆ dep dep = = dv C dqˆ dep dw dw dv Q associated with the positive V terminal is q x p, so the differential charge dq is formed by dqˆ dep dw = d ( q x ) dw p = q d dw + W = q + (the negative terminal could also be used with q x n and a negative sign since dq is being found) iode Small Signal Modeling Page 13-11

12 nalytic Model for epletion Capacitance (con t) The derivative of W with respect to V is dw d 2ε Si 1 2ε = dv dv q + The depletion capacitance is therefore Si ( V ) = bi V 2W q + Cˆ dep ( V ) = dqˆ dep dw dw dv = q + 1 2εSi + 2W q = ε W Si iode Small Signal Modeling Page 13-12

13 epletion Capacitance - Parallel Plate nalogy The form of the depletion capacitance expression suggests an analogy to a parallel plate structure ε Si $Cdep( V ) = WV ( ) The differential charges dq and -dq act as charge plates separated by a width W of material with permittivity ε Si iode Small Signal Modeling Page 13-13

14 Voltage ependence of epletion Capacitance Unlike a simple parallel plate structure, pn-junction depletion capacitance is a function of V through W(V ) s reverse bias increases, W increases, plate separation increases, so capacitance falls (and vice versa for forward bias) iode Small Signal Modeling Page 13-14

15 Voltage Characteristic of epletion Capacitance Example plot is for =10 16, =10 17 and =(50 μm) 2 epletion capacitance increases as V increases since W is becoming narrower The zero-bias depletion capacitance is the value at V =0 In simple model, depletion capacitance goes to inf. at V =V bi because W goes to 0. In practice, the depletion approximation breaks down at high bias, so the simple equation no longer applies iode Small Signal Modeling Page 13-15

16 Example 13.2: epletion Capacitance Constraint well diode is constructed from an implant doping of =4x10 18 /cm 3 and a well doping of =10 16 /cm 3. The 1 area is (100 μm) 2. What bias range is required to ensure that the depletion capacitance does not exceed 1.5pF? (iagram below is for reference, essentially a duplicate of that in the planar diode processing lecture. iode Small Signal Modeling Page 13-16

17 Example 13.2: Solution The built-in potential for this device is V bi = x 10. ln ( 145. x10 ) = 085. V From the specified maximum capacitance, the minimum W is (using in cm 2 ) ε Si C = W = x W dep ( ) x x = 69. x10 cm The corresponding maximum V (recall plot) is then W 2ε Si 1 1 = + q ( Vbi V ) V = 28. V iode Small Signal Modeling Page 13-17

18 Example 13.2: Solution (con t) The corresponding value of V is then W 2ε Si 1 1 = + q ( Vbi V ) V = 28. V If the specified value is the maximum allowable, V must be lower than 2.8V Characteristic generated for different values, but shows behavior of C dep as function of V iode Small Signal Modeling Page 13-18

19 Grading Coefficient and General Model For device modeling, C dep model written in different form First step is to rewrite W(V ) expression Si Si ( ) = + ( V V ) = + ( V ) WV 2ε 1 1 2ε 1 1 bi q q Then depletion capacitance can be written C$ dep ( V ) εsi εsi = = WV W 0 1 V V ( ) ( ) ( V V ) The is only valid for a uniform junction - for generality define the grading coefficient z and write $ ( ) C$ dep ( V ) = C dep bi ( 1 V V ) 0 bi z bi = bi C$ V bi dep 1 V ( ) 0 V V = W ( 0) 1 V bi bi iode Small Signal Modeling Page 13-19

20 Effect of Grading Coefficient For most structures the grading coefficient is between 1/2 and 1/3 The zero bias value is not affected by the value of z, but the nature of the voltage dependence is Characteristic to the right is for per unit area zero bias depletion capacitance of 10-8 F/cm 2, V bi =0.8 and area 75 μm 2 iode Small Signal Modeling Page 13-20

21 iode Small Signal Equivalent Circuit small signal equivalent circuit can be defined for the purpose of determining the response to a small signal perturbation The conductance and capacitance appear in parallel because both arise from the fundamental junction operation ote that the capacitance is C dep, not per unit area parasitic (substrate) resistance would appear in series with this equiv. cct. iode Small Signal Modeling Page 13-21

22 Lecture Summary Small signal equivalent circuit includes Conductance models low frequency current perturbation in response to voltage perturbation Capacitance models charge storage, and introduces frequency dependent impedance iode exhibits depletion capacitance associated with a parallel plate-like structure formed by conductive neutral regions on either side of depletion region Conductance and depletion capacitance are functions of bias, so the small signal equivalent circuit has to be constructed for a particular device from the bias point iode Small Signal Modeling Page 13-22

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