GATE SOLVED PAPER - EC

Transcription

1 03 ONE MARK Q. In a forward biased pn junction diode, the sequence of events that best describes the mechanism of current flow is (A) injection, and subsequent diffusion and recombination of minority carriers (B) injection, and subsequent drift and generation of minority carriers (C) extraction, and subsequent diffusion and generation of minority carriers (D) extraction, and subsequent drift and recombination of minority carriers Q. In IC technology, dry oxidation (using dry oxygen) as compared to wet oxidation (using steam or water vapor) produces (A) superior quality oxide with a higher growth rate (B) inferior quality oxide with a higher growth rate (C) inferior quality oxide with a lower growth rate (D) superior quality oxide with a lower growth rate Q. 3 In a MOSFET operating in the saturation region, the channel length modulation effect causes (A) an increase in the gate-source capacitance (B) a decrease in the transconductance (C) a decrease in the unity-gain cutoff frequency (D) a decrease in the output resistance 03 TWO MARKS Q. 4 The small-signal resistance (i.e., dvb/ did) in kw offered by the n-channel MOSFET M shown in the figure below, at a bias point of V B V is (device data for ' M: device transconductance parameter kn mnc0x^w/ Lh 40 mav /, threshold voltage V TN V, and neglect body effect and channel length modulation effects) (A).5 (B) 5 (C) 50 (D) 00

2 0 TWO MARKS 0 3 Q. 5 The source of a silicon ( n i 0 per cm ) n-channel MOS transistor has an area 9 of sqm m and a depth of m m. If the dopant density in the source is 0 /cm 3, the number of holes in the source region with the above volume is approximately (A) 0 7 (B) 00 (C) 0 (D) 0 Q. 6 In the CMOS circuit shown, electron and hole mobilities are equal, and M and M are equally sized. The device M is in the linear region if (A) V < in.875 V (B).875 V < V < 3.5 V (C) (D) 0 V > in in 3.5 V < Vin < 5V Common Data For Q. 7 and 8 In the three dimensional view of a silicon n-channel MOS transistor shown below, d 0 nm. The transistor is of width m m. The depletion width formed at every p-n junction is 0 nm. The relative permittivity of Si and SiO, respectively, are -.7 and 3.9, and e # 0 F/ m. Q. 7 The gate source overlap capacitance is approximately (A) 0.7 ff (B) 0.7 pf (C) 0.35 ff (D) 0.4 pf Q. 8 The source-body junction capacitance is approximately (A) ff (B) 7fF (C) pf (D) 7pF

3 0 ONE MARK Q. 9 Drift current in the semiconductors depends upon (A) only the electric field (B) only the carrier concentration gradient (C) both the electric field and the carrier concentration (D) both the electric field and the carrier concentration gradient Q. 0 A Zener diode, when used in voltage stabilization circuits, is biased in (A) reverse bias region below the breakdown voltage (B) reverse breakdown region (C) forward bias region (D) forward bias constant current mode Q. A silicon PN junction is forward biased with a constant current at room temperature. When the temperature is increased by 0ºC, the forward bias voltage across the PN junction (A) increases by 60 mv (B) decreases by 60 mv (C) increases by 5 mv (D) decreases by 5 mv 0 TWO MARKS Common Data For Q. and 3 The channel resistance of an N-channel JFET shown in the figure below is 600 W when the full channel thickness (t ch ) of 0 μm is available for conduction. The built-in voltage of the gate P + N junction (V bi ) is - V. When the gate to source voltage (V GS ) is 0 V, the channel is depleted by μm on each side due to the built in voltage and hence the thickness available for conduction is only 8 μm Q. The channel resistance when V GS - 3V is (A) 360 W (B) 97 W (C) 000 W (D) 3000 W Q. 3 The channel resistance when V GS 0V is (A) 480 W (B) 600 W (C) 750 W (D) 000 W

4 00 ONE MARK Q. 4 At room temperature, a possible value for the mobility of electrons in the inversion layer of a silicon n-channel MOSFET is (A) 450 cm / V-s (B) 350 cm / V-s (C) 800 cm / V-s (D) 3600 cm / V-s Q. 5 Thin gate oxide in a CMOS process in preferably grown using (A) wet oxidation (B) dry oxidation (C) epitaxial oxidation (D) ion implantation 00 TWO MARKS Q. 6 In a uniformly doped BJT, assume that NE, NB and N C are the emitter, base and collector doping in atoms/cm 3, respectively. If the emitter injection efficiency of the BJT is close unity, which one of the following condition is TRUE (A) NE NB NC (B) NE >> NB and NB > NC (C) NE NB and NB < NC (D) NE < NB < NC 4 3 Q. 7 Compared to a p-n junction with NA ND 0 /cm, which one of the following 0 3 statements is TRUE for a p-n junction with NA ND 0 /cm? (A) Reverse breakdown voltage is lower and depletion capacitance is lower (B) Reverse breakdown voltage is higher and depletion capacitance is lower (C) Reverse breakdown voltage is lower and depletion capacitance is higher (D) Reverse breakdown voltage is higher and depletion capacitance is higher Statements for Linked Answer Question : 8 and 9 The silicon sample with unit cross-sectional area shown below is in thermal equilibrium. The following information is given: T 300 K electronic charge -9.6 # 0 C, thermal voltage 6 mv and electron mobility 350 cm / V-s Q. 8 The magnitude of the electric field at x 0.5 mm is (A) kv/cm (B) 5 kv/cm (C) 0 kv/cm (D) 6 kv/cm Q. 9 The magnitude of the electron of the electron drift current density at x 0.5 mm is 4 (A).6 # 0 Acm / 4 (B).08 # 0 Am / 3 (C) 4.3 # 0 Acm / (D) 6.48 # 0 Acm /

5 009 ONE MARK Q. 0 In an n-type silicon crystal at room temperature, which of the following can have a concentration of 4# 0 9 cm - 3? (A) Silicon atoms (B) Holes (C) Dopant atoms (D) Valence electrons Q. The ratio of the mobility to the diffusion coefficient in a semiconductor has the units (A) V (B) cm.v (C) V. cm (D) Vs. 009 TWO MARKS Q. Consider the following two statements about the internal conditions in a n - channel MOSFET operating in the active region. S : The inversion charge decreases from source to drain S : The channel potential increases from source to drain. Which of the following is correct? (A) Only S is true (B) Both S and S are false (C) Both S and S are true, but S is not a reason for S (D) Both S and S are true, and S is a reason for S Common Data For Q. 3 and 4 Consider a silicon p- n junction at room temperature having the following parameters: Doping on the n-side # 0 7 cm -3 Depletion width on the n-side 0m. m Depletion width on the p -side 0m. m Intrinsic carrier concentration 4. # 0 0 cm -3 Thermal voltage 6 mv - Permittivity of free space 885. # 0 4 F.cm - Dielectric constant of silicon Q. 3 The built-in potential of the junction (A) is 0.70 V (B) is 0.76 V (C) is 0.8 V (D) Cannot be estimated from the data given Q. 4 The peak electric field in the device is (A) 0.5 MV. cm -, directed from p -region to n -region (B) 0.5 MV. cm -, directed from n -region to p -region (C) 80. MV. cm -, directed from p-region to n -region (D).80 MV. cm -, directed from n -region to p -region

6 008 ONE MARK Q. 5 Which of the following is NOT associated with a p- n junction? (A) Junction Capacitance (B) Charge Storage Capacitance (C) Depletion Capacitance (D) Channel Length Modulations Q. 6 Which of the following is true? (A) A silicon wafer heavily doped with boron is a p + substrate (B) A silicon wafer lightly doped with boron is a p + substrate (C) A silicon wafer heavily doped with arsenic is a p + substrate (D) A silicon wafer lightly doped with arsenic is a p + substrate Q. 7 A silicon wafer has 00 nm of oxide on it and is furnace at a temperature above 000c C for further oxidation in dry oxygen. The oxidation rate (A) is independent of current oxide thickness and temperature (B) is independent of current oxide thickness but depends on temperature (C) slows down as the oxide grows (D) is zero as the existing oxide prevents further oxidation Q. 8 The drain current of MOSFET in saturation is given by I K( V - V ) where K is a constant. The magnitude of the transconductance g m is KV ( - V) (A) VDS (C) Id V - V GS GS T DS (B) KV ( - V) (D) GS T KV ( - V) V GS T GS D GS T 008 TWO MARKS Q. 9 The measured trans conductance g m of an NMOS transistor operating in the linear region is plotted against the gate voltage V G at a constant drain voltage V D. Which of the following figures represents the expected dependence of g m on V G? Q. 30 Silicon is doped with boron to a concentration of 4# 0 7 atoms cm 3. Assume the intrinsic carrier concentration of silicon to be 5. # 0 0 / cm 3 and the value of kt/ q to be 5 mv at 300 K. Compared to undopped silicon, the fermi level of doped silicon (A) goes down by 0.3 ev (B) goes up by 0.3 ev (C) goes down by 0.47 ev (D) goes up by 0.47 ev

7 Q. 3 The cross section of a JFET is shown in the following figure. Let V c be - V and let V P be the initial pinch -off voltage. If the width W is doubled (with other geometrical parameters and doping levels remaining the same), then the ratio between the mutual trans conductances of the initial and the modified JFET is (A) 4 (B) - / Vp (C) e o (D) - / V p - / Vp e o - / Vp -( - Vp ) - [ ( V )] p Q. 3 Consider the following assertions. S : For Zener effect to occur, a very abrupt junction is required. S : For quantum tunneling to occur, a very narrow energy barrier is required. Which of the following is correct? (A) Only S is true (B) S and S are both true but S is not a reason for S (C) S and S and are both true but S is not a reason for S (D) Both S and S are false 007 ONE MARK Q. 33 The electron and hole concentrations in an intrinsic semiconductor are n i per cm 3 at 300 K. Now, if acceptor impurities are introduced with a concentration of N A per cm 3 (where NA>> ni, the electron concentration per cm 3 at 300 K will be) (A) n i (B) ni+ NA (C) N - n (D) ni N A i + Q. 34 In a p n junction diode under reverse biased the magnitude of electric field is maximum at (A) the edge of the depletion region on the p-side (B) the edge of the depletion region on the n-side + (C) the p n junction (D) the centre of the depletion region on the n-side A 007 TWO MARKS Q. 35 Group I lists four types of p- n junction diodes. Match each device in Group I with one of the option in Group II to indicate the bias condition of the device in its normal mode of operation. Group - I Group-II (P) Zener Diode () Forward bias

8 (Q) Solar cell () Reverse bias (R) LASER diode (S) Avalanche Photodiode (A) P -, Q -, R -, S - (B) P -, Q -, R -, S - (C) P -, Q -, R -, S- - (D) P -, Q -, R -, S - Q. 36 Group I lists four different semiconductor devices. match each device in Group I with its charactecteristic property in Group II Group-I Group-II (P) BJT () Population iniversion (Q) MOS capacitor () Pinch-off voltage (R) LASER diode (3) Early effect (S) JFET (4) Flat-band voltage (A) P - 3, Q -, R - 4, S - (B) P -, Q - 4, R - 3, S - (C) P - 3, Q - 4, R -, S - (D) P - 3, Q -, R -, S - 4 Q A p n junction has a built-in potential of 0.8 V. The depletion layer width a reverse bias of. V is mm. For a reverse bias of 7. V, the depletion layer width will be (A) 4 mm (B) 4.9 mm (C) 8 mm (D) mm Q. 38 The DC current gain ( b ) of a BJT is 50. Assuming that the emitter injection efficiency is 0.995, the base transport factor is (A) (B) (C) (D) Common Data For Q. 39 to 4 The figure shows the high-frequency capacitance - voltage characteristics of Metal/Sio/silicon (MOS) capacitor having an area of # 0-4 cm. Assume that the permittivities ( ee 0 r ) of silicon and Sio are # 0 - F/cm and 35. # 0-3 F/ cm respectively. Q. 39 The gate oxide thickness in the MOS capacitor is (A) 50 nm (B) 43 nm (C) 350 nm (D) mm

9 Q. 40 The maximum depletion layer width in silicon is (A) 0.43 mm (B) mm (C) mm (D).43 mm Q. 4 Consider the following statements about the C- V characteristics plot : S : The MOS capacitor has as n-type substrate S : If positive charges are introduced in the oxide, the C- V polt will shift to the left. Then which of the following is true? (A) Both S and S are true (B) S is true and S is false (C) S is false and S is true (D) Both S and S are false 006 ONE MARK Q. 4 The values of voltage ( V D ) across a tunnel-diode corresponding to peak and valley currents are V p, V D respectively. The range of tunnel-diode voltage for V D which the slope of its I- V D characteristics is negative would be (A) VD < 0 (B) 0 # VD < Vp (C) V # V < V (D) V $ V p D v Q. 43 The concentration of minority carriers in an extrinsic semiconductor under equilibrium is (A) Directly proportional to doping concentration (B) Inversely proportional to the doping concentration (C) Directly proportional to the intrinsic concentration (D) Inversely proportional to the intrinsic concentration Q. 44 Under low level injection assumption, the injected minority carrier current for an extrinsic semiconductor is essentially the (A) Diffusion current (B) Drift current (C) Recombination current (D) Induced current Q. 45 The phenomenon known as Early Effect in a bipolar transistor refers to a reduction of the effective base-width caused by (A) Electron - hole recombination at the base (B) The reverse biasing of the base - collector junction (C) The forward biasing of emitter-base junction (D) The early removal of stored base charge during saturation-to-cut off switching D v 006 TWO MARKS Q. 46 In the circuit shown below, the switch was connected to position at t < 0 and at t 0, it is changed to position. Assume that the diode has zero voltage drop and a storage time t s. For 0 t # t, v is given by (all in Volts) < s R

10 (A) vr - 5 (B) vr + 5 (C) 0 # v < 5 (D) -5 # v < 0 R Q. 47 The majority carriers in an n-type semiconductor have an average drift velocity v in a direction perpendicular to a uniform magnetic field B. The electric field E induced due to Hall effect acts in the direction (A) v# B (B) B# v (C) along v (D) opposite to v Q. 48 Find the correct match between Group and Group Group Group E - Varactor diode. Voltage reference F - PIN diode. High frequency switch G - Zener diode 3. Tuned circuits H - Schottky diode 4. Current controlled attenuator (A) E - 4, F -, G -, H - 3 (B) E - 3, F - 4, G -, H - 3 (C) E -, F - 4, G -, H - (D) E -, F - 3, G -, H - 4 Q. 49 A heavily doped n- type semiconductor has the following data: Hole-electron ratio : 04. Doping concentration : 4. # 0 8 atoms/m 3 Intrinsic concentration : 5. # 0 4 atoms/m 3 The ratio of conductance of the n -type semiconductor to that of the intrinsic semiconductor of same material and ate same temperature is given by (A) (B) 000 (C) 0000 (D) 0000 R 005 ONE MARK Q. 50 The bandgap of Silicon at room temperature is (A).3 ev (B) 0.7 ev (C). ev (D).4 ev Q. 5 A Silicon PN junction at a temperature of 0c C has a reverse saturation current of 0 pico - Ameres (pa). The reserve saturation current at 40cC for the same bias is approximately (A) 30 pa (B) 40 pa (C) 50 pa (D) 60 pa Q. 5 The primary reason for the widespread use of Silicon in semiconductor device technology is (A) abundance of Silicon on the surface of the Earth.

11 (B) larger bandgap of Silicon in comparison to Germanium. (C) favorable properties of Silicon - dioxide (SiO ) (D) lower melting point 005 TWO MARKS Q. 53 A Silicon sample A is doped with 0 8 atoms/cm 3 of boron. Another sample B of identical dimension is doped with 0 8 atoms/cm 3 phosphorus. The ratio of electron to hole mobility is 3. The ratio of conductivity of the sample A to B is (A) 3 (B) 3 (C) 3 (D) 3 Q. 54 A Silicon PN junction diode under reverse bias has depletion region of width 0 mm. The relative permittivity of Silicon, e r. 7 and the permittivity of free - space e # 0 F/m. The depletion capacitance of the diode per square meter is (A) 00 mf (B) 0 mf (C) mf (D) 0 mf Q. 55 A MOS capacitor made using p type substrate is in the accumulation mode. The dominant charge in the channel is due to the presence of (A) holes (B) electrons (C) positively charged icons (D) negatively charged ions Q. 56 For an n-channel MOSFET and its transfer curve shown in the figure, the threshold voltage is (A) V and the device is in active region (B) - V and the device is in saturation region (C) V and the device is in saturation region (D) - V and the device is an active region 004 ONE MARK Q. 57 The impurity commonly used for realizing the base region of a silicon n-p- n transistor is (A) Gallium (B) Indium (C) Boron (D) Phosphorus Q. 58 If for a silicon npn transistor, the base-to-emitter voltage ( V BE ) is 0.7 V and the collector-to-base voltage ( V CB ) is 0. V, then the transistor is operating in the (A) normal active mode (B) saturation mode (C) inverse active mode (D) cutoff mode

12 Q. 59 Consider the following statements S and S. S : The b of a bipolar transistor reduces if the base width is increased. S : The b of a bipolar transistor increases if the dopoing concentration in the base is increased. Which remarks of the following is correct? (A) S is FALSE and S is TRUE (B) Both S and S are TRUE (C) Both S and S are FALSE (D) S is TRUE and S is FALSE Q. 60 Given figure is the voltage transfer characteristic of (A) an NOMS inverter with enhancement mode transistor as load (B) an NMOS inverter with depletion mode transistor as load (C) a CMOS inverter (D) a BJT inverter Q. 6 Assuming V CEsat 0. V and b 50, the minimum base current ( I B ) required to drive the transistor in the figure to saturation is (A) 56 ma (C) 60 ma (B) 40 ma (D) 3 ma 004 TWO MARKS Q. 6 In an abrupt p- n junction, the doping concentrations on the p -side and n-side 6 are NA 9# 0 /cm 3 respectively. The p- n junction is reverse biased and the total depletion width is 3 mm. The depletion width on the p -side is (A).7 mm (B) 0.3 mm (C).5 mm (D) 0.75 mm Q. 63 The resistivity of a uniformly doped n -type silicon sample is 05W. - mc. If the electron mobility ( m n ) is 50 cm /V-sec and the charge of an electron is 6. # 0-9 Coulomb, the donor impurity concentration ( N D ) in the sample is (A) # 0 6 /cm 3 (B) # 0 6 /cm 3 (C) 5. # 0 5 /cm 3 (D) 5# 0 5 /cm 3

13 Q. 64 Consider an abrupt p- n junction. Let V bi be the built-in potential of this junction and V R be the applied reverse bias. If the junction capacitance ( C j ) is pf for Vbi + VR V, then for Vbi + VR 4 V, C j will be (A) 4 pf (B) pf (C) 0.5 pf (D) 0.5 pf Q. 65 Consider the following statements Sq and S. S : The threshold voltage ( V T ) of MOS capacitor decreases with increase in gate oxide thickness. S : The threshold voltage ( V T ) of a MOS capacitor decreases with increase in substrate doping concentration. Which Marks of the following is correct? (A) S is FALSE and S is TRUE (B) Both S and S are TRUE (C) Both S and S are FALSE (D) S is TRUE and S is FALSE Q. 66 The drain of an n-channel MOSFET is shorted to the gate so that VGS VDS. The threshold voltage ( V T ) of the MOSFET is V. If the drain current ( I D ) is ma for VGS V, then for V GS 3 V, I D is (A) ma (B) 3 ma (C) 9 ma (D) 4 ma Q. 67 The longest wavelength that can be absorbed by silicon, which has the bandgap of. ev, is. mm. If the longest wavelength that can be absorbed by another material is 0.87 mm, then bandgap of this material is (A). 46 A/cm (B) ev (C) ev (D) ev Q. 68 The neutral base width of a bipolar transistor, biased in the active region, is 0.5 mm. The maximum electron concentration and the diffusion constant in the base are 0 4 / cm 3 and Dn 5 cm /sec respectively. Assuming negligible recombination in the base, the collector current density is (the electron charge is 6. # 0-9 Coulomb) (A) 800 A/cm (B) 8 A/cm (C) 00 A/cm (D) A/cm 003 ONE MARK Q. 69 n-type silicon is obtained by doping silicon with (A) Germanium (B) Aluminium (C) Boron (D) Phosphorus Q. 70 The Bandgap of silicon at 300 K is (A).36 ev (C) 0.80 ev (B).0 ev (D) 0.67 ev

14 Q. 7 The intrinsic carrier concentration of silicon sample at 300 K is 5. # 0 6 /m 3. If after doping, the number of majority carriers is 5# 0 0 /m 3, the minority carrier density is (A) 450. # 0 /m 3 (B) # 0 4 /m 3 (C) 500. # 0 0 /m 3 (D) 300. # 0-5 /m 3 Q. 7 Choose proper substitutes for X and Y to make the following statement correct Tunnel diode and Avalanche photo diode are operated in X bias ad Y bias respectively (A) X : reverse, Y : reverse (B) X : reverse, Y : forward (C) X : forward, Y : reverse (D) X : forward, Y : forward Q. 73 For an n - channel enhancement type MOSFET, if the source is connected at a higher potential than that of the bulk (i.e. VSB > 0), the threshold voltage V T of the MOSFET will (A) remain unchanged (B) decrease (C) change polarity (D) increase 003 TWO MARKS Q. 74 An n -type silicon bar 0. cm long and 00 m m i cross-sectional area has a majority carrier concentration of 5# 0 0 /m and the carrier mobility is 0.3 m /V-s at 300 K. If the charge of an electron is 5. # 0-9 coulomb, then the resistance of the bar is (A) 0 6 Ohm (B) 0 4 Ohm (C) 0 - Ohm (D) 0-4 Ohm Q. 75 The electron concentration in a sample of uniformly doped n-type silicon at 300 K varies linearly from 0 7 /cm 3 at x 0 to 6# 0 6 /cm 3 at x mm. Assume a situation that electrons are supplied to keep this concentration gradient constant with time. If electronic charge is 6. # 0-9 coulomb and the diffusion constant Dn 35 cm /s, the current density in the silicon, if no electric field is present, is (A) zero (B) - A/cm (C) +0 A/cm (D) -0 A/cm Q. 76 Match items in Group with items in Group, most suitably. Group Group P. LED. Heavy doping Q. Avalanche photo diode. Coherent radiation R. Tunnel diode 3. Spontaneous emission S. LASER 4. Current gain (A) P -, Q -, R - 4, S - 3 (B) P -, Q - 3, R -, S - 4 (C) P - 3 Q - 4, R -, S - (D) P -, Q -, R - 4, S - 3

15 Q. 77 At 300 K, for a diode current of ma, a certain germanium diode requires a forward bias of V, whereas a certain silicon diode requires a forward bias of 0.78 V. Under the conditions state above, the closest approximation of the ratio of reverse saturation current in germanium diode to that in silicon diode is (A) (B) 5 (C) 4# 0 3 (D) 8# 0 3 Q. 78 A particular green LED emits light of wavelength 5490 Ac. The energy bandgap of the semiconductor material used there is - (Plank s constant # 0 34 J-s) (A).6 ev (B).98 ev (C).7 ev (D) 0.74 ev Q. 79 When the gate-to-source voltage ( V Gs ) of a MOSFET with threshold voltage of 400 mv, working in saturation is 900 mv, the drain current is observed to be ma. Neglecting the channel width modulation effect and assuming that the MOSFET is operating at saturation, the drain current for an applied V GS of 400 mv is (A) 0.5 ma (B).0 ma (C) 3.5 ma (D) 4.0 ma Q. 80 If P is Passivation, Q is n -well implant, R is metallization and S is source/ drain diffusion, then the order in which they are carried out in a standard n -well CMOS fabrication process, is (A) P-Q-R- S (B) Q-S-R-P (C) R-P-S- Q (D) S-R-Q-P Q. 8 The action of JFET in its equivalent circuit can best be represented as a (A) Current controlled current source (B) Current controlled voltage source (C) Voltage controlled voltage source (D) Voltage controlled current source 00 ONE MARK Q. 8 In the figure, silicon diode is carrying a constant current of ma. When the temperature of the diode is 0c CV, D is found to be 700 mv. If the temperature rises to 40c CV, D becomes approximately equal to (A) 740 mv (C) 680 mv (B) 660 mv (D) 700 mv

16 Q. 83 If the transistor in the figure is in saturation, then (A) I C is always equal to b dc I B (B) I C is always equal to -b de I B (C) I C is greater than or equal to b dc I B (D) I C is less than or equal to b dc I B 00 ONE MARK Q. 84 MOSFET can be used as a (A) current controlled capacitor (B) voltage controlled capacitor (C) current controlled inductor (D) voltage controlled inductor Q. 85 The effective channel length of MOSFET in saturation decreases with increase in (A) gate voltage (B) drain voltage (C) source voltage (D) body voltage 999 ONE MARK Q. 86 The early effect in a bipolar junction transistor is caused by (A) fast turn-on (B) fast turn-off (C) large collector-base reverse bias (D) large emitter-base forward bias 999 TWO MARKS Q. 87 An n-channel JEFT has I DSS ma and V p - 4V. Its transconductance g m (in milliohm) for an applied gate-to-source voltage V GS of - V is (A) 0.5 (B) 0.5 (C) 0.75 (D).0 Q. 88 An npn transistor (with C 0.3 pf) has a unity-gain cutoff frequency f T of 400 MHz at a dc bias current I c ma. The value of its C m ( in pf) is approximately ( V T 6 mv) (A) 5 (B) 30 (C) 50 (D) 96

17 998 ONE MARK Q. 89 The electron and hole concentrations in a intrinsic semiconductor are n i and p i respectively. When doped with a p-type material, these change to n and p, respectively, Then (A) n+ p ni+ pi (B) n+ ni p+ p i (C) np n p (D) np n p i i Q. 90 The f T of a BJT is related to its gm, CpandCm as follows Cp C (A) ft + m p( Cp+ Cm) (B) ft gm gm gm gm (C) ft (D) f C p+ T C m p( Cp+ Cm) Q. 9 The static characteristic of an adequately forward biased p-n junction is a straight line, if the plot is of (A) log I vs log V (B) log I vsv (C) I vs log V (D) I vsv Q. 9 A long specimen of p-type semiconductor material (A) is positively charged (B) is electrically neutral (C) has an electric field directed along its length (D) acts as a dipole Q. 93 Two identical FETs, each characterized by the parameters gm and rd are connected in parallel. The composite FET is then characterized by the parameters g (A) and r m gm d (B) and rd (C) g and rd m (D) g and r m d q Q. 94 The units of are kt (A) V (B) V - (C) J (D) JK / i i 997 ONE MARK Q. 95 For a MOS capacitor fabricated on a p-type semiconductor, strong inversion occurs when (A) surface potential is equal to Fermi potential (B) surface potential is zero (C) surface potential is negative and equal to Fermi potential in magnitude (D) surface potential is positive and equal to twice the Fermi potential 0 3 Q. 96 The intrinsic carrier density at 300 K is.5 # 0 /cm, in silicon. For n-type 5 3 silicon doped to.5 # 0 atoms/ cm, the equilibrium electron and hole densities are (A) n.5 # 0 5 / cm 3, p.5 # 0 0 / cm 3 (B) n.5 # 0 0 / cm 3, p.5 # 0 5 / cm 3 (C) n.5 # 0 5 / cm 3, p.0 # 0 5 / cm 3

18 (D) n.5 # 0 / cm, p.5 # 0 / cm ONE MARK Q. 97 The p-type substrate in a conventional pn-junction isolated integrated circuit should be connected to (A) nowhere, i.e. left floating (B) a DC ground potential (C) the most positive potential available in the circuit (D) the most negative potential available in the circuit Q. 98 If a transistor is operating with both of its junctions forward biased, but with the collector base forward bias greater than the emitter base forward bias, then it is operating in the (A) forward active mode (B) reverse saturation mode (C) reverse active mode (D) forward saturation mode Q. 99 The common-emitter short-circuit current gain b of a transistor (A) is a monotonically increasing function of the collector current I C (B) is a monotonically decreasing function of I C (C) increase with I C, for low I C, reaches a maximum and then decreases with further increase in I C (D) is not a function of I C Q. 00 A n-channel silicon ( E g. ev) MOSFET was fabricated using n +poly-silicon gate and the threshold voltage was found to be V. Now, if the gate is changed to p + poly-silicon, other things remaining the same, the new threshold voltage should be (A) - 0. V (B) 0V (C).0 V (D). V 996 TWO MARKS Q. 0 In a bipolar transistor at room temperature, if the emitter current is doubled the voltage across its base-emitter junction (A) doubles (B) halves (C) increases by about 0 mv (D) decreases by about 0 mv Q. 0 An npn transistor has a beta cut-off frequency f b of MHz and common emitter short circuit low-frequency current gain b o of 00 it unity gain frequency f T and the alpha cut-off frequency f a respectively are (A) 00 MHz, 0 MHz (B) 00 MHz, 99 MHz (C) 99 MHz, 00 MHz (D) 0 MHz, 00 MHz

19 Q. 03 A silicon n MOSFET has a threshold voltage of V and oxide thickness of Ao [ er ( SiO) 3.9, e # 0 F/ cm, q.6 # 0 C] The region under the gate is ion implanted for threshold voltage tailoring. The dose and type of the implant (assumed to be a sheet charge at the interface) required to shift the threshold voltage to - V are (A).08 # 0 /cm, p-type (B).08 # 0 /cm, n-type (C) 54. # 0 /cm, p-type (D) 54. # 0 /cm, n-type ***********

20 SOLUTIONS Sol. Sol. Sol. 3 Sol. 4 Sol. 5 The potential barrier of the pn junction is lowered when a forward bias voltage is applied, allowing electrons and holes to flow across the space charge region (Injection) when holes flow from the p region across the space charge region into the n region, they become excess minority carrier holes and are subject to diffuse, drift and recombination processes. In IC technology, dry oxidation as compared to wet oxidation produces superior quality oxide with a lower growth rate In a MOSFET operating in the saturation region, the channel length modulation effect causes a decrease in output resistance. Given, V B V V TN V So, we have Drain voltage V D volt V G volt V S 0 (Ground) Therefore, V GS > V TN and V DS > V GS -V TN So, the MOSFET is in the saturation region. Therefore, drain current is I D kn^vgs -VTNh or, I D kn ^V B - h Differentiating both side with respect to I D k V dvb N^ B-h did Since, V BQ volt (at D.C. Voltage) Hence, we obtain dvb di -6 D kn^vb- h # 40# 0 # ^- h.5 # 0 3 W.5 kw For the semiconductor, np 0 0 n i 0 p ni per cm n Volume of given device, V Area # depth mm # mm 0-8 cm # 0-4 cm 0 - cm 3 So total no. of holes is,

21 Sol. 6 - p p0 # V 0 # 0 Which is approximately equal to zero. Given the circuit as below : 0 - Since all the parameters of PMOS and NMOS are equal. So, m n mp C W OX b L l C W C W OX b OX M L l b L l M Given that M is in linear region. So, we assume that M is either in cutoff or saturation. Case : M is in cut off So, I I 0 Where I is drain current in M and I is drain current in M. mpcox Since, I W V V V V SD SG Tp SD b - - L l8 ^ h B mpcox & 0 W [ V SD V SG V Tp V SD] b - - L l ^ h Solving it we get, ^VSG - VTph V SD & 5 ^ -Vin -h 5 -VD & VD + 3 For I 0, V D 5V So, V in V So for the NMOS V GS Vin V and VGS > V So it can t be in cutoff region. Case : M must be in saturation region. So, I I V in mpcox W ( V V ) SG Tp SD SD L ( V GS - V Tn) L & ( VSG -VTp) VSD - VSD ( VGS -VTn) & 5 ( -Vin -)( 5-VD) -( 5- VD) ( Vin -0-) & 4 ( -Vin)( 5-VD) -( 5- VD) ( Vin -) Substituting VD VDS VGS - VTn and for N -MOS & VD Vin- & 4 ( -V )( 6-V )-( 6- V ) ( V -) in in in in Tn

22 Sol. 7 Sol. 8 Sol. 9 Sol. 0 & V in - Vin + & 6V in & V in.833 V 6 So for M to be in saturation V in <.833 V or V in <.875 V Gate source overlap capacitance. C W ox 0 o d e e (medium Sio t ) ox # 0 - # # 0 - # 3. 9 # 8. 9 # # 0 F # 0 Source body junction capacitance. C s Aee r 0 d A (0. mm+ 0. mm+ 0. mm) # mm+ (0. mm# 0. mm) 0.68 mm d 0 nm (depletion width of all junction) C s # - # # # # 0 F 0 # 0 Drift current I d qnm n E It depends upon Electric field E and carrier concentration n Zener diode operates in reverse breakdown region. Sol. Sol. For every c C increase in temperature, forward bias voltage across diode decreases by.5 mv. Thus for 0c C increase, there us 5 mv decreases. Full channel resistance is r r # L 600 W...() W # a If V GS is applied, Channel resistance is r L rl # where b a VGS W# b c - V m p Pinch off voltage, qn V p a...() e D

23 Sol. 3 Sol. 4 Sol. 5 Sol. 6 Sol. 7 Sol. 8 If depletion on each side is d μm at VGS 0. qn V j d e D qnd - qnd or ( 0 ) & 0 e # e Now from equation (), we have - V p 0 #( 5 # 0 ) or V p -5 V At V GS - 3V; 6 b 5b - -3 mm 3.6mm - 5 l 6 rl rl rl a W# b Wa # b # 97 W 36. At V GS 0V, b 4mm since b 8mm Thus rl rl a Wa # b # 750 W 4 At room temperature mobility of electrons for Si sample is given m n 350 cm / Vs. For an n-channel MOSFET to create an inversion layer of electrons, a large positive gate voltage is to be applied. Therefore, induced electric field increases and mobility decreases. So, Mobility m n < 350 cm / Vs for n-channel MOSFET Dry oxidation is used to achieve high quality oxide growth. Emitter injection efficiency is given as g + N N B E To achieve g, NE >> NB Reverse bias breakdown or Zener effect occurs in highly doped PN junction through tunneling mechanism. In a highly doped PN junction, the conduction and valence bands on opposite sides of the junction are sufficiently close during reverse bias that electron may tunnel directly from the valence band on the p-side into the conduction band on n-side. Breakdown voltage V N B \ AND So, breakdown voltage decreases as concentration increases Depletion capacitance / C e snand e ' ( Vbi + VR)( NA + ND) Thus C \ N A N D Depletion capacitance increases as concentration increases Sample is in thermal equilibrium so, electric field

24 Sol. 9 Sol. 0 Sol. Sol. Sol. 3 Sol. 4 Sol. 5 Sol. 6 Sol. 7 E 0 kv/ cm mm Electron drift current density J d NDmneE 0 # 350 #. 6 # 0 # 0 # # 0 Acm / Only dopant atoms can have concentration of 4# 0 9 cm - 3 in n -type silicon at room temperature. Unit of mobility m n is cm V. sec Unit of diffusion current D n is cm sec mn Thus unit of is cm / cm V Dn V$ sec sec V - Both S and S are true and S is a reason for S. We know that N A W P N D W N 7-6 or N NDWN A # # # -6 # 0 WP # 0 The built-in potential is V bi V T n NAND c n m i ln 0 0 # # # # e 0 o (. 4# 0 ) The peak electric field in device is directed from p to n and is E endxn - from p to n es endxn from n to p es # 0 # # 0 # # MV/cm 885. # 0 # Channel length modulation is not associated with a p- n junction. It is being associated with MOSFET in which effective channel length decreases, producing the phenomenon called channel length modulation. Trivalent impurities are used for making p - type semiconductors. So, Silicon wafer heavily doped with boron is a p + substrate. Oxidation rate is zero because the existing oxide prevent the further oxidation.

25 Sol. 8 Sol. 9 Sol. 30 Sol. 3 Sol. 3 Sol. 33 Sol. 34 Sol. 35 g ID m ( ) V V KV GS - V T KV ( GS -VT ) GS GS As V D constant Thus g m \ ( VGS - VT ) Which is straight line. E- E kt ln NA n i N A 4# 0 7 n i 5. # E- E 5 0 e ln 4 0 # # ev 5. # 0 Hence fermi level goes down by 0.47 ev as silicon is doped with boron. Pinch off voltage V ew N D P es Let V P V P Now VP W W VP W ( W) or 4V P V P Initial transconductance g m K Vbi VGS n - - ; V E p 0-( -) For first condition g m K K n - n V G ; - P V E P For second condition 0-( -) g m K K V 4V n - G ; - E P P gm - / VP Dividing g f p m - /( VP) Hence V P V P As per mass action law np n i If acceptor impurities are introduces p N A Thus nn A n i or n ni NA The electric field has the maximum value at the junction of p + n.

26 Zener diode and Avalanche diode works in the reverse bias and laser diode works in forward bias. In solar cell diode works in forward bias but photo current is in reverse direction. Thus Zener diode : Reverse Bias Solar Cell : Forward Bias Laser Diode : Forward Bias Avalanche Photo diode : Reverse Bias Sol. 36 Sol. 37 Sol. 38 In BJT as the B-C reverse bias voltage increases, the B-C space charge region width increases which x B (i.e. neutral base width) > A change in neutral base width will change the collector current. A reduction in base width will causes the gradient in minority carrier concentration to increase, which in turn causes an increased in the diffusion current. This effect si known as base modulation as early effect. In JFET the gate to source voltage that must be applied to achieve pinch off voltage is described as pinch off voltage and is also called as turn voltage or threshold voltage. In LASER population inversion occurs on the condition when concentration of electrons in one energy state is greater than that in lower energy state, i.e. a non equilibrium condition. In MOS capacitor, flat band voltage is the gate voltage that must be applied to create flat ban condition in which there is no space charge region in semiconductor under oxide. Therefore BJT : Early effect MOS capacitor : Flat-band voltage LASER diode : Population inversion JFET : Pinch-off voltage W K V+ V R Now m K From above two equation we get W m or W 4 m m b a b Current Gain Base Transport Factor # Emitter injection Efficiency a b# b or b a b 5 #

27 Sol. 39 Sol. 40 At low voltage when there is no depletion region and capacitance is decide by SiO thickness only, 0 r C ee A D r or D ee A 3. 5 # 0 # 0-50 nm C 7# 0 The construction of given capacitor is shown in fig below Sol. 4 Sol. 4 When applied voltage is 0 volts, there will be no depletion region and we get C 7 pf When applied voltage is V, a depletion region will be formed as shown in fig an total capacitance is pf. Thus C T pf or C CC T pf C + C or + CT C C Substituting values of C T and C we get C 7 pf 6 0 r Now D A ee C 4 # 0 - # # 0 4 cm 6 # mm Depletion region will not be formed if the MOS capacitor has n type substrate but from C-V characteristics, C reduces if V is increased. Thus depletion region must be formed. Hence S is false If positive charges is introduced in the oxide layer, then to equalize the effect the applied voltage V must be reduced. Thus the C- V plot moves to the left. Hence S is true. For the case of negative slope it is the negative resistance region

28 Sol. 43 Sol. 44 Sol. 45 Sol. 46 Sol. 47 Sol. 48 Sol. 49 For n-type p is minority carrier concentration np n i np Constant Since n i is constant p \ n Thus p is inversely proportional to n. Diffusion current, since the drift current is negligible for minority carrier. In BJT as the B-C reverse bias voltage increases, the B-C space charge region width increases which x B (i.e. neutral base width) > A change in neutral base width will change the collector current. A reduction in base width will causes the gradient in minority carrier concentration to increases, which in turn causes an increases in the diffusion current. This effect si known as base modulation as early effect. For t < 0 diode forward biased and VR 5. At t 0 diode abruptly changes to reverse biased and current across resistor must be 0. But in storage time 0 < t < t s diode retain its resistance of forward biased. Thus for 0 < t < t s it will be ON and V R - 5 V According to Hall effect the direction of electric field is same as that of direction of force exerted. E -v# B or E B# v The varacter diode is used in tuned circuit as it can provide frequently stability. PIN diode is used as a current controlled attenuator. Zener diode is used in regulated voltage supply or fixed voltage reference. Schottkey diode has metal-semiconductor function so it has fast switching action so it is used as high frequency switch Varactor diode : Tuned circuits PIN Diode : Current controlled attenuator Zener diode : Voltage reference Schottky diode : High frequency switch We have m m P n 04.

29 Sol. 50 Sol. 5 Sol. 5 Sol. 53 Sol. 54 Sol. 55 Sol. 56 Conductance of n type semiconductor s n nqm n Conductance of intrinsic semiconductor Ratio is s i nq i ( m n + m p ) sn nmn n s n ( m + m ) n ^ i i n p i + m m 4. # #. 5 # 0 ( ) 8 For silicon at 0 K, E g0. ev At any temperature -4 E gt Eg0-36. # 0 T At T 300 K, -4 E g # 0 # 300. ev This is standard value, that must be remembered. The reverse saturation current doubles for every 0c C rise in temperature as follows : ( T-T)/ 0 I0 ( T) I0 # Thus at 40c C, I0 40 pa Silicon is abundant on the surface of earth in the from of SiO. s n p n h 4 nqm n pqm p ( n p) mp m 3 s p sp sn n 0 r C eea d - or C 0 r ee 885. # 0 # A d -6 mf 0 # 0 In accumulation mode for NMOS having p -substrate, when positive voltage is applied at the gate, this will induce negative charge near p - type surface beneath the gate. When V GS is made sufficiently large, an inversion of electrons is formed and this in effect forms and n - channel. From the graph it can be easily seen that Vth V Now V GS 3- V and V DS 5-4 V Since V DS > VGS $ VDS > VGS - Vth Thus MOSFET is in saturation region.

30 Sol. 57 Sol. 58 Sol. 59 Sol. 60 Sol. 6 Sol. 6 Sol. 63 Sol. 64 Trivalent impurities are used for making p type semiconductor. Boron is trivalent. Here emitter base junction is forward biased and base collector junction is reversed biased. Thus transistor is operating in normal active region. We have b a - a Thus a -" b - a." b. If the base width increases, recombination of carrier in base region increases and a decreases & hence b decreases. If doping in base region increases, recombination of carrier in base increases and a decreases thereby decreasing b. Thus S is true and S is false. Applying KVL we get VCC -IC RC - VCE 0 or I VCC VCE C ma RC k Now I IC.8 B m 56 ma b 50 We know that WN p A WN n D or W Wn ND p # NA 6 3m # mm 6 9# 0 Conductivity s nqu n or resistivity r s nqm n Thus n qrm n. 6 # 0 # 0. 5 # 50 /cm - 3 For n type semiconductor n N D We know that C e N N S A D j e ; ( Vbi + VR)( NA + ND) E Thus C j \ ( Vbi + VR) Cj ( Vbi + VR) Now Cj ( Vbi + VR) 4 Cj or C j 0.5 pf

31 Sol. 65 Sol. 66 Sol. 67 Sol. 68 Increase in gate oxide thickness makes difficult to induce charges in channel. Thus V T increases if we increases gate oxide thickness. Hence S is false. Increase in substrate doping concentration require more gate voltage because initially induce charges will get combine in substrate. Thus V T increases if we increase substrate doping concentration. Hence S is false. We know that I D KV ( GS -VT ) Thus IDS ( VGS - VT ) I DI ( VGS - VT ) Substituting the values we have ID ( 3- ) 4 I D ( - ) or I D 4I 4 ma E g \ l Eg Thus l. Eg l 087. or E g. #.. 46 ev 087. DI Concentration gradient 4 dn 0 dx # 0 - q 6. # 0 9 C D n 5 4 dn 0 dx # 0 J C qd dn n dx # # 0 # 5 # # 0 8 A/cm Sol. 69 Sol. 70 Sol. 7 Pentavalent make n -type semiconductor and phosphorous is pentavalent. For silicon at 0 K Eg0. ev At any temperature -4 E gt Eg0-36. # 0 T At T 300 K, -4 E g # 0 # 300. ev This is standard value, that must be remembered. By Mass action law np n i

32 Sol. 7 Sol. 73 Sol. 74 Sol. 75 p n i n # 0 # 5. # # 0 5# 0 Tunnel diode shows the negative characteristics in forward bias. It is used in forward bias. Avalanche photo diode is used in reverse bias. rl We that R, r and a nqu A s n From above relation we have R nqm n A - 0. # W # 0 #. 6 # 0 # 0. 3 # 00 # dn 6# dx - # # 0-0 Now J n nqm E D q dn e + n dx Since no electric field is present, E 0 and we get So, J n qd dn n dx # 0 # 35 #(- # 0 ) - 0 A/cm Sol. 76 Sol. 77 Sol. 78 LED works on the principal of spontaneous emission. In the avalanche photo diode due to the avalanche effect there is large current gain. Tunnel diode has very large doping. LASER diode are used for coherent radiation. VD h We know that I Io `e V si T - j where h for germanium and h silicon. As per question VDsi V I ee T - VDGe ` h j I `ehv T -j or on I I o o si si e e E g oge VDsi hvt VDGe hvt hc l - - e e # 6# # 0 3-4# # 0 # 3 # J # 0 E ( J) -9 g In ev Eg ( ev) 36. # ev e 6. # 0 Alternatively 3

33 Sol. 79 Sol. 80 Sol. 8 Sol. 8 Sol. 83 Sol. 84 Sol. 85 Sol. 86 E g 4. ev ev lmm ( ) 5490 # 0 mm We know that I D KV ( GS -VT ) Thus ID ( VGS - VT ) I D ( VGS - VT ) Substituting the values we have ID ( ) 4 I D ( ) or I D 4I DI 4 ma In n -well CMOS fabrication following are the steps : (A) n - well implant (B) Source drain diffusion (C) Metalization (D) Passivation For a JFET in active region we have I DS I VGS DSS c - V m P From above equation it is clear that the action of a JFET is voltage controlled current source. At constant current the rate of change of voltage with respect to temperature is dv - 5. mv per degree centigrade dt Here 3 T T- T cC Thus 3 V D - 5. # 0 50 mv Therefore, V D mv Condition for saturation is IC < bib The metal area of the gate in conjunction with the insulating dielectric oxide layer and semiconductor channel, form a parallel plate capacitor. It is voltage controlled capacitor because in active region the current voltage relationship is given by I DS KV ( GS -VT ) In MOSFET the body (substrate) is connected to power supply in such a way to maintain the body (substrate) to channel junction in cutoff condition. The resulting reverse bias voltage between source and body will have an effect on device function. The reverse bias will widen the depletion region resulting the reduction in channel length.

34 Sol. 87 Sol. 88 Sol. 89 Sol. 90 Sol. 9 Sol. 9 Sol. 93 Sol. 94 Sol. 95 Sol. 96 At a given value of v BE, increasing the reverse-bias voltage on the collector-base junction and thus increases the width of the depletion region of this junction. This in turn results in a decrease in the effective base width W. Since I S is inversely proportional to W, I S increases and that i C increases proportionally. This is early effect. For an n-channel JEFT trans-conductance is g IDSS VGS m ( ) V b P V l - # # - P -4 - ( - 4) G 0-3 # 0.5 mho We have g IC m V 6 T gm Now f T p( Cp+ Cm) 6 / or p(. 0 3# 0 + C m ) - or (0.3 # 0 + C m ) p 400 # # # or C m 5.3 # # 0 5 # 0 5 pf For any semiconductor (Intrinsic or extrinsic) the product np remains constant at a given temperature so here np np i i gm f T p( Cp+ Cm) For a Forward Bias p-n junction, current equation / I I ( e VkT -) or I I + e / 0 0 VkT or kt logbi I + l V 0 So if we plot log I vs V we get a straight line. A specimen of p - type or n - type is always electrical neutral. The unit of q is e and unit of kt is ev. Thus unit of e/ kt is e/ ev V We have n i.5 # 0 /cm 5 3 N d.5 # 0 atoms/ cm

35 Sol. 97 Sol. 98 For n type doping we have electron concentration For a given temperature Hole concentration n -.5 # 0 atom/ cm np n i p n i n N d (. 5 0 ) # 5.0 # 0 /cm 5. # In pn-junction isolated circuit we should have high impedance, so that pn junction should be kept in reverse bias. (So connect p to negative potential in the circuit) Sol. 99 Sol. 00 Sol. 0 If both junction are forward biased and collector base junction is more forward biased then I C will be flowing out wards (opposite direction to normal mode) the collector and it will be in reverse saturation mode. For normal active mode we have b IC I B For small values of I C, if we increases I C, b also increases until we reach ( I C ) saturation. Further increases in I C (since transistor is in saturation mode know) will increases I B and b decreases. For a n-channel mosfet thresholds voltage is given by V TN VGS -VDS ( sat) for p-channel [p + polysilicon used in gate] V TP VSD( sat) -VGS so V TP - VDS ( sat) + VGS so threshold voltage will be same. Emitter current is given by I E I ( e V BE 0 / kt -) or I E Ie V BE / kt e V / or V BE kt ln b I l Now ( V BE ) kt ln I E b I l 0 ( V BE ) kt ln I E b I l 0 or ( VBE) - ( VBE) kt ln IE ; b kt ln I le b I I E E Now if emitter current is double i.e. I E I E 0 I E 0 E l BE kt >>

36 Sol. 0 Sol. 03 ( V BE ) ( V BE ) + (5 # 0.60) m volt ( V BE ) + 5 m volt Thus if emitter current is doubled the base emitter junction voltage is increased by 5 mv. Unity gain frequency is given by f T f B # b 0 6 # MHz a-cutoff frequency is given by fb fb f a f ( b + ) - a - b b b+ 0 6 # (00 + ) 0 MHz ***********