Semiconductor Devices. C. Hu: Modern Semiconductor Devices for Integrated Circuits Chapter 5

Transcription

1 Semiconductor Devices C. Hu: Modern Semiconductor Devices for Integrated Circuits Chapter 5

2 Global leader in environmental and industrial measurement Wednesday 3.2. afternoon Tour around facilities & lecture Room for 20 students Registration in Oodi (first 20 enrolled, binding)

3 Introduction Operation regimes Accumulation, flat-band, depletion, threshold, inversion - BREAK - C-V characteristics Unidealities Oxide charge, gate depletion, quantum mechanical effect

4 The most important building block in today s semiconductor technology Consists of gate (metal or polysilicon) an oxide layer (as thin as 1.5 nm) silicon substrate MOS capacitor MOS capacitor + 2 n + -regions MOSFET (by far the most widely used device) MOS transistor

5 3 different operation regimes Accumulation, depletion, inversion 2 interesting transition points between them Flat-band, threshold FLAT-BAND THRESHOLD

6 When the pieces are separate Gate and body E c & E v at the same level, E F at different level No electric field in oxide and body When the pieces are joined Electrons move from gate to body (difference in E F ) Gate surface +, body surface Electric field, depletion region, band bending

7 Energy bands are flattened due to an applied voltage V fb V fb < 0 (N + -gate, P-body) No electric field in the substrate and in the oxide Important concepts Vacuum level Electron affinity Work function V fb = Ψ g Ψ s (difference between work functions)

8 If V g < V fb Gate negatively charged Positive charge accumulates to the oxide semiconductor interface Band bending E F closer to E v near the interface Surface hole concentration p s larger than bulk hole concentration p 0 q / kt p s s N e a

9 Large number of holes at or near the surface Accumulation layer formation Gate voltage now V V V g fb s ox s : surface potential, band bending (negligible in accumulation) V ox : voltage across the oxide V Q / C ox s ox

10 If V g > V fb Gate positively charged Positive charge repels the holes in the body near the interface (negatively charged ionized acceptors are left behind) Depletion layer is formed Band bending W dep 2 s s qn a s qn W a 2 s 2 dep E F far from both, E v and E c V ox Qdep qnawdep qna 2 s s C C C ox ox ox

11 Threshold (of inversion): n s = N a, or (E c ) surface = ( E v ) bulk, or A=B, and C = D i a a v i v bulk v f g B n N q kt N N q kt n N q kt E E E q ln ln ln ) ( 2 i a B st n N q 2 kt ln 2

12 ox B s a B fb g t C qn V threshold at V V ox s fb g V φ V V At threshold, i a B st n N q 2 kt ln 2 ox B s a ox C qn V 2 2

13 V t V fb 2 B qn sub C 2 2 ox s B + for P-body, for N-body

14 V g > V t V V V V g fb s ox fb s 0 qs / kt dep Q qna 2 inv s s ns e fb s Vfb s Cox Cox Cox Cox Q C sub Q V ox Surface potential and depletion region width do not change significantly as the gate voltage increases Inversion is the most important operating regime because transistors operate in it max 2 s 2 W B dep qn a

15 In strong inversion the charge in the substrate consists of the depletion region charge (=ionized donors) and the inversion layer charge (=electrons at the interface) Qdep Q qna 2s 2 inv B Q Vg Vfb 2B Vfb 2B C C C C Q ox ox ox ox inv V t Q C inv Cox Vg Vt ox inv This is the important so called capacitor law based on which one can calculate e.g. the amount of electrons in the channel of an MOS-transistor.

16 Typically MOS-transistors are enhancement-type devices where the threshold voltage is positive With p-type substrate Vg<Vt => no current Vg>Vt => conducting channel is formed V t is generally set at a small positive value so that, at V g = 0, the transistor does not have an inversion layer and current does not flow between the two N + regions

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19 s 2 B V f accumulation depletion inversion b t W dep V V g W dmax W dmax = (2 s 2 B /qn a 1/2 s ) 1/2 V fb V t accumulation depletion inversion V g

20 Q dep =- qn a W dep (a) V fb accumulation depletion inversion qn a W dep 0 V t qnawdmax V g total substrate charge, Q s Q s Q acc Q dep Q inv Q inv Q s (b) accumulation depletion inversion V fb V t V g accumulation regime depletion regime inversion regime slope = C ox V fb 0 V t V g Q acc slope = C ox Q inv (c) V fb V t slope = C ox accumulation depletion inversion V g

21 The most important parameters of MOS capacitor can be experimentally defined with C-V measurements Oxide thickness Flat-band voltage Threshold voltage C-V Meter MOS Capacitor C dq dv g g dq dv s g

22 C dq dv g g dq dv s g Q s accumulation regime depletion regime inversion regime C ox C V fb 0 V t V g Q inv slope = C ox V fb accumulation depletion inversion V t V g

23 C ox C In the depletion regime: V fb accumulation depletion inversion V t C C ox C dep V g 1 C 1 C 2 ox 2( V g qn V a s fb )

24 Supply of inversion charge may be limited

25 With high frequencies the inversion charge is not able to follow the changes in the voltage Thermal generation at a very slow rate With low frequencies the situation is different

26 C MOS transistor CV, QS CV HF capacitor CV Does the QS CV or the HF capacitor CV apply? V g (1) MOS transistor, 10kHz. (2) MOS transistor, 100MHz. (3) MOS capacitor, 100MHz. (4) MOS capacitor, 10kHz. (5) MOS capacitor, slow V g ramp. (6) MOS transistor, slow V g ramp.

27 C MOS transistor CV, QS CV HF capacitor CV Does the QS CV or the HF capacitor CV apply? V g (1) MOS transistor, 10kHz. (Answer: QS CV). (2) MOS transistor, 100MHz. (Answer: QS CV). (3) MOS capacitor, 100MHz. (Answer: HF capacitor CV). (4) MOS capacitor, 10kHz. (Answer: HF capacitor CV). (5) MOS capacitor, slow V g ramp. (Answer: QS CV). (6) MOS transistor, slow V g ramp. (Answer: QS CV).

28 Electric charge in the gate dielectric changes the flat band voltage and therefore also the threshold voltage V Q Q V 0 ox ox fb fb g s Cox Cox

29 Types of oxide charge Fixed oxide charge, Si + Mobile oxide charge, due to Na + contamination Interface traps, neutral or charged depending on Vg Voltage/temperature stress induced charge and traps--a reliability issue

30 C There is a thin depletion region also in the polysilicon gate T W ox dpoly C C T W ox poly ox s ox dpoly Q C V V inv ox g poly t ox /3 With small operating voltages (~ 1V) this has to be taken into account

31 The charge density maximum is not located right at the interface but deeper in the semiconductor Effective oxide thickness changes

32 T inv is a function of the average electric field in the inversion layer, which is (V g + V t )/6T ox T inv of holes is larger than that of electrons because of difference in effective mass T oxe is the electrical oxide thickness T T W / 3 T / 3 oxe ox dpoly inv Q C V V V V ox inv oxe g t g t Toxe

33 C poly C ox C ox C poly C ox C ox C dep C dep C inv C dep, min C inv C inv General case for both depletion and inversion regions. In the depletion regions V g V t Strong inversion

34 If the voltage is applied suddenly, there is not enough time for the inversion charge to form Deep depletion By applying light, charges can be generated at the interface

35 N-type device: N + -polysilicon gate over P-body P-type device: P + -polysilicon gate over N-body Vfb g s ( Qox / Cox) V g V fb V s ox poly V fb s Q s / C ox poly

36 st 2 B B kt ln q N n sub i V t V fb st qn sub C 2 ox s st + : N-type device, : P-type device

37 (N -gate over P-substrate) (P -gate over N-substrate) Accumulation V g <V fb<0 Flat-band V g >V fb >0 V g =V fb >0 V g =V fb <0 N-type Device (N + -gate over P-substrate) P-type Device (P + -gate over N-substrate) V g =V fb <0 V g 0>V fb f Flat-band Depletion V g =V fb >0 V g 0<V fb Depletion V g 0>V fb V g =V t >0 Threshold V g 0<V fb V g =V t <0 V What s V g =V the t >0 diagram like at V g > g =V t? t <0 at V g = 0? Threshold V g >V t >0 Inversion V g <V t

38 N-type Device (N + -gate over P-substrate) P-type Device (P + -gate over N-substrate) QS CV Transistor CV Capacitor (HF) CV V g V g What is the root cause of the low C in the HF CV branch?

39 MOSFET